EP2003836B1 - Transmission et réception de données numériques contenant des symboles à priorités différentes - Google Patents

Transmission et réception de données numériques contenant des symboles à priorités différentes Download PDF

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Publication number
EP2003836B1
EP2003836B1 EP08010913.5A EP08010913A EP2003836B1 EP 2003836 B1 EP2003836 B1 EP 2003836B1 EP 08010913 A EP08010913 A EP 08010913A EP 2003836 B1 EP2003836 B1 EP 2003836B1
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Prior art keywords
group data
block
bit
reliability
mapping
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EP08010913.5A
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German (de)
English (en)
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EP2003836A2 (fr
EP2003836A3 (fr
Inventor
Jong-Soo Choi
Yan Xin
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR1020070088209A external-priority patent/KR101409571B1/ko
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Publication of EP2003836A3 publication Critical patent/EP2003836A3/fr
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
    • H03M13/356—Unequal error protection [UEP]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/007—Unequal error protection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

Definitions

  • the present invention generally relates to an apparatus and method for transmitting and receiving data in a mobile communication system. More particularly, but not exclusively, the present invention relates to a data transmission apparatus and method and a corresponding data reception apparatus and method, for improving system performance in a mobile communication system.
  • CDMA Code Division Multiple Access
  • a transmitter avoids burst errors by subjecting adjacent symbols or bits to irregular channel fading using a plurality of interleavers.
  • the transmitter multiplexes interleaved data blocks, maps the multiplexed data blocks to bursts, and performs symbol mapping according to a high-order modulation scheme such as 8-ary Phase Shift Keying (8PSK), 16-ary Quadrature Amplitude Modulation (16QAM), 32QAM, or 64QAM.
  • 8PSK Phase Shift Keying
  • 16QAM 16-ary Quadrature Amplitude Modulation
  • 32QAM 32QAM
  • 64QAM 64QAM
  • Symbol Mapping based on Priority was proposed for implementation in the transmitter to improve system performance by symbol mapping based on the priorities of systematic bits (S bits) and Parity bits (P bits) resulting from channel coding according to a coding scheme.
  • SMP systematic bits
  • P bits Parity bits
  • a first interleaver interleaves the S bits
  • a second interleaver interleaves the P bits.
  • symbols are mapped according to a coding rate and the reliability pattern of a high-order modulation scheme.
  • the number of high-reliability bits is determined by the reliability pattern of a used modulation scheme.
  • a reliability pattern can be [H H L L] for 16QAM and [H H M M L L] for 64QAM.
  • the S bits and the P bits can be divided into two sub-blocks.
  • a distributor efficiently divides a coded bit block (or a coded bit stream block) received from a channel encoder into two sub-blocks and provides them to interleavers, instead of simply transmitting the coded bit block separately as the S bits and the P bits to the interleavers in a system supporting a plurality of coding rates and data rates.
  • the two sub-blocks are independently interleaved, multiplexed, and burst-mapped.
  • the distributor divides a channel coded data bit stream including S bits and P bits into two sub-blocks.
  • the first and second interleavers interleave the sub-blocks independently.
  • the data of these interleaved data blocks should be distributed to a plurality of bursts. Also, it is preferred that the performance of the data of each burst is improved by symbol mapping such as SMP that can be applied to a high-order modulation.
  • US 2004/0071172 A1 describes an arrangement and method for channel mapping in a wireless communication system by applying interleaving functions in first and second interleaving means to a bit sequence to produce symbols for mapping to physical channels, the first and second interleaving means being arranged to map symbols from respectively systematic and parity bits in a predetermined scheme.
  • Systematic bits are preferably mapped to high reliability bit positions.
  • EP 1 324 527 A1 describes a data transmission/reception apparatus and method for improving performance of a mobile communication system by realizing a symbol mapping (SMP) technique for differentially mapping reliabilities according to a priority.
  • SMP symbol mapping
  • Certain embodiments aim to provide at least one of the advantages described below.
  • Certain embodiments of the present invention provide a data transmission apparatus and method for determining sub-block division based on a bit reliability pattern of a high-order modulation scheme and then multiplexing two sub-blocks interleaved by parallel interleavers to a plurality of bursts to render the sub-blocks less sensitive to channel fading. Further, corresponding a data reception apparatus and method is provided.
  • Certain embodiments of the present invention provide a data transmission apparatus and method for efficiently mapping bits to high-order modulation symbols on a symbol basis and on a block basis according to a bit reliability pattern of high-order modulation symbols in multiplexed bursts, and to provide corresponding a data reception apparatus and method.
  • the present invention is defined and limited only by the scope of the appended claims.
  • FIG. 1 is a block diagram illustrating a transmitter in a mobile communication system according to the present invention.
  • the transmitter includes a channel encoder 110, such as a convolution encoder or a turbo encoder. Coded bits from the channel encoder 110 are separated into S bits and P bits according to a used coding scheme.
  • a rate matcher 120 matches the number of the S bits and the P bits to a data rate by bit puncturing or bit repetition.
  • a distributor 130 divides the rate-matched S bits and P bits into two sub-blocks A and B, and provides the sub-blocks A and B to first and second interleavers 140 and 150, respectively.
  • the first and second interleavers 140 and 150 independently interleave the two types of data bits A and B.
  • first and second interleavers 140 and 150 prevent burst errors by subjecting adjacent symbols or bits to irregular channel fading.
  • a MUX and burst mapper 160 multiplexes and burst-maps two interleaved data blocks C and D received from the first and second interleavers 140 and 150.
  • An M-ary modulator 170 maps the coded bits received from the MUX and burst mapper 160 to modulation symbols according to a high-order modulation scheme such as 8PSK, 16QAM, 16QAM, 32QAM, or 64QAM.
  • FIG. 2 illustrates an operation for generating a plurality of data bursts by multiplexing and burst mapping according to the present invention.
  • the MUX and burst mapper 160 allocates the two data blocks C and D to N bursts by multiplexing and burst mapping and provides the N bursts to the M-ary modulator 170.
  • FIG. 3 illustrates an operation for multiplexing two data blocks to a plurality of data bursts in the MUX and burst mapper 160 according to the present invention. More specifically, in FIG. 3 , the operation for multiplexing the two data blocks C and D to the N bursts in the MUX and burst mapper 160, illustrated in FIG. 2 , is depicted in more detail.
  • One of the sub-blocks of Block C is paired with one of the sub-blocks of Block D and the pair is mapped to one burst.
  • sub-block C 1 and sub-block D 1 form a first burst (Burst 1) and sub-block C 2 and sub-block D 2 form a second burst (Burst 2).
  • TDMA Time Division Multiple Access
  • GSM Global System for Mobile communications
  • FIG. 4 illustrates bit reliability patterns of modulation symbols, to be applied to the M-ary modulator 170 according to the present invention. More specifically, referring to FIG. 4 , a method for applying high-order modulation symbol mapping to bursts each including a sub-block of Block C and a sub-block of Block D in the M-ary modulator 170 will be described below.
  • bit positions of a high-order M-ary modulation symbol are classified into a Higher reliable bit (H) position, a Medium reliable bit (M) position, and a Lower reliable bit (L) position according to their bit error probabilities.
  • H Higher reliable bit
  • M Medium reliable bit
  • L Lower reliable bit
  • other bit reliability patterns exist according to a gray symbol pattern used for the constellation of a modulation scheme and the layout of In-phase/Quadrature-phase (I/Q) bits for symbol transmission.
  • a higher-priority bit e.g. an S bit
  • a lower-priority bit e.g. a P bit
  • a high-order modulation symbol of, for example, 32/64/128QAM has an M position. That is, the bit error probability of the M position is between those of the H and L positions. Therefore, symbols can be mapped by designating the M position as the H position or the L position under circumstances.
  • the M-ary modulator 170 designates the M position as the H position, for symbol mapping.
  • the M-ary modulator 170 designates the M position as the L position, for symbol mapping.
  • FIGs. 5A , 5B , and 5C illustrate symbol-based bit mapping methods in the M-ary modulator 170 according to exemplary embodiments of the present invention. More specifically, FIG. 5A illustrates a symbol-based bit mapping method for 8PSK, FIG. 5B illustrates a symbol-based bit mapping method for 16QAM, and FIG. 5C illustrates a symbol-based bit mapping method for 32QAM.
  • bits are mapped to high-order modulation symbols on a symbol basis in an i th burst 530a, 530b, and 530c (Burst i) being a combination of two interleaved sub-blocks C i (510a, 510b, and 510c) and D i (520a, 520b, and 520c).
  • sub-block C i includes J bits and sub-block D i includes K bits.
  • bit reliability pattern 410 of 8PSK is [H H L].
  • the M-ary modulator 170 sequentially maps two bits from sub-block C i and one bit from sub-block D i to one 8PSK symbol.
  • the M-ary modulator 170 can perform bit mapping on a symbol basis for 16QAM in the same manner. That is, as illustrated in FIG. 4 , the bit reliability pattern 420 of 16QAM is [H H L L]. Hence, the M-ary modulator 170 sequentially maps two bits from sub-block C i and two bits from sub-block D i to one 16QAM symbol in Burst i.
  • the bit reliability pattern 430 of 32QAM has an M position with a medium reliability.
  • the M-ary modulator 170 performs bit mapping on a symbol basis by designating the M position as an H position. This symbol-based bit mapping can also be implemented by designating the M position as an L position in the M-ary modulator 170. It is clear that the M-ary modulator 170 can easily perform symbol-based bit mapping for the bit reliability pattern 440 of 64QAM and the bit reliability pattern 450 of 128QAM in the same manner.
  • FIGs. 6A , 6B , and 6C illustrate block-based bit mapping methods in the M-ary modulator 170 according to exemplary embodiments of the present invention. More specifically, in the modified examples illustrated in FIGs. 6A , 6B , and 6C , bits are mapped to high-order modulation symbols on a block basis in an i th burst 630a, 630b, and 630c (Burst i) being a combination of two interleaved sub-blocks C i (610a, 610b, and 610c) and D i (620a, 620b, and 620c).
  • the M-ary modulator 170 constructs a burst in the form of a matrix and performs symbol mapping by filling bits by rows, starting from the first row on a block basis according to the bit reliability pattern of a modulation scheme.
  • Each column of the matrix represents one symbol. Accordingly, symbols are read down by columns in the bursts illustrated in FIGs. 6A , 6B , and 6C .
  • FIG. 6A illustrates a block-based bit mapping for 8PSK. It is assumed herein that sub-block C i includes J bits and sub-block D i includes K bits. As illustrated in FIG. 4 , the bit reliability pattern 410 of 8PSK is [H H L]. Therefore, the M-ary modulator 170 divides the bits of sub-block C i into two equal blocks and sequentially maps the two blocks to the first and second rows of a matrix. Also, the M-ary modulator 170 maps sub-block D i to the third row of the matrix without block division. In this manner, bits are mapped to 8PSK symbols.
  • FIG. 6B illustrates a block-based bit mapping for 16QAM
  • FIG. 6C illustrates a block-based bit mapping for 32QAM.
  • the M-ary modulator 170 performs bit mapping on a block basis according to a bit reliability pattern for 16QAM and 32QAM in the same manner as for 8PSK.
  • the bit reliability pattern of a modulation scheme may vary depending on a gray symbol pattern used for the constellation of the modulation scheme and the layout of I/Q channel bits for symbol transmission. It is well known that the reliability pattern of 16QAM, [H H L L] described with reference to FIGs. 5B and 6B can be changed to [H L H L] according to the bit layout of the constellation.
  • 16QAM bit mapping is performed as illustrated in FIGs. 7A and 7B .
  • FIG. 7A illustrates a symbol-based bit mapping method for 16QAM in the M-ary modulator 170 according to an exemplary embodiment of the present invention
  • FIG. 7B illustrates a block-based bit mapping method for 16QAM in the M-ary modulator 170 according to another exemplary embodiment of the present invention.
  • the M-ary modulator 170 alternately takes one bit from sub-block C i (710a)and one bit from sub-block D i (720a)in a sequential manner and maps them to Burst i(730a). Accordingly, bits are mapped to 16QAM symbols on a symbol basis.
  • the M-ary modulator 170 maps sub-block C i (710b)to the first and third rows of a matrix without block division and sub-block D i (720b) to the second and fourth rows of the matrix without block division and maps them to Burst i(730b). Accordingly, bits are mapped to 16QAM symbols on a block basis.
  • bit mapping of 8PSK or 32QAM can be changed in the above-described manner according to its bit reliability pattern.
  • burst mapping for 8PSK, 16QAM, and 32QAM in a Global System for Mobile communications/Enhanced Data Rates for Global Evolution (GSM/EDGE) will be described below in more detail.
  • sub-block C includes 832 bits and sub-block D includes 416 bits, expressed as follows.
  • the data bits of the two sub-blocks C and D are multiplexed to four bursts in GSM/EDGE.
  • the symbol-based bit mapping and block-based bit mapping for 8PSK according to the present invention can be applied.
  • DI bit-mapped data
  • DI 2 DI 3
  • DI 4 c 0 c 1 d 0
  • c 2 c 3 d 1
  • c 4 c 5 d 2
  • ... c 830
  • c 831 d 415 di k
  • k 0, 1, ... , 1247
  • a matrix is formed with the data of blocks C and D on a block basis according to the reliability pattern [H H L]. That is, block C is divided and mapped to the first and second rows of the matrix because the first and second rows correspond to the H positions. Then block D is mapped to the third row of the matrix because the third row corresponds to the L position.
  • 16QAM the number of user data bits to be transmitted is 1664.
  • the 1664 user data bits are distributed to four bursts and transmitted with header part data.
  • the bit reliability pattern of 16QAM can be [H H L L] or [H L H L]. If [H H L L] is used, sub-block C includes 832 bits and sub-block D includes 832 bits, and is expressed as follows.
  • the data bits of the two sub-blocks C and D are multiplexed to four bursts in GSM/EDGE.
  • the symbol-based bit mapping and block-based bit mapping for 16QAM according to the present invention can be applied.
  • DI bit-mapped data
  • DI 2 DI 3
  • DI 4 c 0 c 1 d 0 d 1
  • c 2 c 3 d 2 d 3 c 4 c 5 d 4 d 5
  • ... , 830 c 831 d 830 d 831 di k
  • k 0, 1, ... , 1663
  • a matrix is formed with the data of blocks C and D on a block basis according to the reliability pattern [H H L L]. That is, block C is divided and mapped to the first and second rows of the matrix because the first and second rows correspond to the H positions. Then block D is divided and mapped to the third and fourth rows of the matrix since the third and fourth rows correspond to the L positions.
  • DI bit-mapped data DI are sequentially read down from the matrix by columns, starting from c(0) to d(831).
  • DI can be expressed as shown in Equation (4).
  • the mapping of the data DI may involve header part data (hi, u, q). That is,
  • the number of user data bits to be transmitted is 2120.
  • the 2120 user data bits are distributed to four bursts and transmitted with header part data.
  • the bit reliability pattern of 32QAM can be [H L M H L].
  • sub-block C includes 1272 bits and sub-block D includes 848 bits. That is, M is dealt with as H and thus the data ratio between C:D is 3:2.
  • the data bits of the two sub-blocks C and D are multiplexed to four bursts in GSM/EDGE.
  • the symbol-based bit mapping and block-based bit mapping for 32QAM according to the present invention can be applied.
  • DI bit-mapped data
  • DI 2 DI 3
  • a matrix is formed with the data of blocks C and D on a block basis according to the reliability pattern [H L M H L]. That is, block C is divided into three parts and mapped to the first, third and fourth rows of the matrix because the first, third, and fourth rows correspond to H positions (or the M position). Thereafter, block D is divided and mapped to the second and fifth rows of the matrix because the second and fifth rows correspond to the L positions.
  • DI bit-mapped data DI are sequentially read down from the matrix by columns, starting from c(0) to d(1271).
  • DI can be expressed as shown in Equation (6).
  • the user data bits DI of Equation (5) and Equation (6) are allocated to the bursts as follows.
  • First burst : DI 1 di 0 di 0 di 1 ... di 529
  • Second burst : DI 2 di 530 di 531 ... di 1059
  • Third burst : DI 3 di 1060 di 1061 ... di 1589
  • Fourth burst : DI 4 di 1590 di 1591 ... di 2119
  • the mapping of the data DI may involve header part data (hi, u, q). That is,
  • symbol-based bit mapping and block-based bit mapping can be easily performed for 64QAM and 128QAM in the above-described manner.
  • FIG. 8 is a block diagram of a receiver in the mobile communication system according to the present invention.
  • the receiver is the counterpart of the transmitter with the MUX and burst mapper 160 and the M-ary modulator 170, by way of example.
  • an equalizer (or demodulator) 810 removes channel interference and noise from received data.
  • a Demultiplexer (DEMUX) and demapper 820 divides N data bursts free of interference and noise received from the equalizer 810 into two data blocks C and D.
  • First and second deinterleavers 830 and 840 deinterleave the data blocks C and D, thereby recovering the data of the data blocks C and D to their original bit positions.
  • a de-distributor 850 separates the deinterleaved data A and B into original S bits and P bits and stores them in a buffer 860.
  • a channel decoder 870 recovers the buffered data to a data block transmitted by the transmitter.
  • FIG. 9 is a flowchart illustrating a control operation of the transmitter in the mobile communication system according to the present invention.
  • the channel encoder 110 encodes transmission data in step 901.
  • the rate matcher 120 rate-matches the coded data by puncturing or repetition and provides the rate-matched data separately as S bits and P bits to the distributor 130 in step 903.
  • the distributor 130 divides (or distributes) the S and P bits at a predetermined ratio and outputs the divided S and P bits to the channel interleavers 140 and 150, respectively.
  • the channel interleavers 140 and 150 channel-interleave the S and P bits, respectively, in step 907.
  • the MUX and burst mapper 160 multiplexes two interleaved data blocks C and D received from the channel interleavers 140 and 150 to N bursts according to an exemplary embodiment of the present invention.
  • the M-ary modulator 170 performs symbol mapping in the multiplexed bursts by symbol-based bit mapping or block-based bit mapping according to a high-order modulation scheme and transmits each burst on a radio channel in step 911.
  • FIG. 10 is a flowchart illustrating a control operation of the receiver in the mobile communication system according to the present invention.
  • the receiver operates in a reverse order of the operation of the transmitter illustrated in FIG. 9 in order to recover the transmitted data.
  • the equalizer 810 equalizes (or demodulates) data from a received signal in step 1001. During the data demodulation, the equalizer 810 removes channel interference and noise from the received data. In step 1003, the DEMUX and burst demapper 820 divides N data bursts free of channel interference and noise into two data blocks. The first and second deinterleavers 830 and 840 return the data of the two data blocks to their original bit positions in step 1005. The de-distributor 850 separates the deinterleaved data into original S and P bits in step 1007 and the buffer 860 buffers the S and P bits in step 1009. In step 1011, the channel decoder 870 recovers a data block transmitted by the transmitter from the buffered data.
  • the present invention advantageously provides a data transmission and reception apparatus and method in a mobile communication system, which are less sensitive to channel fading because sub-block division is determined based on the bit reliability pattern of a high-order modulation scheme. Thereafter, two sub-blocks interleaved by parallel interleavers are multiplexed to a plurality of bursts.
  • the present invention improves system performance by providing a data transmission apparatus that maps bits to high-order modulation symbols on a symbol basis or on a block basis according to the bit reliability pattern of the high-order modulation symbols in multiplexed bursts, and by providing a data counterpart reception apparatus.
  • embodiments of the present invention can be realized in the form of hardware, software or a combination of hardware and software. Any such software may be stored in the form of volatile or non-volatile storage such as, for example, a storage device like a ROM, whether erasable or rewritable or not, or in the form of memory such as, for example, RAM, memory chips, device or integrated circuits or on an optically or magnetically readable medium such as, for example, a CD, DVD, magnetic disk or magnetic tape or the like. It will be appreciated that the storage devices and storage media are embodiments of machine-readable storage that are suitable for storing a program or programs comprising instructions that, when executed, implement embodiments of the present invention.
  • embodiments provide a program comprising code for implementing method as claimed in any one of the claims of this specification and a machine-readable storage storing such a program. Still further, such programs may be conveyed electronically via any medium such as a communication signal carried over a wired or wireless connection and embodiments suitably encompass the same.

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Claims (10)

  1. Appareil de transmission de symboles dans un système de communication mobile, comprenant:
    un multiplexeur et mappeur en rafales (160) pour diviser chacun du premier bloc de données de groupe et du second bloc de données de groupe en une pluralité de sous-blocs, les symboles comprenant le premier bloc de données de groupe (310) et le second bloc de données de groupe (320), le second groupe bloc de données (320) ayant un niveau de priorité différent du premier bloc de données de groupe (310) et mappant une combinaison de l'un des premiers sous-blocs de données de groupe et l'un des seconds sous-blocs de données de groupe à chacun d'une pluralité de rafales; et
    un modulateur (170) pour mapper un bit du premier sous-bloc de données de groupe (510a; 510b; 510c; 610a; 610b; 610c; 710a; 710b) et un bit du second sous-bloc de données de groupe (520a; 520b; 520c; 620a; 620b; 620c; 720a; 720b) avec un symbole conforme à un modèle de fiabilité de bits (410, 420, 430, 440, 450) de symboles de modulation dans chacune de la pluralité de rafales,
    ledit appareil étant caractérisé en ce que le modulateur (170) est en outre configuré pour effectuer le mappage de symboles en regroupant chacun de la pluralité de rafales dans une matrice (630a; 630b; 630c; 730b) et le mappage des bits du premier sous-bloc de données de groupe (610a; 610b; 610c; 710b) et des bits du second sous-bloc de données de groupe (620a; 620b; 620c; 720b) bloc par bloc dans des rangées de la matrice (630a; 630b; 630c; 730b) selon le modèle de fiabilité de bits (410, 420, 430, 440, 450).
  2. Appareil selon la revendication 1, dans lequel le modulateur (170) est prévu pour mapper un bit de priorité plus élevée vers une position de bit de fiabilité plus élevée, si le modèle de fiabilité de bit (410, 420, 430, 440, 450) a une position de bit plus élevée,
    mapper un bit de priorité plus faible vers une position de bit de fiabilité plus faible, si le modèle de fiabilité de bit (410, 420, 430, 440, 450) a une position de bit plus faible,
    et si le modèle de fiabilité de bit (410, 420, 430, 440, 450) a une position de bit de fiabilité moyenne, mapper le bit de priorité plus élevée vers la position de bit de fiabilité moyenne si le nombre de bits systématiques dépasse celui des bits de parité, et le bit de priorité plus faible vers la position de bit de fiabilité moyenne si le nombre de bits de parité dépasse celui des bits systématiques,
    dans lequel la position de bit de fiabilité plus élevée, la position de bit de fiabilité plus faible et la position de bit de fiabilité moyenne sont déterminées selon des probabilités d'erreur de bit.
  3. Appareil selon l'une quelconque des revendications précédentes, dans lequel le premier bloc de données de groupe est un bloc de données systématiques, et le second bloc de données de groupe est un bloc de données de parité.
  4. Procédé de transmission de symboles dans un système de communication mobile, consistant à:
    diviser (905) chacun du premier bloc de données de groupe (310) et du second (320) bloc de données de groupe en une pluralité de sous-blocs, les symboles comprenant le premier bloc de données de groupe (310) et le second bloc de données de groupe (320), le second groupe un bloc de données (320) ayant un niveau de priorité différent du premier bloc de données de groupe (310);
    mapper (909) une combinaison de l'un des premiers sous-blocs de données de groupe et l'un des seconds sous-blocs de données de groupe avec chacune de la pluralité de rafales ; ledit procédé étant caractérisé en ce qu'il consiste à:
    moduler (911) les données en mappant un bit du premier sous-bloc de données de groupe (510a; 510b; 510c; 610a; 610b; 610c; 710a; 710b) et un bit du second sous-bloc de données de groupe (520a; 520b; 520c; 620a; 620b; 620c; 720a; 720b) avec un symbole conforme à un modèle de fiabilité de bits (410, 420, 430, 440, 450) de symboles de modulation dans chacune de la pluralité de rafales,
    dans lequel la modulation des données consiste à:
    regrouper chacune de la pluralité de rafales dans une matrice (630a; 630b; 630c; 730b); et
    mapper des bits du premier sous-bloc de données de groupe (610a; 610b; 610c; 710b) et des bits du second sous-bloc de données de groupe (620a; 620b; 620c; 720b) dans des rangées de la matrice, bloc par bloc, selon le modèle de fiabilité des bits (410, 420, 430, 440, 450).
  5. Procédé selon la revendication 4, dans lequel la modulation (911) des données consiste à:
    mapper un bit de priorité plus élevée vers une position de bit de fiabilité supérieure, si le modèle de fiabilité de bit (410, 420, 430,440, 450) a la position de bit plus élevée;
    mapper un bit de priorité plus faible vers une position de bit de fiabilité plus faible, si le modèle de fiabilité de bit (410, 420, 430, 440, 450) a la position de bit plus faible; et
    mapper le bit de priorité plus élevée vers la position de bit de fiabilité moyenne si le nombre de bits systématiques dépasse celui des bits de parité, et mapper le bit de priorité plus faible vers la position de bit de fiabilité moyenne si le nombre de bits de parité dépasse celui des bits systématiques,
    dans lequel la position de bit de fiabilité plus élevée, la position de bit de fiabilité plus faible et la position de bit de fiabilité moyenne sont déterminées selon des probabilités d'erreur de bit.
  6. Procédé selon l'une quelconque des revendications précédentes, dans lequel le premier bloc de données de groupe (310) contient un bloc de données systématiques, et le second bloc de données de groupe (320) contient un bloc de données de parité.
  7. Appareil de réception permettant de recevoir des symboles dans un système de communication mobile, comprenant:
    un égaliseur (810) permettant de recevoir des symboles et de démoduler les symboles en une pluralité de rafales, dans lequel les symboles reçus sont produits dans un appareil émetteur et transmis audit appareil récepteur en divisant chacun d'un premier bloc de données de groupe (310) et d'un second bloc de données de groupe (320) en une pluralité de sous-blocs, le second bloc de données de groupe (320) ayant un niveau de priorité différent du premier bloc de données de groupe (310), mapper une combinaison de l'un des premiers sous-blocs de données de groupe et l'un des seconds sous-blocs de données de groupe avec chacune de la pluralité de rafales, et consistant à mapper un bit du premier sous-bloc de données de groupe (510a; 510b; 510c; 610a; 610b; 610c; 710a; 710b) et un bit du second sous-bloc de données de groupe (520a; 520b; 520c; 620a; 620b; 620c; 720a; 720b) avec un symbole conforme à un modèle de fiabilité de bits (410, 420, 430, 440, 450) de symboles de modulation dans chacune de la pluralité de rafales,
    et dans lequel le mappage des symboles consiste en outre à regrouper chacune de la pluralité de rafales dans une matrice (630a; 630b; 630c; 730b) et mapper des bits du premier sous-bloc de données de groupe (610a; 610b; 610c; 710b) et des bits du second sous-bloc de données de groupe (620a; 620b; 620c; 720b) dans des rangées de la matrice, bloc par bloc, selon le modèle de fiabilité des bits (410, 420, 430, 440, 450), ledit appareil de réception comprenant en outre:
    un démultiplexeur et un démappeur en rafales (820) pour diviser la pluralité de rafales en deux blocs de données;
    un premier désentrelaceur (830) et un second désentrelaceur (840) pour désentrelacer les deux blocs de données, respectivement;
    un dédistributeur (850) permettant de séparer les données désentrelacées en premières données de groupe et secondes données de groupe;
    un tampon (860) pour mettre en mémoire tampon les premières données de groupe et les secondes données de groupe; et
    un décodeur de canal (870) pour récupérer les premières données de groupe en mémoire- tampon et les secondes données de groupe dans le premier bloc de données de groupe et le second bloc de données de groupe.
  8. Procédé de réception permettant de recevoir des symboles dans un système de communication mobile, consistant à:
    recevoir des symboles;
    démoduler (1001) les symboles en une pluralité de rafales, dans lequel lesdits symboles sont produits au niveau d'un émetteur, et ce en:
    divisant chacun d'un premier bloc de données de groupe (310) et d'un second bloc de données de groupe (320) en une pluralité de sous-blocs, le second bloc de données de groupe (320) ayant un niveau de priorité différent du premier bloc de données de groupe (310);
    mapper (1003) une combinaison de l'un des premiers sous-blocs de données de groupe et l'un des seconds sous-blocs de données de groupe avec chacune de la pluralité de rafales; et
    mapper (1003) un bit du premier sous-bloc de données de groupe (510a; 510b; 510c; 610a; 610b; 610c; 710a; 710b) et un bit du second sous-bloc de données de groupe (520a; 520b; 520c; 620a; 620b; 620c; 720a; 720b) avec un symbole conforme à un modèle de fiabilité de bits (410, 420, 430, 440, 450) de symboles de modulation dans chacune de la pluralité de rafales et dans lequel le mappage des symboles consiste à regrouper chacune de la pluralité de rafales dans une matrice (630a; 630b; 630c; 730b) et mapper des bits du premier sous-bloc de données de groupe (610a; 610b; 610c; 710b) et des bits du second sous-bloc de données de groupe (620a; 620b; 620c; 720b) dans des rangées de la matrice, bloc par bloc, selon le modèle de fiabilité des bits (410, 420, 430, 440, 450), ledit procédé de réception consistant en outre à:
    diviser la pluralité de rafales en deux blocs de données;
    désentrelacer (1005) les deux blocs de données, respectivement;
    séparer (1007) les données désentrelacées en premières données de groupe et secondes données de groupe;
    mettre en mémoire tampon (1009) les premières données de groupe et les secondes données de groupe; et
    récupérer (1011) les premières données de groupe en mémoire-tampon et les secondes données de groupe dans le premier (310) bloc de données de groupe et le second (320) bloc de données de groupe.
  9. Programme informatique comprenant des instructions, permettant lorsque le programme est exécuté par un ordinateur, à l'ordinateur d'exécuter les étapes du procédé selon l'une quelconque des revendications 4-6 et 8.
  10. Support de données lisibles machine sur lequel est stocké le programme informatique selon la revendication 9.
EP08010913.5A 2007-06-15 2008-06-16 Transmission et réception de données numériques contenant des symboles à priorités différentes Expired - Fee Related EP2003836B1 (fr)

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