EP2002481A1 - Dispositifs spintroniques contenant des dopants spintroniques et procedes associes - Google Patents

Dispositifs spintroniques contenant des dopants spintroniques et procedes associes

Info

Publication number
EP2002481A1
EP2002481A1 EP07753441A EP07753441A EP2002481A1 EP 2002481 A1 EP2002481 A1 EP 2002481A1 EP 07753441 A EP07753441 A EP 07753441A EP 07753441 A EP07753441 A EP 07753441A EP 2002481 A1 EP2002481 A1 EP 2002481A1
Authority
EP
European Patent Office
Prior art keywords
spintronic
semiconductor
dopant
group
monolayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07753441A
Other languages
German (de)
English (en)
Inventor
Xiangyang Huang
Samed Halilov
Jean Augustin Chan Sow Fook Yiptong
Ilija Dukovski
Marek Hytha
Robert J. Mears
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atomera Inc
Original Assignee
Mears Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/687,430 external-priority patent/US7625767B2/en
Priority claimed from US11/687,422 external-priority patent/US20080012004A1/en
Application filed by Mears Technologies Inc filed Critical Mears Technologies Inc
Publication of EP2002481A1 publication Critical patent/EP2002481A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/158—Structures without potential periodicity in a direction perpendicular to a major surface of the substrate, i.e. vertical direction, e.g. lateral superlattices, lateral surface superlattices [LSS]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y25/00—Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F1/00—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties
    • H01F1/01—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials
    • H01F1/40—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials of magnetic semiconductor materials, e.g. CdCr2S4
    • H01F1/401—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials of magnetic semiconductor materials, e.g. CdCr2S4 diluted
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F1/00—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties
    • H01F1/01—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials
    • H01F1/40—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials of magnetic semiconductor materials, e.g. CdCr2S4
    • H01F1/401—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials of magnetic semiconductor materials, e.g. CdCr2S4 diluted
    • H01F1/405—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials of magnetic semiconductor materials, e.g. CdCr2S4 diluted of IV type, e.g. Ge1-xMnx
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F10/00—Thin magnetic films, e.g. of one-domain structure
    • H01F10/32—Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
    • H01F10/3213—Exchange coupling of magnetic semiconductor multilayers, e.g. MnSe/ZnSe superlattices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F10/00—Thin magnetic films, e.g. of one-domain structure
    • H01F10/32—Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
    • H01F10/324—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer
    • H01F10/3268—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer the exchange coupling being asymmetric, e.g. by use of additional pinning, by using antiferromagnetic or ferromagnetic coupling interface, i.e. so-called spin-valve [SV] structure, e.g. NiFe/Cu/NiFe/FeMn
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/14—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying magnetic films to substrates
    • H01F41/30—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying magnetic films to substrates for applying nanostructures, e.g. by molecular beam epitaxy [MBE]
    • H01F41/302—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying magnetic films to substrates for applying nanostructures, e.g. by molecular beam epitaxy [MBE] for applying spin-exchange-coupled multilayers, e.g. nanostructured superlattices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/151—Compositional structures
    • H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66984—Devices using spin polarized carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F10/00—Thin magnetic films, e.g. of one-domain structure
    • H01F10/08—Thin magnetic films, e.g. of one-domain structure characterised by magnetic layers
    • H01F10/10—Thin magnetic films, e.g. of one-domain structure characterised by magnetic layers characterised by the composition
    • H01F10/18—Thin magnetic films, e.g. of one-domain structure characterised by magnetic layers characterised by the composition being compounds
    • H01F10/193—Magnetic semiconductor compounds

Definitions

  • the present invention relates to the field of electronics, and, more particularly, to the field of spin- based electronics and associated methods.
  • FIGS. IA and IB An exemplary spintronic device is the spin valve as illustrated in the FIGS. IA and IB.
  • the spin valve 11 provides a low resistance when the spins are aligned (FIG. IA) , and provides a high resistance with the spins not aligned (FIG. IB) .
  • the spin valve 11 may be used as a nonvolatile memory element, for example.
  • Other exemplary spintronic devices including the spin-FET 12 schematically illustrated in FIG. 2, and the quantum bit device 13 illustrated in FIG. 3.
  • DMS Diluted Magnetic Semiconductor
  • zinc oxide which includes a transition element or a rare earth lanthanide, or both, in an amount sufficient to change the material from nonmagnetic state to a room temperature ferromagnetic state.
  • the material may be in a bulk form or a thin film form.
  • a DMS material is a semiconductor in which transition metal ions or rare earth lanthanides substitute cations of host semiconductor materials. More particularly, a DMS material 15 is schematically illustrated in FIG. 4B, while to the left in FIG. 4A is a magnetic material 14, and to the right in FIG. 4C is a non-magnetic material 16.
  • a spintronic switching device comprising a half-metal region between first and second conductive regions.
  • the half-metal region comprises a material that, at the intrinsic Fermi level, has substantially zero available electronic states in a minority spin channel. Changing the voltage of the half- metal region with respect to the first conducting region moves its Fermi level with respect to the electron energy bands of the first conducting region, which changes the number of available electronic states in the majority spin channel. In doing so, this changes the majority spin polarized current passing through the switching device.
  • the half-metal region may comprise CrAs and the conducting regions may comprise a p-doped or n-doped semiconductor.
  • the p-doped semiconductor may comprise Mn doped GaAs .
  • a spintronic device application as a memory and a logic device using a spin valve effect obtained by injecting a carrier spin-polarized from a ferromagnetic into a semiconductor at room temperature, and a spin-polarized field effect transistor.
  • the ferromagnet is disclosed as one of a Fe, Co, Ni, FeCo, NiFe, GaMnAs, InMnAs, GeMn, and GaMnN, and can be a half metal having a spin polarization of 100% such as Cr ⁇ 2 -
  • the semiconductor may be one selected from Si, GaAs, InAs, and Ge.
  • the spin channel region is disclosed as Si on insulator (SOI)
  • a double-barrier heterojunction comprising a nonmagnetic semiconductor quantum well between two insulating barriers and two ferromagnetic semiconductive electrodes may behave as half-metallic junctions if the parameters of the quantum well and barrier are properly tuned.
  • FIG. 5 A schematic diagram of a prior art DFH structure 18 is shown in FIG. 5 with a transition metal (Tm) in the form of Mn within a Silicon superlattice. Although this may have a large spin polarization at the Fermi level and a large magnetoresistance effect and Curie temperature higher than in the bulk, it may suffer from a low thermal stability.
  • Tm transition metal
  • spintronic dopant such as Mn.
  • the spintronic dopant tends to precipitate out of the crystal lattice, especially as the concentration is increased, and/or the device is subjected to thermal processing steps.
  • a spintronic device that is readily manufactured and which exhibits good spintronic characteristics, such as at room temperature or higher, for example.
  • a spintronic device comprising at least one superlattice and at least one electrical contact coupled thereto, with the at least one superlattice comprising a plurality of groups of layers.
  • Each group of layers may comprise a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice, at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions, and a spintronic dopant.
  • the spintronic dopant may be constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer. Accordingly, a fairly high spintronic dopant concentration may be achieved and maintained while reducing a likelihood of precipitation of the spintronic dopant.
  • the spintronic dopant may comprise at least one spintronic dopant monolayer- adjacent the at least one non- semiconductor monolayer.
  • the spintronic dopant may comprises a transition metal, such as at least one of Manganese, Iron, and Chromium.
  • the spintronic dopant may comprise a rare earth, such as a rare earth lanthanide, for example .
  • the non-semiconductor may comprise at least one of Oxygen, Nitrogen, Fluorine, Carbon-Oxygen, and Sulphur, for example.
  • the semiconductor may comprise Silicon, or more generally, may comprise a semiconductor selected from the group comprising Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors. The specific materials and structural configurations may be preferably selected so that the superlattice exhibits a Curie temperature of at least as high as room temperature.
  • An embodiment of the spintronic device may be a spintronic field effect transistor.
  • the spintronic FET may include a substrate carrying a pair of superlattices in spaced apart relation to define a source and a drain, with a channel between the source and drain, and a gate adjacent the channel.
  • a spin valve Another embodiment of the spintronic device is a spin valve.
  • the spin valve may also include a substrate carrying a pair of superlattices in spaced apart relation with a spacer between the pair of superlattices .
  • the repeating structure of a superlattice may not be needed.
  • the spintronic device may comprise a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice, at least one non- semiconductor monolayer constrained within the crystal lattice, and a spintronic dopant constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer.
  • the device may also include an electrical contact coupled to the base semiconductor portion.
  • a method aspect is for making a spintronic device comprising forming at least one superlattice and forming at least one electrical contact coupled thereto, with the at least one superlattice comprising a plurality of groups of layers.
  • Each group of layers may comprise a plurality of stacked base -semiconductor monolayers defining a base semiconductor portion having a crystal lattice, at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions, and a spintronic dopant.
  • the spintronic dopant may be constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer.
  • FIG. IA is a schematic diagram of a spin valve as is in the prior art illustrated in a low resistance state.
  • FIG. IB is a schematic diagram of the prior art spin valve as shown in FIG. IA illustrated in a high resistance state.
  • FIG. 2 is a schematic perspective view of a spin FET as in the prior art.
  • FIG. 3 is a schematic diagram of a quantum bit device as in the prior art.
  • FIG. 4A is a schematic diagram of a magnetic material as in the prior art.
  • FIG. 4B is a schematic diagram of a dilute magnetic material as in the prior art.
  • FIG. 4C is a schematic diagram of a non-magnetic material as in the prior art.
  • FIG. 5 is a schematic atomic diagram for a Digital Ferromagnetic Heterostructure (DFH) as in the prior art.
  • DSH Digital Ferromagnetic Heterostructure
  • FIGS. 6A and 6B are, respectively, a schematic diagram and energy level diagram for a DFH in accordance with the invention.
  • FIG. 7 is a schematic atomic diagram for a DFH structure in accordance with the invention.
  • FIG. 8 is a schematic atomic model of a portion of a superlattice for a spintronic device in accordance with the present invention.
  • FIG. 9 is a combined energy diagram for the superlattice as shown in FIG. 8.
  • FIGS. lOA-lOC are schematic atomic diagrams of various relative atomic positions of Si, O, and Mn in a spintronic device in accordance with the invention.
  • FIG. 11 is a schematic cross-sectional diagram of a spintronic FET in accordance with the invention.
  • FIG. 12 is a schematic cross-sectional diagram of a spin valve in accordance with the invention.
  • FIGS. 6A and 6B a first example of the present invention is now described.
  • Oxygen is included in the Si superlattice also including a transition metal, such as Mn.
  • Mn transition metal
  • the Mn will have lower energy as it approaches the Oxygen layer.
  • the structure is most energetically favorable, and the Mn atoms can be well positioned and confined in the Silicon.
  • the relative positioning of the Mn atoms with respect to the Oxygen atoms may be used to tune the Curie temperature (Tc) , for example.
  • Tc Curie temperature
  • the Tc may be much higher than room temperature for a 2D confined system, for example.
  • the DFH structure 20 with Oxygen is advantageously more thermally stable than prior art structures.
  • Mn for example, substitutionally introduces only a small stress into the Silicon monocrystalline structure.
  • Mn is an example of a transition metal suitable for spintronic devices.
  • Those of skill in the art will appreciate that other materials may be used as well, such as, for example, Fe, Cr, etc.
  • Rare earth elements may also be used, such as rare earth lanthanides.
  • the base semiconductor illustratively in the form of Si, may be a semiconductor selected from the group comprising Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.
  • Group IV semiconductors also includes Group IV-IV semiconductors.
  • FIG. 7 The charge and spin densities of various layers of a DFH structure 22 and incorporating Oxygen along with Mn in an Si monocrystalline superlattice is schematically illustrated in FIG. 7.
  • Layer 1 is shown to be in a conductive state, in contrast to the other layers, Layers 6 and 16.
  • a schematic atomic model 25 is shown in FIG. 8, with the transition metal (e.g. Mn) incorporated in the Silicon lattice along with Oxygen.
  • the transition metal e.g. Mn
  • the spin-up energy states 27 (top) and the spin-down energy states 28 (bottom) are shown.
  • the spin-up energy diagram 27 indicates that current will flow because of the low energy states at the Fermi level as will be appreciated by those skilled in the art, and in contrast to the high energy states at the Fermi level for the spin-down diagram 28.
  • FIGS. lOA-lOC the relative energetics of various Si-Mn-O structures are schematically illustrated. More particularly, the structure 31 shown in FIG. 1OA with an Oxygen atom between adjacent Mn atoms offers the lowest stability, the structure 32 shown in FIG. 1OB with an Oxygen atom remote from a pair of Mn atoms offers an intermediate stability, and the structure 33 shown in FIG. 1OC with an Oxygen atom tied to one of a pair of Mn atoms offers the highest relative stability.
  • the spintronic device may comprise at least one superlattice and at least one electrical contact coupled thereto, with the at least one superlattice comprising a plurality of groups of layers.
  • Each group of layers may comprise a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice, at least one non- semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions, and a spintronic dopant.
  • the base semiconductor portion may comprise 5 o 30 monolayers, for example.
  • the spintronic dopant may be constrained within the crystal lattice of the base semiconductor portion by the at least one non- semiconductor monolayer as described above.
  • a relatively high spintronic dopant concentration may be achieved and maintained while reducing a likelihood of precipitation of the spintronic dopant.
  • concentration of the spintronic dopant may be in the range of from about 0.1 to 10 percent.
  • the spintronic dopant may comprise at least one spintronic dopant monolayer adjacent the at least one non- semiconductor monolayer. This may be so, for example, where the energy levels favor attraction and retention of the spintronic dopant to the non-semiconductor.
  • Further details regarding superlattice structures including Silicon and Oxygen to achieve energy band modifications, such as to increase charge carrier mobility, are described in commonly assigned U.S. Patent Nos. 6,891,188 and 7,153,763, for example, the entire contents of which are incorporated herein by reference.
  • the non-semiconductor monolayer (s) may serve to collect or at least contain the spintronic dopant to keep the dopant from precipitating out, especially during any subsequent thermal processing steps as will be appreciated by those skilled in the art.
  • the spintronic dopant may be added by atomic layer deposition.
  • the spintronic dopant may be added by implantation and optionally followed by an anneal, for example, while the non-semiconductor monolayer (s) serves to at least contain the dopant.
  • the non-semiconductor monolayer may be initially formed in a non-continuous fashion, that is, without all available positions for Oxygen being filled in the Silicon lattice, for example.
  • ALD Atomic Layer Deposition
  • the superlattices in some cases may be formed before shallow trench isolation (STI) formation, and are thus subjected to thermal processing during STI formation.
  • the term monolayer is intended to cover this theorized clustering phenomenon, and is not limited to a precise mathematical or atomic stick model layer as will be appreciated by those skilled in the art. It is also theorized by Applicants without their wishing to be bound thereto, that a clustering phenomenon may be considered to occur with the spintronic dopant, especially for the those combinations of materials, such as Si-O-Mn, where the Mn will be attracted to the 0. [0044] Extending the principles described herein further, in some embodiments the repeating structure of a superlattice may not be needed.
  • the spintronic device may comprise a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice, at least one non- semiconductor monolayer constrained within the crystal lattice, and a spintronic dopant constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer.
  • the device may also include an electrical contact coupled to the base semiconductor portion.
  • the spintronic FET 40 illustratively includes a semiconductor substrate 41 carrying a pair of superlattices in spaced apart relation to define a source ' 43 and a drain 44, with a channel 45 between the source and drain, and a gate 50 adjacent the channel.
  • the gate 50 includes a dielectric layer 52 and a gate electrode or contact 51 thereon.
  • the source 43 and drain 44 are illustrated with a plurality of horizontally extending lines schematically indicating the repeating groups of the superlattice and with dots indicative of the spintronic dopant.
  • a source contact 46 and a drain contact 47 are illustratively coupled to the source 43 and drain 44 respectively.
  • the channel 45 is illustratively in the form of a superlattice as well, but without the spintronic dopant. In other embodiments, the channel need not be a superlattice as will be appreciated by those skilled in the art. In yet other embodiments, only one of the source or drain may be a superlattice.
  • the spin valve 60 also includes a semiconductor substrate 61 that carries on its upper surface a pair of superlatices 62, 63 in spaced apart relation with a spacer 66 between the pair of superlattices. Respective electrical contacts 64, 65 are coupled to the superlattices 64, 65. As will be appreciated by those skilled in the art, one of the superlattices 64, 65 may be constructed to be pinned or be a hard ferromagnetic region, while the other is a soft ferromagnetic region.
  • a method aspect is for making a spintronic device comprising forming at least one superlattice and forming at least one electrical contact coupled thereto, with the at least one superlattice comprising a plurality of groups of layers.
  • Each group of layers may comprise a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice, at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions, and a spintronic dopant.
  • the spintronic dopant may be constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer.
  • the spintronic devices described herein including the spintronic FET and spin valve, may also be configured without the repeating structure of the superlattice as will be appreciated by those of skill in the art.
  • the materials described herein may be used in many spintronic devices, particularly for increasing the injection efficiency of -spin carriers believed due to the material compatibility at the interface.
  • the thermal stability of the devices may also be greatly enhanced believed due to the Oxygen being held in the crystal lattice, and the Mn being thermally stable adjacent the Oxygen atoms.
  • Other general references in the field of spintronics include an article by Park et al.

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Abstract

L'invention concerne un dispositif spintronique qui peut comprendre au moins un super-réseau et au moins un contact électrique relié audit super-réseau tel que ledit super-réseau comprenne une pluralité de groupes de couches. Chaque groupe de couches peut comprendre une pluralité de monocouches de semi-conducteurs de base empilées formant une partie de semi-conducteur de base présentant un réseau cristallin, et, au moins une monocouche de matériau non semi-conducteur insérée dans le réseau cristallin des parties de semi-conducteurs de base adjacentes, et un dopant spintronique. Le dopant spintronique peut être incorporé dans le réseau cristallin de la partie de semi-conducteur de base en l'intégrant dans ladite monocouche de matériau non semi-conducteur. Dans certains modes de réalisation, la structure répétée du super-réseau peut ne pas être nécessaire.
EP07753441A 2006-03-17 2007-03-19 Dispositifs spintroniques contenant des dopants spintroniques et procedes associes Withdrawn EP2002481A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US78359806P 2006-03-17 2006-03-17
US11/687,430 US7625767B2 (en) 2006-03-17 2007-03-16 Methods of making spintronic devices with constrained spintronic dopant
US11/687,422 US20080012004A1 (en) 2006-03-17 2007-03-16 Spintronic devices with constrained spintronic dopant
PCT/US2007/006814 WO2007109231A1 (fr) 2006-03-17 2007-03-19 Dispositifs spintroniques contenant des dopants spintroniques et procedes associes

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EP2002481A1 true EP2002481A1 (fr) 2008-12-17

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EP (1) EP2002481A1 (fr)
JP (1) JP2009530827A (fr)
AU (1) AU2007227418A1 (fr)
CA (1) CA2646325A1 (fr)
WO (1) WO2007109231A1 (fr)

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JP5969109B2 (ja) * 2012-03-29 2016-08-10 インテル コーポレイション 磁気状態素子及び回路

Citations (1)

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Publication number Priority date Publication date Assignee Title
US6376337B1 (en) * 1997-11-10 2002-04-23 Nanodynamics, Inc. Epitaxial SiOx barrier/insulation layer

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