EP1985017A1

EP1985017A1 - Circuit arrangement and method for actuating an electrical load

Info

Publication number: EP1985017A1
Application number: EP07711470A
Authority: EP
Inventors: Peter Trattler
Original assignee: Austriamicrosystems AG
Current assignee: Ams AG
Priority date: 2006-02-08
Filing date: 2007-02-08
Publication date: 2008-10-29
Also published as: WO2007090644A1; US20090315407A1; US7999483B2; DE102006005831A1

Abstract

A circuit arrangement (1) for actuating an electrical load (13) comprises a first connection (2) and a second connection (3) for feeding a first control signal (S1) and a second control signal (S2), a first output (23) to which the electrical load (13) can be connected, a power source (9) which is connected to the first output (23), and a control device (5). The control device is connected to a first and second connection (2, 3) and comprises a programming circuit (6) and a triggering circuit (7) which are each connected at the output end to a control output of the power source (9).

Description

description

Circuit arrangement and method for controlling an electrical load

The present invention relates to a circuit arrangement for controlling an electrical load, an arrangement comprising the circuit arrangement, a computing unit and an image recording device, and a method for controlling an electrical load.

Circuit arrangements for controlling electrical loads are used, for example, in devices of mobile communication and in cameras. They are used for example for driving a light emitting diode for generating a flash. Information about the magnitude of a current with which the electrical load is to be applied is frequently provided by a further component of such a circuit arrangement.

Object of the present invention is to provide a circuit arrangement for driving an electrical load, an arrangement with the circuit arrangement and a method for driving an electrical load, which allow a high degree of flexibility in the control of the electrical load and can be realized inexpensively.

This object is achieved with the objects of claims 1 and 7 and the method according to claim 12. Further developments and refinements are the subject matter of the dependent claims. According to the invention, a circuit arrangement for controlling an electrical load comprises a first and a second terminal, a first output, a current source and a control device. An electrical load can be coupled to the first output. The power source can be coupled to the electrical load via the first output. The control device has a programming circuit and a triggering circuit. The control device is connected to the first and the second connection. The programming circuit is connected on the output side to a first control input of the current source. The triggering circuit is connected on the output side to a second control input of the current source.

The first terminal of the circuit arrangement is used to supply a first control signal to the circuit arrangement, and accordingly the second terminal serves to supply a second control signal. The first and second control signals are supplied to the controller. The control device is designed to process the first and the second control signal. The programming circuit and the triggering circuit provide signals on the output side which are fed to the control inputs of the current source and serve for setting and triggering a current source current of the current source. The power source provides power in the form of the current source current of the load.

Advantageously, a parameter for programming the current source and the time for triggering or for switching on the current source as a function of the two supplied control signals are received by the circuit arrangement. In one embodiment, the circuit arrangement may comprise a logic circuit which is connected on the input side to the programming circuit and the triggering circuit and on the output side to a common control input of the current source. The signal provided on the output side of the programming circuit and the signal provided on the output side of the trigger circuit can therefore be linked by means of the combination circuit to form a combined control signal, which is fed to the common control input of the current source. The combination circuit may comprise an AND gate.

In an alternative embodiment, the programming circuit serves to deliver a programming signal to the first control input of the current source. The programming signal may be used to set a current value of a current source current. The programming circuit may be coupled on the input side to the first and the second terminal of the circuit arrangement.

In a development, the programming circuit has a counter which is coupled on the input side to the first terminal of the circuit arrangement and on the output side to the first control input of the current source and is provided for counting a first number n of pulses in the first control signal. Depending on the first number n of pulses, the programming signal is set.

In an alternative embodiment, the tripping circuit serves to supply a tripping signal to the second control input of the current source. The trigger circuit may be coupled on the input side to the first and the second terminal of the circuit arrangement. By means of the trigger signal the power source is switched active at a trip time so that the power source current is delivered to the load. The trigger circuit may comprise a flip-flop and an AND gate, which are suitably connected to provide the trigger signal.

The current source can be designed as a charge pump and provide an output voltage and a current source current on the output side. The power source is preferably designed as a current sink. In one embodiment, the control device can be designed as a computing unit. The circuit arrangement can be realized on a semiconductor body.

In an embodiment according to the proposed principle, an arrangement may comprise the circuit arrangement, the electrical load and a computing unit, which is coupled at a first terminal to the first terminal of the circuit arrangement.

In one embodiment, the arithmetic unit may be coupled at a second terminal to the second terminal of the circuit arrangement. Alternatively, the second terminal of the circuit arrangement can be coupled to the first terminal of the arithmetic unit via an impedance network.

In one embodiment, the arrangement additionally comprises an image recording device, which is connected to the arithmetic unit. The image recording device may comprise a control circuit and a photodetector arrangement, which may be designed as a charge-coupled device. Advantageously, the photodetector arrangement is designed as a CMOS camera arrangement. In a further development, the image recording device can on the output side be coupled via a first impedance formed as a resistor to the second terminal of the circuit arrangement. This coupling can be advantageously used to trigger a flash.

The circuit arrangement may comprise the functionality of a slave module for an inter-IC bus, abbreviated I2C bus. The first port can serve as a serial data port and the second port as a serial clock port. The arithmetic unit may include the functionality of a master device and the image acquisition device may include the functionality of another device.

The arrangement can be used for driving an electrical load, in particular a light-emitting diode, in a camera. The arithmetic unit can be designed as a baseband circuit. The arrangement can be used for driving the electrical load in a device of mobile communication.

According to the invention, a method for controlling an electrical load provides the following steps: a control device evaluates a first and a second control signal and detects during a first phase a start condition by comparing the first control signal with a predetermined value and / or the second control signal with a another predetermined value. The control device prepares a programming signal in response to the first control signal during a second phase, which follows the first phase, and outputs the programming signal to a current source. The control device outputs a triggering signal to the power source during a third phase, which is based on the second Phase follows. The trigger signal is used to enable the delivery of a current source current to supply the load.

The height of the current source current is thus advantageously set by means of the programming signal, and the time of delivery of the current source current to the electrical load by means of the trigger signal.

In a development, the circuit arrangement has a first and a second operating mode and the control device is designed to detect the operating mode during the first phase. In one embodiment, the controller sets the circuitry to a first mode of operation when, during the first phase, the rising edge of the first control signal occurs before the rising edge of the second control signal. Accordingly, the controller may set the circuitry to a second mode of operation when the rising edge of the first control signal occurs after the rising edge of the second control signal.

In one embodiment, in the first mode of operation, the trigger signal may be provided immediately or with an adjustable delay time after the rising edge of the last pulse of the first control signal during the second phase. In an alternative embodiment, in the first mode of operation, the trigger signal may be provided immediately or with an adjustable delay time after the rising edge of the second control signal that occurs during the first phase.

In the second operating mode, the triggering signal in dependence on the occurrence of a predetermined value in the second Control signal to be delivered during the third phase. In this case, in the second operating mode, the trigger signal can be delivered directly or with an adjustable delay time after a rising edge of the second control signal during the third phase. For a permanent setting of the second operating mode, the first terminal of the arithmetic unit can be connected directly to the first terminal of the circuit arrangement and via an impedance network to the second terminal of the circuit arrangement.

In a further development, a first number n of pulses of the first control signal are counted during the second phase and the programming signal is provided as a function of the first number n of pulses.

In one embodiment, the current source is designed such that it is switched to active with the arrival of an edge of the trigger signal. The current source preferably delivers the current source current to the electrical load only after expiry of an adjustable delay time.

The first control signal may be formed as a serial data signal for the I2C bus, abbreviated SDA, and the second control signal as a serial clock signal, abbreviated SCL. The control device recognizes the start condition on the basis of a falling edge of the first control signal, while the second control signal assumes the value HIGH. After the first phase, the arithmetic unit provides the first control signal with an address information. In the case of a match of the address information with an address of the circuit arrangement, the control device evaluates the data received during the following second phase. Advantageously, the data includes a programming value used to set the programming signal in the programming circuit is used. The control device detects the end of the second phase on the basis of a rising edge of the first control signal, while the second control signal has a value of HIGH.

During the third phase, in one embodiment, the first control signal may be HIGH. If, for example, a positive edge occurs in the second control signal during the third phase, then the trigger signal is provided in dependence on this edge. The trip signal may be issued immediately after such a transition. Alternatively, the trigger signal may be delayed by an adjustable delay time from the transition in the second control signal. Alternatively, a falling edge of the second control signal may be used during the third phase to form the trigger signal. There may be additional phases between the first and second phases and between the second and third phases. A positive or rising edge denotes a rising edge. Accordingly, a falling edge is referred to as a negative or falling edge.

The invention will be explained in more detail below with reference to several embodiments with reference to FIGS. Functional or equivalent components or signals bear the same reference numerals. Insofar as circuit parts, components or signals correspond in their function, their description is not repeated in each of the following figures.

FIGS. 1A to 1C show exemplary embodiments of an arrangement according to the proposed principle, Figure ID shows an exemplary embodiment of a control device coupled to a power source and

FIGS. 2A to 2F show exemplary courses of a first and a second control signal as a function of the time t.

FIG. 1A shows an exemplary embodiment of an arrangement with a circuit arrangement 1, an electrical load 13, a computing unit 30 and an image recording device 40. The circuit arrangement 1 comprises a control device 5 with a programming circuit 6 and a triggering circuit 7, a current source 9, a charge pump 10, a first and a second terminal 2, 3, a supply voltage terminal 19 and a first and a second output 23, 4. The control device 5 and thus the programming circuit 6 and the trigger circuit 7 are connected to the first and the second terminal 2, 3 connected. The programming circuit 6 has a counter 26. The programming circuit 6 and the triggering circuit 7 are connected on the output side to a first and a second control terminal of the current source 9. The current source 9 is connected to the first output 23. It couples the first output 23 to a reference potential terminal 8. The second output 4 is coupled to the supply voltage terminal 19. The charge pump 10 is connected between the supply voltage terminal 19 and the second output 4 and is connected via two further terminals of the circuit arrangement 1 with a first capacitor 14.

The electrical load 13 comprises a light-emitting diode 11, which between the second output 4 and the first output 23 of the Circuit 1 is connected. The arrangement comprises a battery 16, which is connected between the supply voltage terminal 19 and the reference potential terminal 8. The arithmetic unit 30 comprises a first terminal 31, which is connected to the first terminal 2 of the circuit arrangement 1. Furthermore, the first terminal 31 of the arithmetic unit 30 is coupled to the second terminal 3 of the circuit arrangement 1 via an impedance network 20, 21. The impedance network 20, 21 is formed as a low-pass filter and includes a resistor 20 and a capacitor 21. The resistor 20 couples the first terminal 31 of the arithmetic unit 30 to the second terminal 3 of the circuit arrangement 1. The second terminal 3 of the circuit arrangement 1 is over the capacitor 21 is coupled to the reference potential terminal 8. The arithmetic unit 30 is connected to a coupling connection 33 with a first connection 41 of the image recording device 40. The image recording device 40 comprises a control circuit 45, which is connected to a photodetector arrangement 46 and to the first terminal 41 of the image recording device 40.

The battery 16 is used to deliver a battery voltage Vbat to the supply voltage terminal 19 of the circuit arrangement 1. The battery voltage Vbat is supplied to the charge pump 10. The charge pump 10 provides an output voltage VA at the second output 4 of the circuit arrangement 1 by means of the first capacitor 14. The arithmetic unit 30 outputs at the first terminal 31 a first control signal Sl which is fed to the first terminal 2 of the circuit arrangement 1. From the first control signal Sl, a second control signal S2 is generated by means of the impedance network 20, 21, which is supplied to the second terminal 3 of the circuit arrangement 1. In dependence of the first and the second control signal Sl, S2, the control device 5 a programming signal SP and a trigger signal ST, which are supplied to a first and a second control terminal of the current source 9 ready. By means of the counter 26, a first number n pulses in the first control signal Sl is counted. The programming signal SP is output from the programming circuit 6 in response to the first number n, whereas the trigger signal ST is provided by the trigger circuit 7. Depending on the programming signal SP, a value of a current source current I of the current source 9 is set. By means of the trigger signal ST, a switch-on time or trip time t3 of the current source 9 can be set. In the case of an activation of the current source 9, the current source current I flows from the charge pump 10 through the electrical load 13 and through the current source 9 to the reference potential connection 8. The photodetector arrangement 46 provides electrical signals as a function of incident light signals, which serve as image information via the control circuit 45 of the arithmetic unit 30 are supplied.

Advantageously, by means of the programming circuit 6 in the control circuit 5, the current source current I and thus the luminosity or the duration of the light emitting diode 11 are set. Advantageously, by means of the tripping circuit 7 in the control circuit 5, a trigger signal ST can be provided, with which a tripping time t3 of the

Current source 9 is adjustable, so that from the light emitting diode 11, a flash of light can be emitted.

In an alternative embodiment, the charge pump 10 may be connected to a second capacitor 15 via two additional terminals of the circuit arrangement 1. The charge pump 10 sets by means of the first capacitor 14 and additionally by means of the second capacitor 15, the output Voltage VA at the second output 4 of the circuit 1 ready.

Alternatively, the electrical load 13 may comprise a first smoothing capacitor 12, which connects the second output 4 to the reference potential terminal 8.

In an alternative embodiment, the arrangement has a second smoothing capacitor 17, which is connected in parallel with the battery 16 and couples the supply voltage terminal 19 to the reference potential terminal 8.

FIG. 1B shows a further exemplary embodiment of the arrangement with the circuit arrangement 1, the arithmetic unit 30, the image recording device 40, the electrical load 13 and the battery 16. The circuit arrangement 1 according to FIG. 1B can be the same circuit arrangement 1 as in FIG. The same semiconductor body comprising the circuit arrangement 1 can be externally connected both according to FIG. 1A and according to FIG.

In contrast to the arrangement according to FIG. 1A, the arrangement according to FIG. 1B shows a first impedance 44, which couples an output 42 of the image recording device 40, which is connected to the control circuit 45 of the image recording device 40, to the second connection 3 of the circuit arrangement 1. In addition, the second terminal 3 of the circuit arrangement 1 is connected to a second terminal 32 of the arithmetic unit 30. If the second terminal 32 of the computing unit 30 is switched to an open operating state, a signal at the output 42 of the image recording device 40 is transmitted via the first impedance 44 to the second terminal 3 of the circuit arrangement 1 as the second control signal S2. tet. Advantageously, a time t3 for triggering the flash can thus be specified by the control circuit 45.

In an alternative embodiment, the arrangement has no first impedance 44 and thus no coupling of an output 42 of the image recording device 40 to the second terminal 3 of the circuit arrangement 1. According to this embodiment, the arithmetic unit 30 uses the second control signal S2 to set the triggering time t3 for the flash, and for this purpose uses the connection of the second terminal 32 of the arithmetic unit 30 to the second terminal 3 of the circuit arrangement 1.

FIG. 1C shows another exemplary embodiment of the arrangement with the control circuit 1, the electrical load

13, the arithmetic unit 30, the image pickup device 40 and a further circuit 47. The arrangement has an I2C bus 18. The arithmetic unit 30 is designed as a master module and the circuit arrangement 1, the image recording device 40 and the further circuit 47 are designed as slave modules for the I2C bus 18. In contrast to the arrangements according to FIGS. 1A and 1B, the first terminal 31 of the arithmetic unit 30 is connected to the first terminal 2 of the circuit arrangement 1, a second terminal 43 of the image recording device 40, a first terminal 48 of the further circuit 47 and via a resistor 25 to the Supply voltage terminal 19 connected. The second terminal 32 of the arithmetic unit 30 is connected to the second terminal 3 of the circuit arrangement 1, the first terminal 41 of the image recording device 40 and a second terminal 49 of the further circuit 47. In addition, the second terminal 3 of the circuit arrangement 1 is connected to the output 42 of the image recording device 40 via the coupled first impedance 44. The first impedance 44 is designed as a resistor.

The resistor 25 serves to supply the battery voltage Vbat to that line of the I2C bus 18, which couples the terminals 2, 31, 43, 48. If none of the terminals 2, 31, 43, 48 is switched to a value LOW, then the line of the I2C bus 18, which connects the four terminals 2, 31, 43, 48, is at the value HIGH. The line which couples the four terminals 3, 32, 41, 49 is acted on in a first operating state of the arrangement with a signal which is provided by the second terminal 32 of the arithmetic unit 30. In a second operating state of the arrangement in which the flash is to be triggered, the second terminal 32 of the computing unit 30 is switched to a tristate state and the line is supplied with a signal which is provided by the output 42 of the image recording device 40. According to the I2C bus specifications, the first and second control signals S1, S2 are provided by the computing unit 30 at the first and second terminals 31, 32. A signal at the output 42 of the image recording device 40 is approximately equal to the second control signal S2, provided that the second terminal 32 of the arithmetic unit 30 and the first terminal 41 of the Bildaufnahmeein- device 40 and the second terminal 49 of the further circuit 47 are in an open operating state , Advantageously, programming values of the programming circuit 6 can thus be fed to the control device 5 via the I2C bus 18. Advantageously, the triggering signal ST can be provided as a function of a signal at an output 42 of the image recording device 40. In an alternative embodiment, unlike the circuit arrangement 1 according to FIGS. 1A, 1B and 1C, the circuit arrangement 1 may have a current source 9 with a control input instead of the first and the second control input.

Figure ID shows an exemplary embodiment of a control device 5, comprising a programming circuit 6 and a trigger circuit 7, and a coupling of the control device 5 with a power source 9, as it can be used in the Schaltungsan- orders 1 according to the figures IA to IC.

The programming circuit 6 comprises the counter 26 and a NOR gate 50. The NOR gate 50 is coupled on the input side to the first and the second connection 2, 3 of the circuit arrangement 1. The counter 26 is connected at a counter signal input CZ to the first terminal 2 of the circuit arrangement 1 and at a reset input R to an output of the NOR gate 50. The triggering circuit 7 has an AND gate 28 and a flip-flop 27. The flip-flop 27 is coupled on the input side to the first and the second terminal 2, 3 of the circuit arrangement 1. The flip-flop 27 is designed as a single-edge-controlled flip-flop, which can also be referred to as a non-transparent flip-flop. The flip-flop 27 can be realized as a master-slave flip-flop. In this case, a data input D of the flip-flop 27 is connected to the first terminal 2 and a clock input C of the flip-flop 27 is connected to the second terminal 3. The AND gate 28 is connected on the input side to the second terminal 3 of the circuit arrangement 1 and a data output Q of the flip-flop 27. That's it

Flipflop 27 realized such that it takes on a rising edge at its clock input C applied to its data input D value and approximately delay free as value at its data output Q provides. Only at a subsequent rising edge at the clock input C, the flip-flop 27 can assume a voltage applied to its data input D new value. On the output side, the counter 26 of the programming circuit 6 and the AND gate 28 of the trigger circuit 7 via a combination circuit having a further AND gate 51, coupled to a control input of the current source 9 for providing a combined control signal SPT.

By means of the further AND gate 51 is achieved that a default value for the current source current I is forwarded to the current source 9 only at a value HIGH of the trigger signal ST. At the time of tripping t3, the current source 9 provides the current source current I.

In an alternative embodiment, the counter 26 has a second number m outputs, which are coupled to control inputs of the current source 9 via a second number m of AND gates 51. Advantageously, thus, the current source current I can be programmed in smaller steps.

FIG. 2A shows an exemplary course of the first and second control signals S1, S2, as may occur in the arrangement of FIG. 1A. In a first phase Pl, the first control signal Sl has a rising edge. Time delayed, the second control signal S2 also shows a rising edge. The time delay is dependent on the impedance network 20, 21, which is connected upstream of the second terminal 3. According to the example in FIG. 2A, FIG

Start condition, which is met at a time tl, both for the first and for the second control signal Sl, S2 a value HIGH. In the following to the first phase Pl second phase P2 shows the first control signal Sl a first number n pulses, by way of example, three pulses are shown. The second control signal S2 is virtually unchanged during the second phase P2 due to the low-pass characteristic of the impedance network 20, 21 at the value HIGH. As soon as the first control signal S1 is constantly at a value HIGH, the end of the second phase P2 and a beginning of a third phase P3 have been reached. In the third phase P3, the first and the second control signal Sl, S2 have a value HIGH. In the third phase P3 becomes after expiration of an adjustable

Delay time Td means of the drive signal ST, the current source 9 is switched to an active operating state. Thus, it is advantageously possible to set both a value of the current source current I and a tripping time t3 by means of a single output signal at the first terminal 31 of the arithmetic unit 30.

FIG. 2B shows exemplary profiles of the first and second control signals S1, S2, as may be encountered in an arrangement of FIG. 1B. As in FIG. 2A, the starting condition is met in FIG. 2B as soon as the first and the second control signal S1 ₇ S2 have the value HIGH. This is the case at a time tl. In the second phase P2, the first control signal Sl shows a first number n of pulses. If the first control signal S1 constantly has the value HIGH, then the end of the second phase P2 and the beginning of the third phase P3 have been reached. The second control signal S2 has the value HIGH during the second phase P2 and at the beginning of the third phase P3. At a time t2, the second terminal 32 of the arithmetic unit 30 is switched to an open state. The second control signal S2 is thus from the time t2 thus by means of a signal at the output 42 of the image pickup device 40 in response to the first impedance 44 generated. In the example according to FIG. 2B, the second control signal is raised from the value LOW to the value HIGH in the tripping time t3 by means of the image recording device 40. The positive edge of the second control signal S2 triggers the trigger signal ST, with which the current source 9 is switched to an active operating state at the tripping time t3.

In one embodiment of the circuit arrangement 1, a first or a second operating mode A, B is set as a function of the first and the second control signal S1 ₇ S2 during the first phase P1. With the courses of the control signals S1 and S2 according to FIG. 2A, the first operating mode A and with the courses of the first and second control signals S1, S2 according to FIG. 2B, the second operating mode B is switched on. According to FIG. 2A, the positive edge of the first control signal occurs before the positive edge of the second control signal S2. On the other hand, in FIG. 2B the positive edge of the first control signal S1 occurs after the positive edge of the second control signal S2. Alternatively, the positive edge of the second control signal S2 may also occur before the positive edge of the first control signal S1 in order to switch the circuit arrangement 1 into the second operating mode B.

In the first operating mode A, the trigger signal ST is automatically switched by the circuit arrangement 1, so that the current source 9 is switched to the tripping time t3 in an active operating state. On the other hand, in the second operating mode B, the second control signal S2 is evaluated and the trigger signal ST is provided only on a positive edge of the second control signal S2 during the third phase P3. FIGS. 2C and 2D show exemplary embodiments of progressions of the first and second control signals S1, S2 in the case of an arrangement with I2C bus 18. According to the I2C specification, a start is triggered by the first control signal S1 having a falling edge while the second control signal S2 is at the value HIGH. The first control signal Sl is designed as an SDA signal and the second control signal S2 as an SCL signal. This start condition defines the first phase Pl. The second control signal S2 serves as a clock signal, while the first control signal

Sl transfers data. In a phase following the first phase Pl, an address is output by the arithmetic unit 30. The slave components such as the circuit arrangement 1, the image recording device 40 and the further circuit 47 are designed to compare the address with their own address. The addressed module evaluates data following the address. If the circuit arrangement 1 is addressed, the data sent after the address comprise a programming value, which is supplied to the programming circuit 6 and serves to provide the programming signal SP. After the end of the second phase P2, the first and second control signals S1, S2 are determined in accordance with the I2C specifications such that a stop condition is reached.

At time t2, the second terminal 32 of the arithmetic unit 30 is switched to an open state. Therefore, the image pickup device 40 can provide the second control signal S2 from this time t2 by means of a signal at the output 42 and the first impedance 44. With a positive edge in the signal at the output 42 of the image recording device 40, a positive edge of the second control signal S2 is realized, so that the trigger signal ST to the output Dissolution time t3, the power source 9 switches to an active state.

FIG. 2D shows a further exemplary course of the two control signals S1, S2 in an arrangement with I2C bus 18. In contrast to the curves according to FIG. 2C, in FIG. 2D the second control signal S2 is at a value HIGH at the beginning of the third phase, before the second terminal 32 of the arithmetic unit 30 is switched to an open operating state at the time t2. Only the circuit arrangement 1 responds to the change of the second control signal S2 during the third phase P3, in which no regular communication over the I2C bus 18 is performed. Thus, the image recording device 40 can advantageously determine the triggering time t3 of a flash light.

FIG. 2E shows a further exemplary course of the signals. The signals according to FIG. 2E can occur in the arrangement according to FIG. 1A, into which the control device 5 is dimensioned according to FIG. ID. With respect to the first and second control signals Sl, S2, reference is hereby made to the description of Figure 2A, which is not repeated here. The first and second control signals Sl, S2 are supplied to the NOR gate 50. A signal at the output of the NOR gate 50 is fed to the reset input R of the counter 26. The signal at the output of the NOR gate 50 is at the beginning of the first phase Pl at the value HIGH, so that the counter 26 is reset at this time. After resetting the counter 26 counts the pulses in the first control signal Sl. These are supplied to the counter 26 in the second phase P2. A clock signal applied to the clock input C of the flip-flop 27 corresponds to the second control signal S2. Since the flip-flop 27 is an edge-triggered flip-flop, which assumes the value at a rising edge of the clock signal applied to the data input D, the flip-flop 27 in the first phase Pl takes the value HIGH at the time t 1 and provides an output signal SQ at the data output Q ready with the value HIGH. The output signal SQ remains at the value HIGH. The two inputs of the AND gate 28 are the second control signal S2 and the output signal SQ supplied. At the output of the AND gate 28, the trigger signal ST is provided. The trigger signal ST is from the time tl to the end of the third phase P3 to the value HIGH. With the rising edge of the triggering signal ST at the time t ¹ , the time interval of the delay time Td ¹ , which ends at the tripping time t ³ , begins. The current source 9 outputs the current source current I after the delay time Td 'has elapsed. Advantageously, the delay time Td ^{1 is set} such that the tripping time t3 is encompassed by the third phase P3.

FIG. 2F shows a further exemplary course of the signals. The signals according to FIG. 2F can occur in the arrangement according to FIG. 1B, into which the control device 5 according to FIG. ID is inserted. With respect to the first and second control signals Sl, S2, reference is hereby made to the description of Figure 2B, which will not be repeated here. The signals of the counter 26 correspond to the description given in FIG. 2E. In the first phase Pl, a rising edge occurs in the second control signal S2, so that the flip-flop 27 takes over the value LOW applied to the data input D and therefore provides the output signal SQ with the value LOW from a time tθ. At a rising edge of the second control signal S2 in the third phase P3 over- takes the flip-flop 27 which is applied to the data input D value HIGH and provides the output signal SQ with the value HIGH. This occurs at a time t4. Only from the rising edge in the second control signal S2 in the third phase P3, the trigger signal ST has the value HIGH, so that as in Figure 2E, the delay time Td ¹ begins. Corresponding to FIG. 2E, in the third phase P3, after expiry of the delay time Td ¹ at the triggering time t3, the current source 9 emits the current source current I.

Advantageously, an embodiment of the control device 5 can be operated both in an arrangement according to FIG. 1A and in an arrangement according to FIG. If the output signal SQ has the value HIGH at the end of the first phase Pl, then the arrangement is in the first operating mode A. However, if the output signal SQ is at the value LOW at the end of the first phase Pl, the arrangement is in the second operating mode B. can be distinguished by means of the flip-flop 27 and the output signal SQ between the two operating modes A, B. The output signal SQ has the same value in both operating modes A, B during the second phase P2 as at the end of the first phase P1.

Advantageously triggers in both arrangements, the rising edge of the second control signal S2, the trigger signal ST, so that the power source 9 is from the triggering time t3 in an active operating state in which it provides the current source current I. In this case, the rising edge of the second control signal S2 causes a rising edge of the trigger signal ST. The triggering of the current source 9 is thus performed in response to a rising edge of the second control signal S2 and the delay time Td ¹ . Advantageously, the current source 9 reacts with a delay the delay time Td 'on the rising edge of the trigger signal ST. While in the first operating mode A, the rising edge of the trigger signal ST is generated in response to the first rising edge of the second control signal S2, the rising edge of the trigger signal ST is generated in the second operating mode B in response to the second rising edge of the second control signal S2.

In one embodiment, the delay time Td ¹ can be set.

In alternative embodiments to the curves according to FIGS. 2B to 2F, the triggering instant t3 is set as a function of a falling edge of the second control signal S2.

LIST OF REFERENCE NUMBERS

1 circuit arrangement

2 first connection 3 second connection

4 second exit

5 control device

6 programming circuit

7 Trip circuit 8 Reference potential connection

9 power source

10 charge pump

11 LED

12 first smoothing capacitor 13 electrical load

14 first capacitor

15 second capacitor

16 battery

17 second smoothing capacitor 18 I2C bus

19 Supply voltage connection

20 resistance

21 capacitor

23 first output 25 resistor

26 counters

27 flip-flop

28 AND gate

29 delay circuit 30 arithmetic unit

31 first connection

32 second connection

33 coupling connection 34 fourth connection

40 image recording device

41 first connection

42 output 43 second connection

44 first impedance

45 control circuit

46 photodetector arrangement

47 more circuit 48 first port

49 second connection

50 NOR gates

51 AND gates

A first operating mode B second operating mode

C clock input

CZ counter signal input

D data input

I current source current Pl first phase

P2 second phase

P3 third phase

Q data output

R Reset input Sl First control signal

52 second control signal SP programming signal

SPP further programming signal

SPT combined control signal SQ output signal

ST trip signal t time

Td, Td ¹ delay time tθ, tl, t2, t4 Time t3 tripping time

VA output voltage

Vbat battery voltage

Claims

claims

1. Circuit arrangement for controlling an electrical load, comprising - a first terminal (2) for supplying a first control signal (S1),

a second connection (3) for supplying a second control signal (S2),

a first output (23) to which an electrical load (13) can be coupled,

a current source (9) coupled to the first output (23),

- A control device (5) which is coupled to the first and the second terminal (2, 3), comprising - a programming circuit (6), which is output side coupled to a first control input of the current source (9), and

a trigger circuit (7) which is coupled on the input side to the first and the second terminal (2, 3) and on the output side to a second control input of the current source (9).

2. A circuit arrangement according to claim 1, characterized in that the programming circuit (6) for delivering a programming signal (SP) to the first control input of the current source (9) for setting a current value of a current source current (I) and the trigger circuit (7) for delivering a Trigger signal (ST) to the second control input of the current source (9) for triggering a delivery of the current source current (I) to the electrical

Load (13) is designed.

3. Circuit arrangement according to claim 1 or 2, characterized in that the programming circuit (6) comprises a counter (26) whose input side is coupled to the first terminal (2) and output side to the first control input of the current source (9) and to counting pulses of the first control signal (Sl) is designed.

4. Circuit arrangement according to one of claims 1 to 3, characterized in that the trigger circuit (7) comprises a flip-flop (25) and an AND gate (28) for generating the trigger signal (ST).

5. Circuit arrangement according to one of claims 1 to 4, characterized in that the control device (5) for operating the trigger circuit (7) in one of two operating modes (A, B) in response to the first and / or the second control signal (Sl , S2) is designed.

6. Circuit arrangement according to one of claims 1 to 5, characterized in that the first control input of the current source (9) and the second control input of the current source (9) are designed as a common control input of the current source (9).

7. Arrangement comprising the circuit arrangement (1) according to one of claims 1 to 6, to the first output (23) connected electrical load (13), a computing unit (30) having a first terminal (31) connected to the first terminal (11) the circuit arrangement (10) for supplying the first

Control signal (Sl) is connected, and an image pickup device (40) which is coupled to the arithmetic unit (30).

8. Arrangement according to claim 7, characterized in that the second terminal (3) of the circuit arrangement (1) via an impedance network (20, 21) to the first terminal (31) of the arithmetic unit (30) is coupled.

9. Arrangement according to claim 7, characterized in that the second terminal (3) of the circuit arrangement (1) with a second terminal (32) of the arithmetic unit (30) and via a first impedance (44) with an output (42) the image pickup device (40) is coupled.

10. Arrangement according to one of claims 7 to 9, characterized in that the arithmetic unit (30) is designed as a baseband circuit.

11. The use of the circuit arrangement (1) according to one of arrival claims 1 to 6 for driving an electrical load (13), in particular a light-emitting diode (11), in a camera or a device of the mobile communication.

12. A method for controlling an electrical load, comprising the following steps:

Detecting a start condition by evaluating a first and a second control signal (Sl, S2) by means of a control device (5),

- Setting a programming signal (SP) in the control device (5) in response to the first control signal

(Sl) and output of the programming signal (SP) to a power source (9) and - Outputting a trigger signal (ST) from the control device (5) to the current source (9) for triggering a current source current (I), which is delivered to the electrical load (13).

13. The method according to claim 12, characterized by

Counting a first number n of pulses of the first control signal (Sl) and setting the programming signal (SP) in dependence on the first number of n pulses.

14. The method according to claim 12 or 13, characterized by

Delivering the trigger signal (ST) to the current source (9) as a function of the second control signal (S2).

15. The method according to claim 12 or 13, characterized by

Delivering the trigger signal (ST) to the current source (9) in response to a falling edge of the last pulse of the first control signal (Sl) and an adjustable delay time (Td).

16. The method according to claim 14 and 15, characterized by

Operating the trigger circuit (7) in a first or a second operating mode (A, B) in response to the first and / or the second control signal (Sl, S2), wherein the trigger signal (ST) - in the first operating mode (A) in Dependence on the falling edge of the last pulse in the first control signal (Sl) and the adjustable delay time (Td) and - In the second operating mode (B) in response to the second control signal (S2) is emitted.

17. The method according to any one of claims 12 to 14, characterized by

Generating an edge of the trigger signal (ST) by means of an edge of the second control signal (S2) and triggering the current source current (I) in response to the edge of the trigger signal (ST) and an adjustable delay time (Td ¹ ).

18. The method according to claim 13, characterized by

Providing the first control signal (Sl) as a serial data signal and the second control signal (S2) as a serial clock

Signal of an I2C bus (18) and reading in of a binary coded programming value and setting of the programming signal (SP) in dependence on the programming value.

19. The method according to claim 18, characterized by

Delivering the trigger signal (ST) to the current source (9) in response to the second control signal (S2), while the first control signal (Sl) has a value HIGH.