Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
  • H04L12/40—Bus networks
  • H04L12/40006—Architecture of a communication node
  • H04L12/40013—Details regarding a bus controller
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
  • H04L12/40—Bus networks
  • H04L12/40006—Architecture of a communication node
  • H04L12/40032—Details regarding a bus interface enhancer
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
  • H04L12/40—Bus networks
  • H04L12/407—Bus networks with decentralised control
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
  • H04L12/40—Bus networks
  • H04L12/407—Bus networks with decentralised control
  • H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
  • H04L12/4135—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD] using bit-wise arbitration
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L47/00—Traffic control in data switching networks
  • H04L47/50—Queue scheduling
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/90—Buffering arrangements
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/90—Buffering arrangements
  • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/90—Buffering arrangements
  • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
  • H04L12/40—Bus networks
  • H04L2012/40208—Bus networks characterized by the use of a particular bus standard
  • H04L2012/40241—Flexray

Definitions

• the invention relates to a subscriber interface between a FlexRay communication module and a FlexRay subscriber assigned to the FlexRay communication module.
• the FlexRay communication block is connected to a FlexRay communication connection via which bots are transmitted.
• the FlexRay communication block comprises a message memory for temporarily storing messages from the FlexRay communication connection or for the FlexRay communication connection.
• the invention also relates to a method for transmitting messages between a FlexRay communication module and a FlexRay subscriber assigned to the FlexRay communication module via a subscriber interface.
• the FlexRay communication block is connected to a FlexRay communication connection via which messages are transmitted.
• the FlexRay communication module includes a Message memory for buffering messages from the FlexRay communication connection or for the FlexRay communication connection.
• FlexRay protocol A well-known protocol for this is the FlexRay protocol, which is currently based on the FlexRay protocol specification v2.0.
• the FlexRay protocol defines a fast, deterministic and fault-tolerant bus system, especially for use in a motor vehicle.
• the data transmission according to the FlexRay protocol takes place according to a Time Division Multiple Access
• TDMA time division multiple access
• the data transmission over the communication link is carried out in regularly recurring transmission cycles, each of which is divided into a plurality of data frames, which are also referred to as time slots.
• the subscribers or the messages to be transmitted are assigned fixed time slots in which they have exclusive access to the communication connection.
• the time slots are repeated in the specified transmission cycles, so that the time at which a message is transmitted over the bus can be accurately predicted and the bus access is deterministic.
• FlexRay divides the transmission cycle, which can also be referred to as cycle or bus cycle, into a static and a dynamic part.
• the fixed time slots are located in the static part at the beginning of a bus cycle.
• the time slots are allocated dynamically.
• FlexRay communicates via two physically separate lines of the communication link at a maximum data rate of 10 MBiVs (10 MBaud). Every 5 ms, and even every 2.5 ms in some communication systems, one bus cycle is completed.
• the two channels correspond to the physical layer, in particular the OSI (Open System Architecture) layer model.
• the two channels are mainly used for the redundant and thus fault-tolerant transmission of messages, but can also transmit different messages, which would double the data rate. FlexRay can also be operated at lower data rates.
• a FlexRay device which can also be referred to as a FlexRay network node or host, contains a participant or host processor, a FlexRay or communication controller, and a bus guardian in bus monitoring.
• the user processor delivers and processes the data that is transmitted via the FlexRay communication controller and the FlexRay communication connection.
• Messages or message objects with eg up to 254 data bytes can be configured for communication in a FlexRay network.
• an interface module consisting of two parts, wherein one sub-module is independent of the subscriber and the other sub-module is subscriber-specific.
• the subscriber-specific sub-module which is also referred to as Customer CPU Interface (CIF) connects a customer-specific subscriber in the form of a subscriber-specific host CPU to the FlexRay communication module.
• the subscriber-independent submodule which is also referred to as the Generic CPU Interface (GIF), represents a generic, that is to say general, CPU interface, via which different customer-specific host CPUs are addressed by means of corresponding subscriber-specific submodules, that is Customer CPU Interfaces (CIFs) connect the FlexRay communication module.
• the interface can be flexibly adapted by simply varying the subscriber-specific sub-module to any trained or kind of participants.
• the sub-blocks can also be realized within the one interface block in each case in software, that is, each sub-block as a software function.
• the state machine in the FlexRay communication block may be hardwired into hardware.
• the sequences can also be hardwired into hardware.
• the state machine can also be freely programmable in the communication module via the subscriber interface by the subscriber.
• the information preferably contains the type of access and / or the type of access and / or the access address and / or the data size and / or control information on the data and / or at least one information for securing data.
• the message memory of the FlexRay communication module is preferably designed as a single-ported RAM (Random Access Memory).
• This RAM memory stores the messages or message objects, ie the actual user data, together with configuration and status data.
• the exact structure of the message memory of the known communication module can be found in the cited document DE 10 2005 034 744. It has been found that the transmission of the messages between the message memory of the FlexRay communication module and the FlexRay subscriber takes place only relatively slowly and at the expense of large resources on the part of the subscriber, in particular with regard to the required computing power of the host CPU and the required memory space.
• a constant activity of the host CPU (possibly DMA, direct memory access) is required in order to transfer newly received buffer contents of the message memory of the communication module into the memory of the host CPU , With the so-called polling, the host CPU can regularly check whether new messages have been stored in the message memory of the subscriber interface. Direct access of the host CPU to the message memory of the communication block is not possible. In particular, if the data rate of the FlexRay communication link is fully utilized, this proves to be disadvantageous. In addition, waiting times of the host CPU for setting registers etc. must be accepted.
• the present invention is therefore an object of the invention to provide a FlexRay communication module available, which optimally the
• the subscriber interface has an arrangement for buffering the messages to be transmitted between the FlexRay communication module and the FlexRay subscriber, the arrangement comprising at least one message memory comprising a first connection to the FlexRay communication module and a second connection to the subscriber.
• a further message memory is provided in the area of the subscriber interface into which the content of the message memory of the FlexRay communication module can be transmitted without or with minimal load on the host CPU.
• the host CPU of the FlexRay station can access the mirrored data in the message memory of the subscriber interface at maximum speed.
• the host CPU can also receive messages or data packets at a suitable point during a transmission cycle and release them for transmission. The entire procedure does not require waiting times for the transmissions in the message memory of the FlexRay communication block and is only limited by the performance of the interface of the message memory of the FlexRay communication block.
• the message memory of the subscriber interface is designed such that read or write access to the message memory can be accessed via one of the connections in writing or reading and at the same time via the other connection.
• the message memory of the subscriber interface as a dual-port RAM (Random Access Memory with two ports) is formed. With dual-port RAM, read access is possible from two sides at the same time.
• Possible types of DP-RAM that may be used in the present invention are: one side of the DP-RAM can write, the other side can read, one side of the DP-RAM can read and write, and the other side can read, one side of DP-RAM can read and write and the other side can write, and one side of DP-RAM can read and write and the other side can read and write.
• the first type of DP RAM mentioned above has the lowest hardware overhead (gate count) and the fourth type mentioned has the highest hardware overhead. Without considering the testability, all proposed RAMs would be feasible with the first mentioned DP-RAM type. Possible testability applications may require the use of one of the above-mentioned second to fourth DP-RAM types.
• Such memories usually have separate address and data bus systems and an arbitration logic that initiates appropriate measures for collision resolution in the case of simultaneous write operations. Due to the simultaneous access, two otherwise separate systems, namely the FlexRay communication module on the one hand and the host CPU of the FlexRay Participants on the other hand, working with shared data without restricting each other in the access speed.
• the subscriber interface has a state machine which controls a transmission of messages between the message memory of the FlexRay communication module and the message memory of the subscriber interface in both directions.
• the state machine which can also be referred to as a state machine or as a finite state machine, ensures that the contents of the message memory of the communication block for the host CPU invisible or without intervention of the host CPU in the message memory (eg Dual Port RAM) of the subscriber interface is transmitted.
• the message memory of the subscriber interfaces has a writing area in which, via the FlexRay
• Communication link are stored to transmit messages, and has a read area in which messages received from the FlexRay communication link are stored.
• the names Write area and Read area were chosen from the point of view of the host CPU of the subscriber.
• Data to be written to and transferred via the FlexRay data bus is stored in the write area of the buffer, and data received from the FlexRay data bus are written to the read memory and read from there into the subscriber.
• registers are assigned to the message memory of the subscriber interface, preferably a write register being assigned to the write area of the message memory and a read register to the read area of the message memory.
• the status of the message memory (eg dual-port RAM) of the subscriber interface is transmitted via the registers from the to-state machine to the FlexRay communication block.
• the read bits are reset.
• the buffer received by the FlexRay communication block is transmitted by the state machine.
• the FlexRay communication module signals the presence of a buffer content newly received via the subscriber interface to the state machine.
• the state machine then transfers the buffer contents from the FlexRay communication block to the message memory (eg dual-port RAM).
• the state machine displays the transmission in the read status register and, if necessary, triggers an interrupt.
• the host CPU can then determine which read buffers have been rewritten by the state machine by reading the read status register.
• the identifier for example the number, of the last buffer successfully transmitted by the state machine (each separated according to read and write memory) is stored by the state machine in a further register, a so-called read-write position register, of the user interface.
• the transfer of the buffer written by the host CPU into the message memory, for example the dual-port RAM, of the subscriber interface takes place in the same way as the reading.
• the buffer to be sent is determined by evaluating the write register.
• the bit number in the register corresponds to the priority during transmission.
• the state machine scans the bits of the register from bottom to top.
• the corresponding buffer of the first bit set to "1" is transferred from the message memory (eg dual-port RAM) to the message memory of the communication block.
• the associated bit in the write register and the buffer number are written to the read / write position register of the subscriber interface. This process is carried out continuously.
• the message memory of the subscriber interface has sufficient storage space for storing therein at least the data of a transmission cycle via the FlexRay communication connection.
• a transmission cycle via the FlexRay communication connection is subdivided into a plurality of data frames, wherein the message memory of the subscriber interface advantageously has sufficient storage space in order to store at least the data frames in their maximum size, the so-called buffers, of a transmission cycle.
• the message memory of the subscriber interface preferably has sufficient storage space to store therein 128 data frames in their maximum size (so-called buffers).
• the registers assigned to the message memory of the subscriber interface then have a size of 1 bit per data frame, preferably 128 bits.
• the state machine or the host CPU of the user is informed when data for removal in the direction of the message memory of the communication module or in the direction of the memory of the host CPU is available.
• the read or write register For each buffer of the message memory (eg dual-port RAM) of the subscriber interface, one bit is available in the read or write register.
• the messages to be transmitted between the FlexRay communication module and the subscriber be temporarily stored in an arrangement of the subscriber interface for buffering the messages, wherein the arrangement comprises at least one message memory which can be accessed simultaneously by the FlexRay communication module and the subscriber.
• the synchronous access to the message memory or the registers is controlled by an arbiter of the subscriber interface. This one can do that too Allow the state machine to be configured by the host CPU of the subscriber.
• Figure 1 shows a communication module and its connection to a
• Figure 3 shows the structure of a message memory of the communication module of Figure 2;
• FIGS. 4 to 6 show the architecture and the process of a data access in the direction from the subscriber to the message memory in a schematic representation
• FIGS. 7 to 9 show the architecture and the process of data access in the direction from the message memory to the subscriber;
• Figure 10 is a schematic representation of the structure of a message manager and finite state machines contained therein;
• FIG. 11 shows components of the communication module from FIGS. 1 and 2 as well as the subscriber and the corresponding data paths controlled by the message administrator in a schematic representation
• FIG. 12 shows the access distribution to the message memory with reference to FIG.
• FIG. 13 shows a subscriber interface according to the invention in accordance with a first preferred embodiment of the invention
• FIG. 14 shows a subscriber interface according to the invention in accordance with a second preferred embodiment of the invention.
• Figure 15 is a sequence diagram of a method according to the invention for the transmission of messages from an input memory
• FIG. 16 shows a sequence diagram of a method according to the invention for transmitting messages from a transmission memory.
• FIG. 1 schematically shows a FlexRay communication module 100 for connecting a subscriber or host 102 to a FlexRay communication connection 101, that is to say the physical layer of the FlexRay.
• the FlexRay communication module 100 is connected to the subscriber or subscriber processor 102 via a connection 107 and via a connection 106 connected to the communication link 101.
• a first arrangement 105 serves for storing, in particular clipboard, at least part of the messages to be transmitted.
• a second arrangement 104 is connected via the connections 107 and 108.
• a third arrangement 103 is connected via the connections 106 and 109, as a result of which very flexible inputting and outputting of data as part of messages, in particular FlexRay messages, into or out of the first arrangement 105 achievable with guaranteed data integrity at optimal speed.
• this communication module 100 is shown in a preferred embodiment again in more detail.
• the respective connections 106 to 109 are also shown in more detail.
• the second arrangement 104 contains an input buffer or input buffer 201 (input buffer IBF), an output buffer or output buffer 202 (Output Buffer OBF) and an interface module consisting of two parts 203 and 204, wherein one sub-module 203 is subscriber-independent and the second sub-module 204 is subscriber-specific.
• the subscriber-specific sub-module 204 (Customer CPU Interface CIF) connects a subscriber-specific host CPU 102, that is to say a customer-specific subscriber, to the FlexRay communications module.
• a bidirectional data line 216, an address line 217 and a control input 218 are provided. Also provided with 219 is an interrupt or interrupt output.
• the subscriber-specific sub-module 204 is connected in conjunction with a subscriber-independent sub-module 203 (Generic CPU Interrupt Module). face, GIF), ie the FlexRay communication module or the FlexRay IP module has a generic, that is to say general, CPU interface 203, to which a large number of different customers are connected via corresponding subscriber-specific submodules 204, that is, Customer CPU Interfaces CIF - connect specific host CPUs 102.
• GIF Global System for Microwave Interrupt Module
• the input buffer or input buffer 201 and the output buffer or output buffer 202 may be formed in a common memory device or in separate memory devices.
• the input buffer memory 201 serves for the buffering of messages for transmission to a message memory 300.
• the input buffer module 201 is preferably designed such that it contains two complete messages each comprising a header segment or header segment, in particular with configuration data and a data segment or payload Can save segment.
• the input buffer 201 is formed in two parts (partial buffer memory and shadow memory), whereby the transmission between subscriber CPU 102 and message memory 300 can be accelerated by alternately writing the two parts of the input buffer memory or by changing access.
• the output buffer 202 (output buffer OBF) is used for buffering messages for transmission from the message memory 300 to the subscriber CPU 102.
• the output buffer 202 is designed so that two complete messages consisting of header segment, in particular with configuration data and data segment, ie payload segment, can be stored.
• the output buffer 202 is divided into two parts, a partial buffer memory and a shadow memory, which also here by alternately reading the two parts of the transmission or by Access change speeds up the transmission between host CPU 102 and message memory 300.
• This second assembly 104 consisting of the blocks 201 to 204 is connected to the first assembly 105 as shown.
• the arrangement 105 consists of a message handler 200 (message handler MHD) and a message memory 300 (message RAM).
• the message manager 200 controls the data transfer between the input buffer 201 and the output buffer 202 and the message memory 300. Likewise, it controls the data transfer in the other direction via the third device 103.
• the message memory 300 is preferably single-ported RAM executed. This RAM memory stores the messages or embassy objects, ie the actual data, together with configuration and status data. The exact structure of the message memory 300 is shown in more detail in FIG.
• the third arrangement 103 consists of the blocks 205 to 208. According to the two channels of the FlexRay Physical Layer, this arrangement 103 is divided into two data paths with two data directions each. This is illustrated by the links 213 and 214, which show the two data directions for channel A with RxA and TxA for receive (RxA) and transmit (TxA) and for channel B with RxB and TxB. Connection 215 indicates an optional bidirectional control input. The connection of the third arrangement 103 takes place via a first buffer memory 205 for channel B and a second buffer memory 206 for channel A. These two buffer memories (Transient Buffer RAMs:
• RAM A and RAM B serve as temporary storage for the data transfer from or to the first arrangement 105.
• these two buffer memories 205 and 206 are connected to an interface module 207 and 208, respectively, containing the FlexRay protocol controller or bus protocol - Controller consisting of a transmit / receive shift register and the FlexRay protocol finite state machine, included.
• the two buffer memories 205 and 206 thus serve as temporary storage for the data transfer between the shift registers of the interface modules or FlexRay protocol controllers 207 and 208 and the message memory 300.
• the data fields, ie the payload segment or data segment are advantageously provided by each buffer memory 205 or 206 stored in two FlexRay messages.
• GTU Global Time Unit
• SUC General System Control
• Block 211 shows the network and error management (Network and Error Management NEM) as described in FlexRay protocol specification v2.0.
• block 212 shows the interrupt control (INT) which manages the status and error interrupt flags and controls the interrupt outputs 219 to the subscriber CPU 102.
• Block 212 also includes an absolute and a relative timer for generating the time interrupts or timer interrupts.
• message objects or messages can be configured with up to 254 data bytes.
• the message memory 300 is in particular a message RAM memory (Message RAM), which z. B. can store up to a maximum of 128 message objects. All functions that affect the treatment or management of the messages themselves are implemented by the message handler or message handler 200. These are, for example, the acceptance filtering, transfer of the messages between the two FlexRay protocol controller blocks 207 and 208 and the message memory 300, that is to say the message RAM, as well as the control of the transmission order and the provision of configuration data or status data.
• Message RAM message RAM memory
• An external CPU that is to say an external processor of the subscriber processor 102, can access the registers of the FlexRay communication module 100 directly via the subscriber interface 204 with the subscriber-specific part 204. It uses a variety of registers. These registers are used to control the FlexRay protocol controllers, ie the interface modules 207 and 208, the message handler (MHD) 200, the global time unit (GTU) 209, the general system controller (System Controller SUC) 210 to configure and control the network and error management unit (NEM) 211, the interrupt controller (INT) 212, and the access to the message RAM, that is, the message memory 300, and also to display the corresponding status. At least parts of these registers will be discussed in more detail in Figures 4 to 6 and 7 to 9.
• Such a described FlexRay communication module 100 enables the simple implementation of the FlexRay specification v2.0, whereby an ASIC or a microcontroller with corresponding FlexRay functionality can be generated easily.
• the FlexRay protocol specification in particular v2.0, can be fully supported and thus, for example, up to 128 messages or message objects can be configured.
• the message memory 300 is advantageously designed as FIFO (first in-first out), resulting in a configurable receive FIFO.
• Each message or message object in memory can be configured as a ReceivedBuffer, TransmitBuffer object, or as part of the configurable ReceiveField. Likewise, acceptance filtering on frame ID, channel ID and cycle counter in the FlexRay network is possible. Expediently, the network management is thus supported.
• maskable module interrupts are also provided.
• FIG. 3 describes in detail the division of the message memory 300.
• a message memory is required for the provision of messages to be sent (transmit buffer Tx) as well as the storage of messages received without errors (receive buffer Rx).
• a FlexRay protocol allows messages with a data range, ie a payload range from 0 to 254 bytes.
• the message memory 300 is part of the FlexRay communication module 100.
• the method described below and the corresponding message memory 300 describe the storage of messages to be sent as well as received messages, in particular using a random access memory (RAM). whereby it is possible by means of the mechanism described in a message memory of a predetermined size to produce a variable number of messages to save shadow.
• RAM random access memory
• the number of storable messages is dependent on the size of the data areas of the individual messages, whereby on the one hand the size of the required memory can be minimized without restricting the size of the data areas of the messages and on the other hand an optimal utilization of the memory takes place.
• this variable division of a particular RAM-based message memory 300 for a FlexRay Communication Controller will be described in more detail.
• a message memory with a fixed word length of n bits, for example 8, 16, 32, etc., as well as a predetermined memory depth of m words is given by way of example (m, n as natural numbers).
• the message memory 300 is divided into two segments, a header segment or header segment HS and a data segment DS (Payload Section, Payload Segment).
• a header area HB and a data area DB are thus created per message.
• header areas or header areas HB0, HB1 to HBk and data areas DB0, DB1 to DBk are thus created.
• first and second data the first data corresponding to configuration data and / or status data relating to the FlexRay message and stored in a header area HB (HBO, HB1, ..., HBk) in each case.
• the second data which correspond to the actual user data that is to be transmitted, are correspondingly stored in data areas DB (DBO, DBl,..., DBk).
• the second data size per message may be different .
• the division between the header segment HS and the data segment DS is now variable in the message memory 300, ie there is no predetermined boundary between the domains.
• the division between head segment HS and data segment DS is dependent on the number k of messages and the second data. extent of the actual user data, a message or all k messages together.
• the configuration data KDO, KD1 to KDk of the respective message is now assigned directly to a pointer element or data pointer DPO, DPI to DPk.
• each header area HBO, HB 1 to HBk is assigned a fixed number of memory words, here two, so that always a configuration data KD (KDO, KD 1,..., KDk) and a pointer element DP (DPO , DPI, ..., DPk) are stored together in a header area HB.
• the data segment DS includes for storing the actual message data DO, Dl to Dk. This data segment (or data section) DS depends in its scope of data on the respective data volume of the stored message data, here in six words DBO, DBl one word and DBk two words.
• the respective pointer elements DPO, DPI to DPk thus always point to the beginning, ie to the start address of the respective data area DBO, DB1 to DBk, in which the data DO, D1 to Dk of the respective messages 0, 1 to k are stored.
• the division of the message memory 300 between header segment HS and data segment DS is variable and depends on the number k of messages themselves and the respective data volume of a message and thus the entire second data volume. If fewer messages are configured, the header segment HS becomes smaller and the freed area in the message memory 300 can be used as an addition to the data segment DS for the storage of data. This variability ensures optimal memory utilization, which also allows the use of smaller memory.
• the free data segment FDS is therefore minimal and can even become 0.
• the first and second data ie the configuration data KD (KDO, KDl, ..., KDk) and the actual data D (DO, Dl, ..., Dk) in a predetermined Store sequence so that the order of the header areas HBO to HBk in the header segment HS and the order of the data areas DBO to DBk in the data segment DS is identical. Then could even be dispensed with a pointer element under certain circumstances.
• the message memory is assigned an error detection generator, in particular a parity bit generator element and a misrecognition tester, in particular a parity bit test element, in order to ensure the correctness of the stored data in HS and DS by per memory word or per area (HB and / or DB) a checksum just in particular as a parity bit can be stored.
• error detection generator in particular a parity bit generator element
• a misrecognition tester in particular a parity bit test element
• the user can decide in programming whether to use a larger number of messages with a small data field or whether he wants to use a smaller number of messages with a large data field.
• the available memory space is optimally utilized.
• the user has the option to share a data storage area for different messages.
• the size of the message memory 300 can be adapted to the needs of the memory by adapting the memory depth (number m of words) of the memory used. be adapted to the application without changing the other functions of the Communication Controller.
• the host CPU access that is to say writing and reading of configuration data or status data and of the actual data via the buffer memory arrangement 201 and 202, will now be described in greater detail with reference to FIGS. 4 to 6 and 7 to 9.
• the aim is to produce a decoupling with regard to the data transmission in such a way that the data integrity can be ensured and at the same time a high transmission speed is ensured.
• the control of these processes via the message manager 200, which will be described later in more detail in Figures 10, 11 and 12.
• FIGS. 4, 5 and 6 the write accesses to the message memory 300 by the host CPU of the subscriber CPU 102 via the input buffer 201 are first explained in greater detail.
• FIG. 4 once again shows the communications module 100, with only the parts of the communications module 100 relevant here being shown for reasons of clarity.
• the message manager 200 responsible for controlling the processes and two control registers 403 and 404 which, as shown, can be accommodated outside the message manager 200 in the communication module 100, but can also be contained in the message administrator 200 itself.
• 403 represents the Input Buffer Command Request Register and 404 the Input Buffer Command Mask Register.
• Input buffer 201 (input buffer). This input buffer 201 is now divided or doubled, as a partial buffer memory 400 and a shadow memory 401 associated with the sub-buffer memory. Thus, as described below, a continuous access of the host CPU 102 to the messages or message objects or data of the message buffer is possible. Memory 300 occur and thus data integrity and accelerated transmission are ensured.
• the accesses are controlled via the input request register 403 and via the input mask register 404.
• the numbers from 0 to 31 in FIG. 5 show the respective bit positions in 403 by way of example here for a width of 32 bits. The same applies to the register 404 and the bit positions 0 to 31 in the mask register 404 from FIG. 6.
• bit positions 0 to 5, 15, 16 to 21 and 31 of the register 403 have a special function with regard to the sequence control.
• an identifier IBRH Input Buffer Request Host
• an identifier IBRS Input Buffer Request Shadow
• register 15 of 403 IBSYH and in register 31 of 403 IBSYS are registered as access identifiers.
• the host CPU 102 writes the data of the message to be transferred in the
• the host CPU 102 may write only the configuration and header data KD of a message for the header segment HS of the message memory 300 or only the actual data D to be transmitted of a message for the data segment DS of the message memory 300 or both.
• Which part of a message, ie configuration data and / or the actual data to be transmitted is determined by the special data identifiers LHSH and LDSH in the input tag register 404.
• LHSH Load Header Section Host
• LDSH Load Data Section Host
• LHSH and LDSH are now related to the shadow memory 401.
• LHSS Load Header Section Shadow
• LDSS Load Data Section Shadow
• start bit or the start identifier STXRH is set in bit position 2 of the input mask register 404, after the transfer of the respective configuration data and / or actual data to be transmitted to the message memory 300, a send request (transmission Request) for the corresponding message object. Ie. The automatic transmission of a transmitting message object is controlled, in particular started, by this start identifier STXRH.
• the counterpart corresponding to this for the shadow memory 401 is the start identifier STXRS (Set Transmission X Request Shadow), which is contained in bit position 18 of the input tag register 404 by way of example and, in the simplest case, is also designed as one bit.
• STXRS Set Transmission X Request Shadow
• the function of STXRS is analogous to the function of STXRH, only relative to the shadow memory 401.
• the TeN buffer memory becomes 400 of the input buffer memory 201 and the associated shadow memory 401 swapped or the respective access from the host CPU 102 and message memory 300 to the two sub-memories 400 and 401 reversed, as indicated by the semicircular arrows.
• the data transfer ie the data transfer to the message memory 300 is started.
• the data transmission to the message memory 300 itself takes place from the
• Shadow memory 401 At the same time the register areas IBRH and IBRS are exchanged. Likewise exchanged LHSH and LDSH against LHSS and LDSS. In the same way STXRH is exchanged with STXRS. IBRS thus shows the identifier of the message, that is to say the number of the message object for the one transmission, ie a transfer from the shadow memory 401 is in progress or which message object, ie which area in the message memory 300 as the last data (KD and / or D ) received from the shadow memory 401.
• IBRH that is, bits 0 to 5
• the host CPU 102 may write the next message to be transferred into the input buffer memory 201 or the sub buffer 400, respectively.
• IBSYH Input Buffer Busy Host
• the requested transfer (request by STXRH see above) is started and bit IBSYH is reset.
• the IBSYS bit remains set all the time to indicate that data is being transferred to the message memory 300. All used bits of all embodiments can also be designed as identifiers with more than one bit. The one-bit solution is advantageous for storage and processing economic reasons.
• the mechanism thus described allows the host CPU 102 to continuously transfer data to the message memory 300 message objects consisting of the header area HB and the data area DB, provided the access speed of the host CPU 102 to the input buffer memory 201 is less than or equal to the internal data transfer rate of the host computer FlexRay IP module, ie the communication block 100.
• FIGS. 7, 8 and 9 the read accesses to the message memory 300 by the host CPU or user CPU 102 via the output buffer 202 are explained in greater detail.
• Figure 7 once again shows the communication module 100, where for reasons of clarity, only the relevant parts of the communication module 100 are shown here.
• the message manager 200 responsible for controlling the processes
• two control registers 703 and 704 which, as shown, can be accommodated outside the message administrator 200 in the communication module 100, but also in the message administrator 200 themselves can be included.
• 703 represents the Output Buffer Command Request Register and 704 the Output Buffer Command Mask Register. Read accesses of the host CPU 102 to the message memory 300 thus occur via the intermediate output buffer 202 (output buffer).
• This output buffer memory 202 is now likewise divided or doubled, specifically as a partial buffer memory 701 and a shadow memory 700 belonging to the partial buffer memory.
• a continuous access by the host CPU 102 to the shadow objects or messages respectively Data of the message memory 300 done and thus data integrity and accelerated transmission are now guaranteed in the opposite direction from the message memory 300 to the host 102.
• the access is controlled via the output request register
• bit positions 0 to 5, 8 and 9, 15 and 16 to 21 of register 703 have a special function with respect to the flow control of the read access.
• an identifier OBRS Output Buffer Request Shadow
• an identifier OBRH Output Buffer Request Host
• an identifier OBSYS Output Buffer Busy Shadow
• Excellent are also the digits 0 and 1 of the output masking register 704, wherein in the bit positions 0 and 1 with RDSS (Read Data Section Shadow) and RHSS (Read Header Section Shadow) further identifiers are entered as data identifiers. Further data identifiers can be found, for example, in bit positions 16 and 17 with RDSH (Read Data Section Host) and RHSH (Read Header Section). on host). These data identifications are here also exemplary in the simplest form, namely each formed as a bit. In bit position 9 of the register 703, a start identifier REQ is entered. Furthermore, a switchover identifier VIEW is provided, which is entered as an example in bit position 8 of register 703.
• the host CPU 102 requests the data of a message object from the message memory 300 by writing the ID of the desired message, that is, in particular, the number of the desired message object to OBRS in the bit positions 0 to 5 of the register 703.
• the host CPU 102 can read only the status or configuration data KD of a message from a header area or only the data D actually to be transmitted from the data area or both , Which part of the data is to be transferred from the header area and / or data area is thus set comparable to the opposite direction by RHSS and RDSS. That is, RHSS indicates whether the header data should be read, and RDSS indicates whether the actual data should be read.
• a start identifier serves to start the transmission from the message memory 300 to the shadow memory 700. That is, when a bit is used as the identifier as in the simplest case, the transmission from the message memory 300 to the shadow memory 700 is started by setting bit REQ in bit position 9 in the output request register 703. The current transmission is again indicated by an access identifier, here again in the simplest case by a bit OBSYS in the register 703. In order to avoid collisions, it is advantageous if the REQ bit can only be set if OBSYS is not set, ie no ongoing transmission is currently taking place. Here, the message transfer between the message memory 300 and the shadow memory 700 then takes place. The actual sequence could now be controlled on the one hand comparable to the opposite direction as described under FIGS.
• bit OBSYS is reset and by setting the bit VIEW in the output request register 703, the partial buffer memory 701 and the associated shadow memory 700 exchanged or the accesses are exchanged thereon and the host CPU 102 can now read the embassy memory 300 requested message object, ie the corresponding message from the sub-buffer 701.
• the register cells OBRS and OBRH are also exchanged here, comparable to the countertransference direction in FIGS.
• RHSS and RDSS are exchanged for RHSH and RDSH.
• the bit VIEW can only be set if OBSYS is not set, ie no ongoing transmission takes place.
• This output buffer 202 like the input buffer 201, is designed in two parts to provide continuous access by the host CPU 102 to the message objects residing in the message memory 300 are guaranteed. Again, the benefits of high data integrity and accelerated transmission are achieved.
• the use of the described input and output buffers 201, 202 ensures that a host CPU 102 can access the message memory 300 uninterruptedly despite the module-internal latencies.
• the data transmission is performed by the message manager 200 (message handler MHD).
• message manager 200 messages handler MHD
• the message manager 200 can be represented in its functionality by a plurality of state machines or state machines, ie finite state machines, so-called finite state machines (FSM). In this case, at least three state machines and in a special embodiment four finite state machines are provided.
• a first finite-state machine is the IOBF-FSM and designated 501 (input / output buffer state machine). This IOBF-FSM could also be divided into two finite-state machines per transmission direction with regard to the input buffer memory 201 or the output buffer memory 202.
• IBF-FSM Input Buffer FSM
• OBF-FSM Output Buffer FSM
• IBF FSM Input Buffer FSM
• OBF-FSM Output Buffer FSM
• a maximum of five state machines IBF FSM, OBF-FSM, TBF1-FSM, TBF2-FSM, AFSM
• IBF FSM Input Buffer FSM
• OBF-FSM Input Buffer FSM
• TBF1-FSM TBF1-FSM
• TBF2-FSM AFSM
• a second finite-state machine is here divided in the course of the preferred embodiment into two blocks 502 and 503 and serves the two channels A and B with respect to the memory 205 and 206, as described for Fig. 2.
• a finite state machine can be provided to serve both channels A and B, or, as in the preferred form, a finite state machine TBF1-FSM is designated 502 (transient buffer 1 (206, RAM A) state Machine) for channel A and for channel B a TBF2-FSM 503 (Transient Buffer 2 (205, RAM B) State Machine).
• an arbiter finite state machine is indicated at 500.
• the data (KD and / or D) are stored in one by a clocking means, e.g. a VCO (Voltage Controlled Oscillator), a VCO (Voltage Controlled Oscillator), a VCO (Voltage Controlled Oscillator), a VCO (Voltage Controlled Oscillator), a VCO (Voltage Controlled Oscillator), a VCO (Voltage Controlled Oscillator), a VCO (Voltage Controlled Oscillator), a VCO (Voltage Controlled Oscillator), a VCO (Voltage Controlled Oscillator), a VCO (Voltage Controlled Oscillator), a VCO (Voltage Controlled Oscillator), a VCO (Voltage Controlled Oscillator), a VCO (Voltage Controlled Oscillator), a VCO (Voltage Controlled Oscillator), a
• the clock T can be generated in the block or be specified from the outside, eg as a bus clock.
• This arithmetic finite state machine AFSM 500 alternately gives one of the three finite state machines 501-503, in particular access to the message for one clock period T in each case. Shaft memory 300. That is, the time available is divided according to the access requirements of each state machine 501, 502, 503 on these requesting state machine. If an access request is made by only one finite-state machine, it will receive 100% of the access time, ie all the clocks T. If an access request is received from two state machines, each finite-state machine receives 50% of the access time. Finally, if an access request from three state machines occurs, each of the finite state machines will receive 1/3 of the access time. This optimally utilizes the available bandwidth.
• the first finite-state machine 501 ie IOBF-FSM, performs the following actions as required:
• the state machine 502 for channel A ie TBF1-FSM, carries out the following actions: Data transfer from the selected message object in the message memory 300 to the buffer memory 206 of channel A.
• TBF2-FSM is the finite state machine for channel B in block 503.
• This performs the data transfer from the selected message object in message memory 300 to buffer memory 205 of channel B and the data transfer from buffer 205 to the selected bot
• the search function is analogous to TBFl-FSM for a matching message object in the message memory 300, wherein upon receipt the message object (Receive Buffer) is searched for storing a received message on channel B in the context of acceptance filtering and when sending the Next message to be sent on channel B or message object (transmit buffer).
• FIG. 11 shows again the processes and the transmission paths.
• the three state machines 501-503 control the respective data transfers between the individual parts.
• the host CPU is shown again at 102, the input buffer memory at 201 and the output buffer memory at 202. With 300 the message memory is shown and the two buffers for channel A and channel B with 206 and 205.
• the interface elements 207 and 208 are also shown.
• the first state machine IOBF-FSM designated 501, controls the data transfer ZlA and ZlB, ie from the input buffer 201 to the message memory 300 and from the message memory 300 to the output buffer 202.
• the data is transmitted via data buses having a word width of, for example, 32 bits other bit number is possible. The same applies to the transmission Z2 between the message memory and the buffer memory 206.
• This data transmission is controlled by TBFI-FSM, ie the state machine 502 for channel A.
• Transmission Z3 between message memory 300 and buffer memory 205 is controlled by state machine TBF2-FSM, ie 503.
• the data transfer takes place over the upper data buses with an exemplary word width of 32 bits, whereby here too every other bit number is possible.
• the transmission time is divided in relation to the clock periods T by the arbiter, ie the AFSM 500.
• the arbiter ie the AFSM 500.
• FIG. 11 therefore, the data paths between those memory components controlled by the message handler 200 are shown.
• data should advantageously be exchanged simultaneously at the same time only on one of the illustrated paths Z1A and Z1B as well as Z2 and Z3.
• FIG. 12 shows an example of how the available system clocks T are divided by the arbiter, that is to say the AFSM 500, into the three requesting state machines.
• access requests are made by state machine 501 and state machine 502, that is, half of the time is shared between the two requesting state machines.
• phase 2 (II) the access is done only by the state machine 501, so that every three clock periods, ie 100% of the access time from T5 to T7 on IOBF-FSM accounts.
• phase 3 (III) access requests are made by all three state machines 501 to 503, so that one third of the total access time takes place.
• the arithmetic AFSM 500 then distributes the access time, for example, such that in the clock periods T8 and TIl the finite state machine 501, in the clock periods T9 and T12 the finite state machine 502 and in the clock periods T10 and T13 the finite state - Machine 503 gets access.
• phase 4 (IV) access is provided by two state machines 502 and 503 on the two channels A and B of the communication module 100, so that an access distribution of the clock periods T14 and T16 to finite state machine 502 and into T15 and T17 at finite state machine 503.
• the arithmetic state machine AFSM 500 thus ensures that if more than one of the three state machines 501-503 makes a request for access to the message memory 300, the access is intermittently and alternately split to the requesting state machines 501-503. This procedure ensures the integrity of the message objects stored in message memory 300, ie data integrity. If, for example, the host CPU 102 wants to read out a message object via the output buffer 202 while a received message is being written to this message object, then either the old state or the new state will be read out, without the accesses in the message being started, depending on which request was first started Message object in message memory 300 itself collide.
• the described method allows the host CPU 102 to read or write any message object in the message memory 300 during operation without the selected message object for the duration of access of the host CPU 102 from participating in the data exchange on both channels of the FlexRay bus 101 would be blocked (Buffer Locking).
• Buffer Locking the integrity of the data stored in the message memory 300 is ensured by the intermittent interleaving of the accesses, and the transmission speed is increased, even by utilizing the full bandwidth.
• the FlexRay communication module 100 optimally supports the communication in the FlexRay network, and in order to be able to connect the FlexRay communication module 100 to the subscriber in a resource-saving and resource-saving manner that is particularly resource-saving for the subscriber 102 or the host CPU
• a particularly configured user interface 204 is proposed, which is shown in detail in FIG.
• the interface 204 has an arrangement 800 for temporary storage of the messages to be transmitted between the FlexRay communication module 100 and the FlexRay subscriber 102.
• the arrangement 800 comprises at least one message memory 802 having a first connection 804 to the FlexRay communication module 100 and a second connection 806 to the subscriber 102.
• the message memory 802 of the memory device 800 is preferably implemented as a dual-ported RAM. It includes a writing area (W) in which the FlexRay
• the message memory 802 is at least large enough that it has enough memory space for storing all the messages of a bus cycle. Preferably, the memory 802 has enough storage space for 128 buffers (maximum size of a data frame (so-called frames)).
• the subscriber interface 204 has a second arrangement 808, which an entity 810 (Arbiter ARB) for controlling data integrity regulates the access order to the message memory 802 of the subscriber interface 204 and comprises at least one state machine 812 (state machine SM).
• an entity 810 Asset ARB
• state machine SM state machine 812
• the state machine 812 the content of the message memory 300 of the FlexRay communication module 100 is invisibly transferred to the DP RAM message memory 802 of the interface 204 for the subscriber 102 or the host CPU.
• the host CPU can access the mirrored data in the DPRAM 802 at maximum speed.
• connection 824 which is designed, for example, as a bus system, data, addresses and control data are interposed between the communication module
• connection 826 which is designed, for example, as a bus system
• data, addresses and control data are exchanged between the bus arbiter 810 of the subscriber interface 204 and the subscriber 102 or the host CPU.
• connection 806 which is designed, for example, as a bus system Data
• addresses and control data are exchanged between the memory arrangement 800 of the subscriber interface 204 and the subscriber 102 or the host CPU.
• a connection 834 which may be embodied as a bus system.
• An interrupt can be transmitted to the subscriber 102 or the host CPU via a connection 828 as soon as a buffer has been received from the message memory 300 of the communication module 100 in the memory 802 (DPBuffer_received_lnt signal). Via connection 830, the state machine 812 of the interface 204 is informed of the beginning of a new bus cycle (new_cycle signal).
• a connection 820 notifies the state machine 812 of the interface 204 that a new buffer has been received in the message memory 300 of the communication device 100 (Buffer_received signal), and the state machine 812 causes this new buffer to be transferred to the message memory 802 of the interface 204 , Finally, the state machine 812 receives via a connection 832 a clock signal from the communication module 100 for controlling and coordinating its activity with the remaining processes in the overall system 100, 101, 102, 204.
• Registers are assigned to the message memory 802 of the user interface 204, preferably a write register (DP / status register W) 814 and the read area R of the message memory 802 having a read register (DP / status register R) 816 assigned to the write area W of the message memory 802.
• the status of the message memory 802 of the subscriber interface 204 is transmitted via the registers 814, 816 from the state machine 812 to the FlexRay interface.
• the size of the status registers 814, 816 preferably depends on the size of the message memory 802 or the number of messages that can be buffered therein. With a size of memory 802 of 128 buffers, registers 814, 816 are preferably 128 bits in size, with each bit of register 814, 816 is associated with a buffer of memory 802, respectively. Reading the status register resets the read bits.
• the identifier, for example the number, of the last buffer successfully transmitted by the state machine 812 (each separated according to read and write memory) is transferred from the in-state machine 812 to a further register 818, a so-called read-write position register of the user interface 204 , filed.
• the host CPU 102 can also receive data packets at a suitable point during a bus cycle and release them for transmission. That is, with the aid of the state machine 812, an optimization or limited preprocessing of the messages to be stored in the buffer 802 can be undertaken within a bus cycle in order to further accelerate the access to the stored messages.
• the pre-processing of the messages is preferably limited to formalities and the exterior of the messages, for example the position in which the messages are stored in the message memory 802. An analysis of the content of the messages and a corresponding content-dependent preprocessing preferably does not take place.
• the host CPU has random access to the contents of the message memory 300 of the FlexRay communication module 100 via the subscriber interface 204 according to the invention.
• the entire procedure of storing messages in message memory 802 and invoking messages from message memory 802 does not require any delays in data transmission.
• the transmission speed or transmission rate is limited only by the performance of the DPRAM interface of the message memory 802. A timely manipulation of buffers is possible.
• a bit in the write register (DP / status register W) 814 is set by the host CPU 102.
• identifiers corresponding to the host CPU 102 are written to the write register (D P / Status / W register) 814, for example, by setting appropriate bits for the buffers to be transmitted.
• the state machine 812 transfers all buffers marked in the write registers 814 (e.g., by setting a bit) into the message memory 300 of the communication module 100.
• Data transfer from message memory 300 (e.g., MRAM) of communication module 100 to message memory 802 (e.g., DP-RAM) of user interface 204 is initiated by communication module 100 through a buffer / received signal.
• the state machine 812 After the state machine 812 has then requested the buffer to be transmitted from the communication device 100, it transmits it from the message memory 300 (e.g., MRAM) to the message memory 802 (e.g., DP-RAM).
• state machine 812 sets the corresponding bit in read register 816 (D P / status register R). In addition, the state machine 812 may still trigger an interrupt to the host CPU 102 at the end of the transfer.
• Subscriber interface 204 is written in the same way as reading. Unlike reading, the buffer to be sent is determined by evaluating the read register 816 (DP / status / R register). The bit number in register 816 corresponds to the priority in the transmission. State machine 812 scans the bits of register 816 from bottom to top. The corresponding buffer of the first bit set to "1" is transmitted from the message memory 802 of the subscriber interface 204 into the message memory 300 of the communication module 100. After transmission, the associated bit in read register 816 and the buffer number are written to read / write position register (DP / R-pos register) 818. This process is carried out continuously. All buffers marked "1" are transmitted to the message memory 300 of the communication module 100 according to their priority by the message memory 802.
• Communication module 100 and the subscriber interface 204 two separate components.
• the state machine 812 for the data transfer between the message memory 300 of the communication module 100 and the message memory 802 of the subscriber interface 204 transfers the buffers of the message memory 300 of the communication module 100 into the message memory 802 of the subscriber interface 204 without the intervention of the host CPU 102.
• the DPRAM 802 is connected directly to the state machine 812 on the one hand and to the host CPU 102 on the other hand. Both sides can access the DPRAM 802 without delay.
• the status of the DPRAM 802 is communicated from the state machine 812 to the host CPU 102 via the D P / Status / R register 816.
• the buffers to be transmitted from the state machine 812 to the communication device 100 are written by the host CPU 102 into the D P / Status / W register 814. After host CPU write access, register 814 contains the binary or its previous contents and the written data.
• the state machine 812 transfers all in
• the Busarbiter 810 allows synchronous access of both the state Machine 812 and the host CPU 102 to the registers 814, 816 of the interface 204th
• the state machine 812 directly accesses (via the arbiter 810) registers of the communication module 100 assigned to the message memory 300.
• the state machine 812 After the communication module 100 indicates a buffer newly received by the communication connection 101 via a buffer / received signal 820, the state machine 812 actively requests the buffer number by accessing the registers of the communication module 100. Subsequently, the state machine 812 determines the buffer attributes (buffer address in the buffer memory 300 of the communication module 100, length of the buffer, etc.) by reading out the corresponding register of the communication module 100. After the necessary transfer data is present in the state machine 812, the Communication block for visual switching (VI EW command) of the buffer in the transfer window of the communication block 100 is requested. In the last step, the state machine 812 automatically transfers the buffer content of the memory 300 to the message memory 802.
• the buffer attributes buffer address in the buffer memory 300 of the communication module 100, length of the buffer, etc.
• the corresponding R bit is set in the D P status register 816 and the buffer number is entered into the DP / R position. Register 818 written.
• the setting of the DP status register R bits may trigger an interrupt to the host CPU 102 in response to the interrupt mask (128-bit DP Status L register 822) which is sent to the host CPU via the interrupt connection 828.
• CPU 102 is transmitted. This process repeats for each transmitted buffer.
• the inventive method works without interrupt, so that the I nterrup register 822 and the interrupt connection 828 can be omitted.
• the order in which the buffers are stored in the message memory 802, regardless of the order in which buffers are stored in the message memory 300 of the communication module 100, is determined by the arbiter 810.
• the order in which the buffers are stored in the message memory 300 of the communication module 100, irrespective of the order, in the buffer are stored in the message memory 802 are determined by the state machine 812, and could be configured by the host CPU 102, for example.
• the transfer of the buffer written by the host CPU 102 to the DPRAM 802 is the same as the reading. Unlike reading, the buffer to be sent is determined by evaluating DP / status / W register 814.
• the bit number in register 814 corresponds to the priority of the transmission.
• the state machine 812 scans the bits of the register 814 from bottom to top.
• the corresponding buffer of the first bit set to "1" is transmitted by the DPRAM 802 into the message memory 300 of the communication module 100.
• the associated bit in the D P / Status / W register 814 and the buffer number are written to the D P / R-pos register 818. This process is carried out continuously. All buffers marked with "1" are transmitted by the DPRAM 802 to the message memory 300 of the FlexRay communication module 100 according to their priority.
• the state machine is configured and started and stopped via the MDTSN-config register
• FIG. 14 shows a second exemplary embodiment of the subscriber interface 204 according to the invention, which differs from the embodiment of FIG. 13 in particular in that the interface 204 is integrated in the FlexRay communications module 100.
• both embodiments use the dual-port-based approach of the invention for buffering between the FlexRay communication module 100 and FlexRay interface.
• Participant 102 to be transmitted data.
• the data transmission instead of the own state machine 808 and the own arbiter 810 of the interface 204 (see Figure 13) by one or more of the state machines 500-503 of the FlexRay communication module and / or the Sab administrators 200 are coordinated and controlled.
• the appropriate interface 204 does not have to be completely self-sufficient, but can also use parts of the communication module 100.
• FIG. 15 shows a sequence diagram for a data transfer between the message memory 300 of the FlexRay communication module 100 and the message memory 802 (for example, DPRAM) of the subscriber interface 204.
• the control of the message memory 300 of the FlexRay communication module 100 by one or more of the state machines 500-503 is designated by 900.
• the control of the message memory 802 of the subscriber interface 204 by one or more of the state machines 500-503 and / or the state machine 808 is designated by 902.
• the control of the status of the message memory 802 of the subscriber interface 204 by one or more of the state machines 500-503 and / or the state machine 808 is designated by 904.
• the controller 900 sends a signal 914 to the controller 902, after which a new buffer [y] has been received in the message memory 300, and the steps performed for the buffer [x] are executed for the buffer [y]. This is repeated until all buffers of a data cycle have been transmitted.
• FIG. 16 is a sequence diagram for a data transfer between the message memory 802 (eg DPRAM) of the subscriber interface 204 and the message memory 300 of the FlexRay communication module 100.
• the write register W 814 of the message memory 802 of the subscriber interface 204 is designated 920.
• the control of the message memory 802 of the subscriber interface 204 by one or more of the state machines 500-503 and / or the state machine 808 is designated by 922.
• the highest priority DPRAM status W bit [z] is determined in which the corresponding DPRAM status W register [z] bit in register 814 is set, ie, not equal to zero.
• the buffer [z] of the message memory 300 of the FlexRay communication module 100 is updated with the content of the buffer [z] of the message memory 802 of the subscriber interface 204.
• the register DPRAM status W-pos 818 is updated with y.
• the position DPRAM status W [z] in register 814 is reset, ie set to zero.

Landscapes

• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Communication Control (AREA)
• Small-Scale Networks (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=37510788

Family Applications (1)

Country Status (6)

Families Citing this family (10)

Family Cites Families (22)

• 2005
  • 2005-10-06 DE DE102005048581.2A patent/DE102005048581B4/de active Active
• 2006
  • 2006-10-04 CN CN200680037101.XA patent/CN101283548B/zh active Active
  • 2006-10-04 WO PCT/EP2006/067025 patent/WO2007039620A1/de active Application Filing
  • 2006-10-04 US US12/083,263 patent/US20100281131A1/en not_active Abandoned
  • 2006-10-04 JP JP2008534009A patent/JP4903801B2/ja active Active
  • 2006-10-04 EP EP06806960A patent/EP1941668A1/de not_active Ceased

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events