EP1918902A1 - Plasmaanzeigevorrichtung - Google Patents

Plasmaanzeigevorrichtung Download PDF

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Publication number
EP1918902A1
EP1918902A1 EP06255670A EP06255670A EP1918902A1 EP 1918902 A1 EP1918902 A1 EP 1918902A1 EP 06255670 A EP06255670 A EP 06255670A EP 06255670 A EP06255670 A EP 06255670A EP 1918902 A1 EP1918902 A1 EP 1918902A1
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EP
European Patent Office
Prior art keywords
sub
data
field group
field
fields
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06255670A
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English (en)
French (fr)
Inventor
Sang Jin Yoon
Il Hoon Choi
Seongho Kang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LG Electronics Inc
Original Assignee
LG Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LG Electronics Inc filed Critical LG Electronics Inc
Priority to EP06255670A priority Critical patent/EP1918902A1/de
Publication of EP1918902A1 publication Critical patent/EP1918902A1/de
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G09G3/204—Display of intermediate tones by time modulation using two or more time intervals using sub-frames the sub-frames being organized in consecutive sub-frame groups
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0266—Reduction of sub-frame artefacts
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/2803—Display of gradations

Definitions

  • the present invention relates to a display apparatus.
  • a plasma display apparatus is one of several contemporary display technologies, and includes a plasma display panel (hereinafter, PDP) where an image is shown, and a driver for driving the PDP.
  • PDP plasma display panel
  • a PDP displays an image, when ultraviolet rays generated by electrical discharge in an inert gas mixture such as He+Xe, Ne+Xe, and He+Xe+Ne excites phosphors to emit visible light.
  • the plasma display apparatus is thin and relatively easy to manufacture in large screen sizes. Recent technological developments have contributed to improve the image quality.
  • FIG. 1 is a perspective view showing a conventional 3-electrode alternating current (AC) surface discharge PDP.
  • the conventional 3-electrode AC surface discharge PDP comprises a plurality of scan electrodes Y and a plurality of sustain electrodes Z which are formed on an upper substrate 10, and a plurality of address electrodes X formed on a lower substrate 18.
  • the discharge cells of a PDP are disposed at positions where the scan electrodes Y, the sustain electrodes Z and the address electrodes X are crossed with each other, and arranged in the form of a matrix.
  • Each of the scan electrodes Y and the sustain electrodes Z comprises a transparent electrode 12 and a metal bus electrode 11 which has a smaller linewidth than the transparent electrode 12 and formed at one edge of the transparent electrode 12.
  • the transparent electrode 12 is generally formed of an indium tin oxide (ITO) on the upper substrate 10.
  • the metal bus electrode 11 is generally formed of metal on the transparent electrode 12 to reduce voltage decrease caused by the highly resistant transparent electrode 12.
  • An upper dielectric layer 13 and a protective layer 14 are stacked on the upper substrate 10 where the scan electrodes Y and the sustain electrodes Z are formed. In the upper dielectric layer 13, wall charges generated during plasma discharge are accumulated.
  • the protective layer 14 protects the address electrodes X, the scan electrodes Y, the sustain electrodes Z, and the upper dielectric layer 13 from sputtering during plasma discharge, and increases a secondary electron emission efficiency.
  • the protective layer is generally formed of magnesium oxide (MgO).
  • the address electrodes X are formed in the lower substrate 18 in a direction crossing the scan electrodes Y1 to Yn and the sustain electrodes Z.
  • a lower dielectric layer 17 and barrier ribs 15 are formed in the lower substrate 18.
  • a phosphor layer 16 is formed on the surface of the lower dielectric layer 17 and the barrier ribs 15.
  • the barrier ribs 15 physically divide the discharge cells.
  • the phosphor layer 16 is excited by ultraviolet ray generated during plasma discharge and generates visible light of any one among red, green and blue.
  • Inert gas mixture for discharge such as He+Xe, Ne+Xe, and He+Xe+Ne, is injected into the discharge space of the discharge cells arranged between the upper and lower substrates 10 and 18 and the barrier ribs 15.
  • the 3-electrode AC surface discharge PDP is operated by dividing a frame into a plurality of sub-fields having a different light emission frequency to realize a gray level of image.
  • FIG. 2 describes an image representing method of a conventional plasma display apparatus.
  • a frame time (16.67ms) corresponding to a 1/60 second is divided into 8 sub-fields SF1 to SF8.
  • Each of the sub-fields SF1 to SF8 is divided into a reset period for initializing the discharge cells, an address period for selecting a discharge cell, and a sustain period for realizing a gray level according to the discharge frequency number.
  • flickering occurs when the decay time of a phosphor is shorter than the frame frequency of video signals. For example, when the frame frequency is assumed to be 60Hz, video of one frame is displayed every 16.67 m/sec. Since the response time of the phosphor is faster than that, the screen flickers and image quality is deteriorated.
  • the frame frequency is 50, which is relatively short, in a phase alternating line (PAL) method, and the flickering becomes more serious.
  • PAL phase alternating line
  • the problem of flickering is reduced by arranging a plurality of groups of sub-fields in one frame.
  • FIG. 3 is a block view illustrating a structure of a conventional plasma display apparatus for processing video data.
  • the conventional plasma display apparatus comprises an inverse gamma corrector 41, a half-tone processor 42, a sub-field mapper 43, and a plasma display panel (PDP) 44.
  • PDP plasma display panel
  • the inverse gamma corrector 41 performs inverse gamma correction onto digital video data, or read, green and blue (RGB) data, to linearize brightness change for the gray level value of a video signal.
  • the half-tone processor 42 diffuses the quantization error into adjacent cells to delicately control the brightness value. For this, the half-tone processor 42 divides data into an integer part and a decimal part, and multiplies the decimal part by a predetermined error diffusion coefficient, for example, a Floid-Steinberg coefficient.
  • a predetermined error diffusion coefficient for example, a Floid-Steinberg coefficient.
  • the sub-field mapper 43 maps the digital video data inputted from the half-tone processor 42 to a sub-field pattern predetermined for each bit, and supplies the mapping data to the PDP through a data sorter (not shown).
  • a plasma display apparatus of the PAL method which divides one frame into a plurality of sub-field groups to suppress the flickering may have a contour step noise within a frame time when image is realized.
  • an object of the present invention is to solve at least the problems and disadvantages of the background art.
  • PDP plasma display panel
  • a first embodiment of the present invention provides a plasma display apparatus which comprises a firsts sub-field mapper for mapping inputted video data to a first sub-field group, a second sub-field mapper for mapping the same video data to a second sub-field group, and a PDP for displaying an image formed by the data mapped to the first sub-field group and the data mapped to the second sub-field group consecutively within a frame.
  • a second embodiment of the present invention provides a plasma display apparatus which comprises a first gray level processor for modulating error-diffused data and processing a gray level of the data through dithering, a first sub-field mapper for mapping the gray level-processed data to a first sub-field group, a second gray level processor for modulating the error-diffused data and processing a gray level of the data through dithering, a second sub-field mapper for mapping the gray level-processed data to a second sub-field group, and a PDP for displaying an image formed by the data mapped to the first sub-field group and the data mapped to the second sub-field group consecutively within a frame.
  • the invention also provides corresponding methods.
  • the present invention improves gray level representation by minimizing flickering and contour step noise which are generated when a plasma display panel (PDP) is driven.
  • PDP plasma display panel
  • a plasma display apparatus comprises a firsts sub-field mapper for mapping inputted video data to a first sub-field group, a second sub-field mapper for mapping the same video data to a second sub-field group, and a PDP for displaying the data mapped to the first sub-field group and the data mapped to the second sub-field group consecutively within a frame time.
  • the sub-fields of each of the first sub-field group and the second sub-field group are arranged in a sequence that weights of the sub-fields are decreased.
  • the sub-fields of the first sub-field group are arranged in a sequence that weights of the sub-fields are increased, and the sub-fields of the second sub-field group are arranged in a sequence that weights of the sub-fields are decreased.
  • the sub-fields of the first sub-field group are arranged in a sequence that weights of the sub-fields are decreased, and the sub-fields of the second sub-field group are arranged in a sequence that weights of the sub-fields are increased.
  • One frame time approximately ranges from 16ms to 20ms.
  • a plasma display apparatus comprises a first gray level processor for modulating error-diffused data and processing a gray level of the data through dithering, a first sub-field mapper for mapping the gray level-processed data to a first sub-field group, a second gray level processor for modulating the error-diffused data and processing a gray level of the data through dithering, a second sub-field mapper for mapping the gray level-processed data to a second sub-field group, and a PDP for displaying the data mapped to the first sub-field group and the data mapped to the second sub-field group consecutively within a frame time.
  • Each of the first gray level processor and the second gray level processor comprises a data modulating unit for correcting at least any one between brightness and color temperature of error-diffused data and a half-tone post-processing unit for dithering the modulated data.
  • FIG. 4 is a block view describing a structure of a plasma display apparatus according to a first embodiment of the present invention.
  • the plasma display apparatus of the first embodiment comprises an inverse gamma corrector 101, a half-tone processor 102, a first sub-field mapper 104, a second sub-field mapper 105, a data sorter 106, and a PDP 107.
  • the inverse gamma corrector 101 performs 2.2 inverse gamma correction onto 10-bit digital video data, or RGB data, and supplies the inverse gamma-corrected digital video data in the form of 10-bit integer part and 6-bit decimal part to the half-tone processor 102.
  • the half-tone processor 102 delicately controls a brightness value by diffusing the quantization error of the decimal part of the inverse gamma-corrected digital video data, i.e., RGB data, into adjacent cells. For this, the half-tone processor 102 multiplies the decimal part by a predetermined error diffusion coefficient, for example, a Floid-Steinberg coefficient.
  • the digital video data error-diffused in the half-tone processor 102 are supplied to the first sub-field mapper 104 and the second sub-field mapper 105 in 9 bits.
  • the first sub-field mapper 104 maps the digital video data inputted from the half-tone processor 102 to sub-fields of a first sub-field group on a bit basis, and supplies the mapping data to the data sorter 106.
  • the second sub-field mapper 105 maps the digital video data inputted from the half-tone processor 102 to sub-fields of a second sub-field group on a bit basis, and supplies the mapping data to the data sorter 106.
  • the data sorter 106 combines the digital video data mapped to the first sub-field group and the digital video data mapped to the second sub-field group, and supplies the digital video data mapped to the first sub-field group to a data integrated circuit of the PDP, which is not illustrated in the drawing, and the digital video data mapped to the second sub-field group to the data integrated circuit of the PDP consecutively within a frame time to thereby realize image o the PDP 107.
  • the plasma display apparatus of the first embodiment includes two sub-field mappers to map data to two sub-field groups included in one frame, and consecutively realizes the mapped data on the PDP to thereby prevent contour step noise.
  • the prevent embodiment presents two sub-field mappers but the number of sub-field mappers may be determined according to the number of sub-field groups included in one frame.
  • the plasma display apparatus processes image by dividing one frame into a plurality of sub-field groups, e.g., a first sub-field group and a second sub-field group, supplying data mapped to each sub-field group to the PDP, and displaying image.
  • one frame time (T) approximately ranges from 16ms to 20ms, and an arrangement sequence of the sub-fields by weight within one frame is as shown in FIG. 4.
  • FIGS. 5A to 5C show a weight arrangement of sub-fields included in a frame according to the first embodiment of the present invention.
  • the weight of sub-fields included on one frame may be arranged in various forms in the first embodiment of the present invention.
  • one frame includes two or more (not shown) sub-field groups and each sub-field group SFG1 or SFG2 includes sub-fields arranged in a sequence that the weight of the sub-fields increases.
  • the sub-fields of each sub-field group are arranged in a sequence that their gray levels increase.
  • one frame includes two or more (not shown) sub-field groups and each sub-field group SFG1 or SFG2 includes the sub-fields arranged in a sequence that the weight of the sub-fields decreases.
  • one frame includes two or more (not shown) sub-field groups and each sub-field group SFG1 or SFG2 includes sub-fields arranged in a different sequence.
  • the sub-fields of one sub-field group among the sub-field groups are arranged in a sequence that their weight expressed as gray levels increase or in a sequence that their weight expressed as gray levels decrease.
  • FIG. 5C shows sub-fields of one sub-field group arranged in a different sequence from a sequence that those of another sub-field group are arranged according to a predetermined rule
  • the sub-fields of each sub-field group may be randomly arranged without any rule on their weight.
  • 'Vsync' denotes a vertical sync signal for forming a frame
  • 'SFP' denotes the size of weight according to a sub-field pattern
  • FIG. 6 is a block view describing a structure of a plasma display apparatus according to a second embodiment of the present invention.
  • the plasma display apparatus suggested in the second embodiment of the present invention comprises an inverse gamma corrector 111, a half-tone pre-processor 112, a first gray level processor 113, a second gray level processor 114, a first sub-field mapper 115, a second sub-field mapper 116, a data sorter 17, and a PDP 118.
  • the inverse gamma corrector 111 performs 2.2 inverse gamma correction onto 10-bit digital video data, i.e., RGB data, and supplies the inverse gamma-corrected digital video data in the form of a 10-bit integer part and a 6-bit decimal part to the half-tone pre-processor 112.
  • the half-tone pre-processor 112 delicately controls a brightness value by diffusing a quantization error of the decimal part of the inverse gamma-corrected digital video data, i.e., RGB data, into adjacent cells. For this, the half-tone pre-processor 112 multiplies the decimal part by a predetermined error diffusion coefficient, for example, a Floid-Steinberg coefficient.
  • the digital video data error-diffused in the half-tone pre-processor 112 are supplied to the first and second gray level processors 113 and 114 in 9 bits.
  • the first and second gray level processors 113 and 114 modulate the error-diffused data and improve the gray level representation of the data through dithering.
  • each of the first and second gray level processors 113 and 114 comprises a data modulating unit 113a or 114a for correcting at least any one between the brightness and color temperature, and a half-tone post-processing unit 113b or 114b for dithering the modulated data.
  • the first data modulating unit 113a stores brightness correction data established based on the first sub-field group SFG1 to correct a brightness difference, when there is a difference in brightness between the first sub-field group SFG1 and the second sub-field group SFG2, or it stores color temperature correction data for correcting the color temperature of data mapped to the first sub-field group SFG1.
  • the first data modulating unit 113a modulates the digital video data inputted from the half-tone pre-processor 112 in 1:1 based on the predetermined brightness correction data or color temperature correction data and supplies the modulated data to the first sub-filed mapper 115.
  • the second data modulating unit 114a too, stores brightness correction data established based on the second sub-field group SFG2 to correct a brightness difference, when there is a difference in brightness between the first sub-field group SFG1 and the second sub-field group SFG2, or it stores color temperature correction data for correcting the color temperature of data mapped to the second sub-field group SFG2.
  • the second data modulating unit 114a modulates the digital video data inputted from the half-tone pre-processor 112 in 1:1 based on the predetermined brightness correction data or color temperature correction data and supplies the modulated data to the second sub-filed mapper 116.
  • the first and second data modulating units 113a and 114a includes a Read Only Memory (ROM) for storing the brightness correction data or the color temperature correction data and a look-up table comprising a memory control circuit for designating the address of the ROM.
  • ROM Read Only Memory
  • the first half-tone post-processing unit 113a dithers the data outputted from the first data modulating unit 113a with a dither mask which is optimally designed based on the first sub-field group (SFG1) to thereby make the quantization error of the decimal part a threshold value, and supplies 9-bit digital video data to the first sub-field mapper 115.
  • a dither mask which is optimally designed based on the first sub-field group (SFG1) to thereby make the quantization error of the decimal part a threshold value, and supplies 9-bit digital video data to the first sub-field mapper 115.
  • the second half-tone post-processing unit 114b dithers the data outputted from the second data modulating unit 114a with a dither mask which is optimally designed based on the second sub-field group (SFG2) to thereby make the quantization error of the decimal part a threshold value, and supplies 9-bit digital video data to the second sub-field mapper 116.
  • a dither mask which is optimally designed based on the second sub-field group (SFG2) to thereby make the quantization error of the decimal part a threshold value, and supplies 9-bit digital video data to the second sub-field mapper 116.
  • the first sub-field mapper 115 maps the digital video data inputted from the first half-tone post-processing unit 113b to a predetermined first sub-field group SFG1 on a bit basis and supplies the mapping data to the data sorter 117.
  • the second sub-field mapper 116 maps the digital video data inputted from the second half-tone post-processing unit 114b to a predetermined second sub-field group SFG2 on a bit basis and supplies the mapping data to the data sorter 117.
  • the data sorter 117 combines the digital video data mapped to the first sub-field group SFG1 and the digital video data mapped to the second sub-field group SFG2, supplies the digital video data mapped to the first sub-field group SFG1 to data integrated circuits of the PDP, which are not shown in the drawing, and then supplies the digital video data mapped to the second sub-field group SFG2 to data integrated circuits of the PDP consecutively within a frame time.
  • the first data modulating unit 113a may perform inverse gamma correction onto the digital video data to be mapped to the first sub-field group SFG1
  • the second data modulating unit 114a may perform inverse gamma correction onto the digital video data to be mapped to the second sub-field group SFG2.
  • the inverse gamma corrector 111 is removed.
  • the plasma display apparatus of the second embodiment comprises two sub-field mappers to map data to two sub-field groups included in one frame. When it represents the mapped data on the PDP consecutively, it can prevent the contour step noise.
  • the plasma display apparatus can improve gray level representation by correcting the brightness or color temperature of the data.
  • the plasma display apparatus of the second embodiment processes image by dividing one frame into a plurality of sub-field groups, e.g., a first sub-field group and a second sub-field group, which is the same as in the plasma display apparatus of the first embodiment, supplying data mapped to each sub-field group to the PDP, and displaying the image.
  • one frame time (T) approximately ranges from 16ms to 20ms, and the sub-fields of one frame are arranged by weight in a sequence described in the plasma display apparatus of the first embodiment. Since the arrangement sequence is the same, further description on it will not be provided herein.
  • the plasma display apparatus of the present invention is not limited to a case where the frequency of video signals is 50Hz but it can be applied to a case where the frequency of video signals is 60Hz, such as the National Television System Committee (NTSC) television.
  • NTSC National Television System Committee
EP06255670A 2006-11-03 2006-11-03 Plasmaanzeigevorrichtung Withdrawn EP1918902A1 (de)

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EP06255670A EP1918902A1 (de) 2006-11-03 2006-11-03 Plasmaanzeigevorrichtung

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0982708A1 (de) * 1998-08-19 2000-03-01 Deutsche Thomson-Brandt Gmbh Verfahren und Vorrichtung zur Verarbeitung von Videobildern, insbesondere zur Reduzierung von grossflächigem Flimmereffekt
WO2002045062A2 (en) * 2000-11-30 2002-06-06 Thomson Licensing S.A. Method and apparatus for controlling a display device
EP1589516A2 (de) * 2004-04-23 2005-10-26 Lg Electronics Inc. Plasmaanzeigegerät und Steuerverfahren dafür
EP1679679A1 (de) 2005-01-06 2006-07-12 Thomson Licensing, S.A. Verfahren und Vorrichtung zur Bearbeitung von Videobildern, im Besonderen zur Verminderung von großflächigen Flimmereffekten und Falschkontureffekten
EP1715469A2 (de) 2005-04-21 2006-10-25 LG Electronics, Inc. Plasmaanzeigevorrichtung und Verfahren zu ihrer Ansteuerung mit verbesserten durch Unterrahmenmodulation ausgeführten Graustufen und reduziertem Flimmern

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0982708A1 (de) * 1998-08-19 2000-03-01 Deutsche Thomson-Brandt Gmbh Verfahren und Vorrichtung zur Verarbeitung von Videobildern, insbesondere zur Reduzierung von grossflächigem Flimmereffekt
WO2002045062A2 (en) * 2000-11-30 2002-06-06 Thomson Licensing S.A. Method and apparatus for controlling a display device
EP1589516A2 (de) * 2004-04-23 2005-10-26 Lg Electronics Inc. Plasmaanzeigegerät und Steuerverfahren dafür
EP1679679A1 (de) 2005-01-06 2006-07-12 Thomson Licensing, S.A. Verfahren und Vorrichtung zur Bearbeitung von Videobildern, im Besonderen zur Verminderung von großflächigen Flimmereffekten und Falschkontureffekten
EP1715469A2 (de) 2005-04-21 2006-10-25 LG Electronics, Inc. Plasmaanzeigevorrichtung und Verfahren zu ihrer Ansteuerung mit verbesserten durch Unterrahmenmodulation ausgeführten Graustufen und reduziertem Flimmern

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KYOUNGHO KANG ET AL: "A New 42-in. AC PDP Using MAoD II Driving Scheme", 2001 SID INTERNATIONAL SYMPOSIUM, vol. XXXII, 3 June 2001 (2001-06-03), SAN JOSE CONVENTION CENTER, CALIFORNIA, pages 1130, XP007007751 *

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