EP1909395A1

EP1909395A1 - Communication apparatus and decoding method

Info

Publication number: EP1909395A1
Application number: EP06768155A
Authority: EP
Inventors: Wataru c/o Mitsubishi Electric Corp. MATSUMOTO; Rui c/o Mitsubishi Electric Corporation SAKAI; Hideo c/o Mitsubishi Electric Corporation YOSHIDA; Yoshikuni Mitsubishi Electric Corp. MIYATA
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 2005-07-13
Filing date: 2006-07-12
Publication date: 2008-04-09
Anticipated expiration: 2026-07-12
Also published as: KR100983692B1; KR20080015145A; US8132080B2; EP1909395B1; EP1909395A4; WO2007007801A1; CN101248583B; JP4627317B2; US20090132887A1; JPWO2007007801A1; CN101248583A

Abstract

A communication apparatus according to the present invention is a communication apparatus at a receiving side that decodes an LDPC-encoded codeword, and includes: an intermediate-result retaining unit (21) that retains an intermediate result of a decoding; a row processing unit (22) that repeatedly performs row processing of calculating a column-processing LLR for each column and each row in a check matrix, by a predetermined number of times; and a column processing unit (23) that calculates a row-processing LLR for each column and each row of the check matrix, and further repeatedly performs column processing of holding a minimum value k of absolute values of the row-processing LLR for the row weight in the intermediate-result retaining unit (21). The row processing unit (22) and the column processing unit (23) alternately execute the process in column unit. The column processing unit (23) cyclically updates the minimum k value of each row, and the row processing unit (22) performs calculation using an approximate minimum value.

Description

TECHNICAL FIELD

The present invention relates to an error correction technology in digital communication, and, particularly to a communication apparatus at a receiving side and a decoding method for decoding an LDPC (Low-Density Parity Check)-encoded signal.

BACKGROUND ART

As basic algorithms of decoding an LDPC code, there are a "Sum-Product algorithm" and a "Min-Sum algorithm". According to these algorithms, the decoding is performed while repeatedly calculating a likelihood ratio (LLR) as probabilistic reliability information of a reception signal (see Nonpatent Document 1). The "Sum-Product algorithm" has high decoding performance, but has high calculation cost for packaging such as the need for holding a table, because a calculation using a mathematical function is required. At least a memory that stores intermediate values by only the number of "1" contained in a binary check matrix of "0" and "1" is necessary. On the other hand, the "Min-Sum algorithm" does not require a mathematical function, and has small calculation cost, but decoding performance is degraded.
The "Sum-Product algorithm" is explained. First, at the transmitter side, transmission data is LDPC encoded using a parity check matrix H of M rowsxN columns, and a codeword c= (c₁, c₂, ... , c_N), c_n=0, 1 (n=1, 2, ..., N). A modulation such as a BPSK (Binary Phase Shift Keying) modulation is performed to this codeword c, and a modulation signal x=(x₁, x₂, ..., x_N) is sent.
On the other hand, the receiver side receives, via an Additive White Gaussian Noise Channel (AWGN channel), a signal y=(y₁, y₂, ..., y_N) as expressed by the following Equation (1) : $y_{n} = x_{n} + e_{n}$

where e_n is a Gaussian noise series of which average is 0, and a variance σ²=N₀/2
At the receiver side, a predetermined digital demodulation corresponding to the above BPSK modulation is performed to the modulation signal received via the above channel. Further, iterative decoding by the "Sum-Product algorithm" is executed to a logarithmic likelihood ratio (LLR) obtained from the demodulation result, and a hard decision result is finally output.
A conventional decoding method "Sum-Product algorithm" implemented by the above receiver is shown below.

(Initialization step)

First, the number of repetitions l=1 and the maximum number of repetitions l_max are set, and, as LLR: β_mn ^(l=1) from a bit node to a check node at the initial time, a reception LLR:λ_n is input as given by the following Equation (2):. $\begin{array}{l} {β_{mn}}^{(1)} = λ_{n} \\ n = 1, 2, \dots, N \\ m = 1, 2, \dots, M \end{array}$

(Row processing step)

Next, as row processing, LLR:α_mn ⁽¹⁾ at the first repetition (repetition first-time LLR:α_mn ⁽¹⁾ of a bit n to be sent from the check node m to the bit node n is updated for each m and n by the following Equation (3):
$\begin{array}{l} [Expression 1] \\ α_{mn}^{} = 2 \tanh^{- 1} (\prod_{nʹ \in N (m) \ n} \tanh (\frac{β_{mnʹ}^{(l - 1)}}{2})) \end{array}$
where N(m) is a set of column numbers having "1" of a m-th row, n' is N(m) other than n, and β_mn,^(l-1) is LLR from the (l-1)-thbit node to the check node other than an n-th column.

(Column processing step)

Next, as a column processing, a repetition first-time LLR:β_mn ⁽¹⁾ of a bit n to be sent from the bit node n to the check node m is updated for each m and n by the following Equation (4):
$\begin{matrix} [Expression 2] \\ β_{mn}^{} = λ_{n} + \sum_{mʹ \in M (n) \ m} α_{mʹn}^{(1)} \end{matrix}$
A repetition first-time posterior value β_n ⁽¹⁾ of a bit n for a hard decision is updated for each n by the following Equation (5) :
$\begin{matrix} [Expression 3] \\ β_{n}^{} = λ_{n} + \sum_{mʹ \in M (n)} α_{n}_{(1)} \end{matrix}$
where M(n) is a set of row numbers having "1" of an n-th column, m' is M(n) other than m, and β_m'n ⁽¹⁾ is LLR from the first check node to the bit node other than an m-th row.

(Stop regulation)

Thereafter, when the repetition first-time posterior value β_n ⁽¹⁾ of the bit n is "β_n ⁽¹⁾>0", a decoding result is "x_n'=1" (where x' corresponds to the original transmission signal x). On the other hand, when "β_n ⁽¹⁾≤0", a decoding result is "x_n'=0", and a decoding result x'=(x₁', x₂',...., X_N') is obtained.
When a result of parity check is "Hx'=0" or when the number of repetitions is "l=1_max" (when any one of these condition is satisfied), a decoding result x' in this case is output. When none of the two conditions is satisfied, "l=l+1" is set, and the process control returns to the above row processing. Thereafter, the calculation is sequentially performed.
Nonpatent Document 1: Low-Density Parity-Check Codes and Its Decoding Algorithm, LDPC (Low Density Parity Check) code/sum-product decoding algorithm, Tadashi Wadayama, Triceps.

DISCLOSURE OF INVENTION

PROBLEM TO BE SOLVED BY THE INVENTION

However, while the above "Sum-Product algorithm" is known to have high decoding performance, this algorithm requires a repeated calculation (calculation of tanh^-1), using a mathematical function. Therefore, this algorithm has a problem in that calculation load at the receiver side becomes high whether hardware or software is used to realize this algorithm. There is also a method of holding a predetermined table to decrease the calculation load (table lookup). However, this method increases the memory capacity necessary to store the table.
In the above "Sum-Product algorithm", at least a memory that stores intermediate values (algorithmic likelihood ratios of each row, updated values for each repetition, etc.) by only the number of "1 (weight)" contained in a binary check matrix of "0" and "1" is necessary. That is, a consumption amount of the memory becomes very large. Further, the above "Sum-Product algorithm" has also problems that the number of quantization bits is large, the number of repetitions is large, etc.
The present invention has been achieved to solve the above problems in the conventional technology and it is an object of the present invention to provide a communication apparatus and a decoding method, capable of reducing calculations and a memory capacity required in decoding of an LPDC encoded codeword. The invention also has an object of providing a communication apparatus and a decoding method, capable of achieving a reduction in the quantization size and a reduction in the number of repetitions.

MEANS FOR SOLVING PROBLEMS

To solve the problems and achieve the object mentioned above, there is provided a communication apparatus that decodes an LDPC-encoded codeword using a check matrix including: a retaining unit that retains an intermediate value obtained by a predetermined process in a decoding algorithm; a row processing unit that performs row processing of calculating a logarithmic likelihood ratio (logarithmic likelihood ratio to be sent from a check node to a bit node: column-processing LLR) used in the column processing based on an absolute value of a logarithmic likelihood ratio (logarithmic likelihood ratio to be sent from a bit node to a check node: row-processing LLR) corresponding to a row weight of a check matrix; and a column processing unit that calculates a row-processing LLR to be used in the row processing based on a column-processing LLR corresponding to a column weight, and stores a minimum value of absolute values of the row-processing LLR in the retaining unit. The column processing unit performs decoding while updating the minimum k value of the row.

EFFECT OF THE INVENTION

According to the present invention, in the LDPC decoding, an absolute value of an LLR for row processing is reduced to a minimum k value in a row unit by a cyclic structure. Therefore, there is an effect that the memory capacity required to store the absolute values can be substantially reduced. Further, according to the present invention, probability propagation can be performed more efficiently than that performed by the conventional "Min-Sum algorithm". Therefore, the number of repetitions of decoding can be substantially reduced. As a result, the calculations in decoding can be substantially reduced.

BRIEF DESCRIPTION OF DRAWINGS

[Fig. 1] Fig. 1 is a configuration example of a communication system including an LDPC encoder and an LDPC decoder.
[Fig. 2] Fig. 2 is a configuration example of a row processing unit that executes a row processing step of the "Min-Sum algorithm" in the LDPC decoder.
[Fig. 3] Fig. 3 is a configuration example of a column processing unit that performs a column processing step of the "Min-Sum algorithm" in the LDPC decoder.
[Fig. 4] Fig. 4 is a flowchart of a process according to the "Min-Sum algorithm".
[Fig. 5-1] Fig. 5-1 is a configuration example of an LDPC decoder according to a first embodiment.
[Fig. 5-2] Fig. 5-2 is a configuration example of the LDPC decoder according to the first embodiment.
[Fig. 6] Fig. 6 is a configuration example of a row processing unit that performs row processing according to the "Cyclic approximated min algorithm".
[Fig. 7-1] Fig. 7-1 is a configuration example of a column processing unit that performs column processing according to the "Cyclic approximated min algorithm".
[Fig. 7-2] Fig. 7-2 is a configuration example of the column processing unit that performs column processing according to the "Cyclic approximated min algorithm".
[Fig. 8] Fig. 8 is a schematic diagram for explaining column processing of n=15 when information of n=15 is held in a Min2LLR.
[Fig. 9] Fig. 9 is a flowchart of a process according to the "Cyclic approximated min algorithm".
[Fig. 10] Fig. 10 is an example of column number notation.
[Fig. 11] Fig. 11 is a graph of results of a comparison simulation between the "Cyclic approximated min algorithm" and the "Min-Sum algorithm".
[Fig. 12] Fig. 12 is a graph of results of a comparison simulation between the "Cyclic approximated min algorithm" and the "Min-Sum algorithm".
[Fig. 13]. Fig. 13 is a configuration example of an LDPC decoder according to a second embodiment.
[Fig. 14] Fig. 14 is a graph of performance comparison regarding the number of repetitions.
[Fig. 15] Fig. 15 is a configuration example of a row processing unit that performs row processing according to a third embodiment.
[Fig. 16] Fig. 16 is a configuration example of a row processing unit that performs row processing according to a fourth embodiment.
[Fig. 17] Fig. 17 is a graph of results of comparison between a decoding algorithm using the "Cyclic approximated min algorithm" or the "Overlapped cyclic approximated min algorithm" applied to the "δ min algorithm", and the "Sum-Product algorithm".
[Fig. 18] Fig. 18 is a configuration example of a row processing unit that performs row processing according to a fifth embodiment.
[Fig. 19] Fig. 19 is a configuration example of a column processing unit that performs column processing in the "Serial cyclic approximated min algorithm" according to a sixth embodiment.

EXPLANATIONS OF LETTERS OR NUMERALS

1: LDPC encoder
2: Modulator
3: Communication channel
4: Demodulator
5: LDPC decoder
11: Reception-LLR calculating unit
12: Decoding core unit
21, 21a: Decoding core unit
22, 22-1, 22-2, 22-G: Row processing unit
23, 23-1, 23-2, 23-G: Column processing unit
24: Decoding-result determining unit
25, 25a: Controller
31, 31a, 31b, 31c: Minimum-value selecting unit
32: Sign calculating unit
33: LLR calculating unit
41: α adding unit
42: λ adding unit
43: Minimum-k-value comparing unit
44: Sign calculating unit
45: Switch

BEST MODE(S) FOR CARRYING OUT THE INVENTION

Exemplary embodiments of a communication apparatus and a decoding method according to the present invention are explained in detail below with reference to the accompanying drawings. Note that the present invention is not limited to the embodiments. The present invention can be applied to decoding at a terminal and a base station, in wireless communication through, for example, a portable telephone. The present invention can also be applied to decoding in satellite communication, an HDD, optical communication, a wireless LAN, a quantum code, and the like.

First Embodiment

Described first is positioning, in a communication system, of a communication apparatus and an LDPC decoder that implements a decoding method according to the present invention. Fig. 1 is a configuration example of the communication system including an LDPC encoder and an LDPC decoder. In Fig. 1, a communication apparatus at the transmission side (hereinafter, "transmitting device") includes an LDPC encoder 1 and a modulator 2, and a communication apparatus at the receiving side (hereinafter, "receiving device") includes a demodulator 4 and an LDPC decoder 5.
A flow of encoding and decoding in the communication system that employs an LDPC code is briefly explained. The LDPC encoder 1 within the transmitting device generates a generation matrix G of K rows×N columns according to a known method (K: an information length, N: a codeword length). The LDPC encoder 1 receives a message (m₁, m₂, ..., m_K) of the information length K, and generates a codeword C, using this message and the above generated matrix G, as represented by the following Equation (6): $\begin{array}{l} C & = (m_{1}, m_{2}, \dots {, m}_{k}) G \\ = (c_{1} c_{2} \dots c_{N}) \end{array}$
When a parity check matrix for the LDPC is H (M rows×N columns), the generation matrix G satisfies GH^T=0 (T is a transposed matrix), H (c₁, c₂, ..., c_N) T=0 .
The modulator 2 performs a digital modulation to the codeword C generated by the LDPC encoder 1, by a predetermined modulation system such as BPSK, multivalue PSK, multivalue QAM, etc., and transmits a modulation signal x=(x₁, x₂, ..., x_N) to the receiving device via a communication channel 3.
On the other hand, in the receiving device, the demodulator 4 performs a digital demodulation corresponding to the above modulation system such as BPSK, multivalue PSK, multivalue QAM, etc. to a modulation signal y= (y₁, y₂, ..., y_N) that is received via the communication channel 3. Further, the LDPC decoder 5 performs decoding according to the decoding algorithm of the present embodiment, described later, using a logarithmic likelihood ratio (LLR) obtained from the demodulation result, and outputs a hard decision value (corresponding to the original message m₁, m₂, ..., m_K) as a decoding result.
Before explaining the decoding algorithm of the present embodiment, the "Min-Sum algorithm" is explained as the conventional decoding algorithm that is the basis of the decoding algorithm.
According to the "Min-Sum algorithm", the initialization step similar to that of the "Sum-Product algorithm" described above is first performed. Next, the row processing step of the "Min-Sum algorithm" is performed. Thereafter, the column processing step and the stop regulation similar to those of the "Sum-Product algorithm" described above are performed to calculate and update probability information.
Fig. 2 is a configuration example of a row processing unit that performs a row processing step of the "Min-Sum algorithm" in an LDPC decoder. This row processing unit includes: a minimum-value selecting unit 101 including a memory unit 111 that stores therein the LLR: β_mn' ^(l=1) of a row weight portion of the parity check matrix H, and a comparator 112 that compares sizes of the LLR and outputs a minimum value of the LLR; a sign calculating unit 102 including a memory unit 113 that stores therein a sign of an LLR of the row weight portion, and a multiplying unit 114 that multiplies signs of the LLR (+ or -); and an LLR calculating unit 103 that calculates an LLR:α_mn ⁽¹⁾ by multiplying a minimum value obtained from the minimum-value selecting unit 101 with a multiplication result of signs (+ or -) obtained from the sign calculating unit 102.
In the row processing unit, the comparator 112 of the minimum-value selecting unit 101 includes a plurality of comparators of two inputs (a, b). Each comparator receives LLR for comparison from the above memory unit 111 and a former-stage comparator (the first-stage comparator receives LLR from only the memory unit 111), and when "|a|<|b|", each comparator outputs |a|. In other cases, each comparator outputs |b|, thereby outputting a minimum value of absolute values of the LLR. The LLR calculating unit 103 multiplies the above minimum value with the multiplication result of the above sign, and delivers the LLR:α_mn ⁽¹⁾ as the multiplication result, to the column processing unit.
Fig. 3 is a configuration example of the column processing unit that performs a column processing step of the "Min-Sum algorithm" in an LDPC decoder. This column processing unit retains the LLR:α_m'n ⁽¹⁾ of a column weight of the parity check matrix H, and adds each LLR, thereby outputting the repetition first-time posterior value β_n ⁽¹⁾.

(Row processing step)

The row processing of the above "Min-Sum algorithm" can be generalized by the following Equation (7). In this case, as the row processing, the repetition first-time LLR: α_mn ⁽¹⁾ of the bit n from the check node m to the bit node n is updated for each of m and n by the following Equation (7):
$\begin{array}{l} [Expression 4] \\ \begin{array}{l} α_{mn}^{(l)} & = 2 \tanh^{- 1} (\prod_{nʹ \in N (m) \ n} \tanh (\frac{β_{mnʹ}^{(l - 1)}}{2})) \\ = 2 \tanh^{- 1} (\prod_{nʹ \in N (m) \ n} sgn (β_{mnʹ}^{(l - 1)}) \cdot \prod_{nʹ \in N (m) \ n} \tanh (\frac{|β_{mnʹ}^{(l - 1)}|}{2})) \\ = \prod_{nʹ \in N (m) \ n} sgn (β_{mnʹ}^{(l - 1)}) \cdot 2 \tanh^{- 1} (\prod_{nʹ \in N (m) \ n} \tanh (\frac{|β_{mnʹ}^{(l - 1)}|}{2})) \\ \approx \prod_{nʹ \in N (m) \ n} sgn (β_{mnʹ}^{(l - 1)}) \cdot \min_{nʹ \in N (m) \ n} |β_{mnʹ}^{(l - 1)}| \end{array} \end{array}$
where min |β_mn' ^(l-1)| is the minimum value of absolute values of the LLR:β_mn' ^(l-1) excluding the n-th column in the m-th row of the parity check matrix H, and sgn (β_mn' ^(l-1)) is the sign of the LLR:β_mn,^(l-1) excluding the n-th column.
As described above, according to the "Min-Sum algorithm", after a row processing step, processing based on column processing and stop regulation similar to those of the "Sum-Product algorithm" is performed to obtain a final sign result.
Next, the flow of the process according to the "Min-Sum algorithm" is briefly explained referring to Fig. 4.
According to the "Min-Sum algorithm", a reception LLR is calculated from reception information (steps S1, S2), and the calculation result is set in the memory unit 111 as an initial value. Further, the number of repetitions is initialized as l=1 (step S3). Row processing is performed first time in the iterative decoding calculation (repetition first-time decoding calculation) (step S4: the first iterative decoding to the last iterative decoding). Next, column processing in the repetition first-time decoding calculation is performed, and thereafter, a posterior value calculated in the repetition first-time decoding calculation is subjected to a hard decision. This determination value is determined as a decoding result, and a parity check is performed (stop regulation). In the above stop regulation, when the parity check result becomes OK or when the number of repetitions becomes l=1_max, a decoding result this time is finally output (step S5).
In the above "Min-Sum algorithm", calculations and the required memory capacity are reduced from those of the "Sum-Product algorithm", by approximating the row processing of the "Sum-Product algorithm", i.e., Equation (3). However, in the above "Min-Sum algorithm", a large memory capacity corresponding to the number of "1 (weight)" contained in the parity check matrix H is necessary to store the intermediate value. Further improvement is necessary to reduce the required memory capacity.
The decoding algorithm according to the present embodiment explained below achieves a further reduction in required memory capacity and calculations, and is the improved algorithm of the "Min-Sum algorithm" as the approximated decoding method of the "Sum-Product algorithm", for example.
A configuration of the LDPC decoder 5 constituting the receiving device according to the present invention, and a decoding method (decoding algorithm) performed by the LDPC decoder 5, are explained in detail below with reference to the drawings.
Fig. 5-1 depicts a configuration of the LDPC decoder 5 according to the present embodiment. This LDPC decoder 5 includes a reception-LLR calculating unit 11 that calculates the reception LLR from the reception information, and the decoding core unit 12 that performs decoding according to the present embodiment. The decoding core unit 12 includes an intermediate-result retaining unit 21 configured by a memory which stores therein an intermediate result (intermediate value) of decoding, a row processing unit 22 that performs row processing according to the present embodiment, a column processing unit 23 that performs column processing according to the present embodiment, a decoding-result determining unit 24 that performs a hard decision on a posterior value in the column processing and an error determination of a parity check result, as a stop regulation according to the present embodiment, and a controller 25 that performs a repetition control of decoding.
The decoding algorithm according to the present embodiment is a method of cyclically updating only the absolute value of the LLR of the minimum k value. Because this algorithm is the method of decoding using an approximate minimum value instead of an accurately minimum value, this method is hereinafter called the "Cyclic approximated min algorithm". The minimum k value represents "from the minimum value to the k-th value in the ascending order.
The "Cyclic approximated min algorithm" executed in the receiving device is shown below.

(Initialization step)

First, the number of repetitions 1=1 and the maximum number of repetitions l_max are set. The LLR of the minimum k value of the m-th row at the initial time is set as β_mn(i) ⁽⁰⁾, and a reception LLR:λ_n is input to obtain B_mn(i) as in the following Equation (8). As a sign of the LLR:β_mn ⁽⁰⁾ of the m-th row at the initial time, sgn(λ_n) is input to obtain S_m as in the following Equation (8):
$\begin{array}{l} [Expression 5] \\ \begin{array}{l} B_{mn (i)} & = |β_{mn (i)}^{(0)}| = \min_{n \in N (m) \ \{n\} \{(1), n (2), \dots, n (i - 1)\}} [|λ_{n}|], \forall i \in [1 k] \\ S_{m} & = \prod_{n \in N (m)} sgn (λ_{n}) \\ n (i) & = \arg \min_{n \in N (m) \ \{n\} \{(1), n (2), \dots, n (i - 1)\}} [|λ_{n}|] \\ n \\ (0) & = φ \end{array} \end{array}$
where B_mn(i) is an absolute value of the LLR:β_mn(i) of the minimum k value of the m-th row, n(i) is a column number of the minimum i-th LLR in B_mn(i), and S_m is a product of signs (+ or -) of the LLR:β_mn of the m-th row.

(Row processing step)

In the present embodiment, a starting column of the row processing is arbitrary. At the stage where the process ends to the last column, decoding is performed again cyclically from the first column. As the row processing, the repetition first-time LLR: α_mn ⁽¹⁾ of the bit n to be sent from the check node m to the bit node n is updated for 1≤n≤N and for each m by the following Equation (9) :
$\begin{array}{l} [Expression 6] \\ \begin{array}{l} α_{mn}^{(1)} & = \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ < n \end{array}} sgn (β_{mnʹ}^{(1)}) \cdot \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ > n \end{array}} sgn (β_{mnʹ}^{(l - 1)}) \cdot \min_{nʹ \in N_{k} (m) \ n} [B_{mnʹ}] \\ = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \min_{nʹ \in N_{k} (m) \ n} [B_{mnʹ}] \\ = S_{m}^{ʹ} \cdot \min_{nʹ \in N_{k} (m) \ n} [B_{mnʹ}] \\ S_{m}^{ʹ} & = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \end{array} \end{array}$
where N_k(m) is the set of n(i) of the m-th row, and is expressed as N_k(m)={n (1), n(2), ..., n(k)}. Specifically, when the current column number is n, a column number that satisfies "n'<n" takes the product of signs of the LLR:β_mn' ⁽¹⁾ updated in the first-time column processing, and a column number that satisfies "n'>n" takes the product of signs of the LLR:β_mn' ^(l-1) updated by the (1-1)-th time column processing. A result of multiplying these results by the minimum LLR:min[β_mn'] in the minimum k value of the m-th row is set as the updated LLR:α_mn ⁽¹⁾ of the column number n. In the present embodiment, the term of multiplying the product of the signs of β_mn' ⁽¹⁾ by the product of the signs of β_mn' ^(l-1) is substituted by the term of multiplying S_m updated at the (1-1)-th time by the sign of β_mn' updated at the (l-1)-th time. With this arrangement, calculations and the required memory capacity can be reduced.

(Column processing step)

Next, as the column processing, the repetition first-time LLR:β_mn ⁽¹⁾ of the bit n to be sent from the bit node n to the check node m is updated for each m and n by the following Equation (10):
$\begin{array}{l} [Expression 7] \\ \begin{array}{l} β_{mn}^{(1)} & = λ_{n} + \sum_{mʹ \in M (n) \ m} α_{mʹn}^{(1)} \\ S_{m} & = S_{m}^{ʹ} \cdot sgn (β_{mn}^{(1)}) \\ n (i) & = \arg \min_{nʹ \in N_{k} (m) \ \{n\} \{(1), n (2), \dots, n (i - 1) n (i)\}} [B_{mnʹ}, |β_{m}^{(1)}|] \\ B_{{mn}_{(i)}} & = \min_{nʹ \in N_{k} (m) \ \{n\} \{(1), n (2), \dots, n (i - 1) n (i)\}} [B_{mnʹ}, |β_{m}^{(1)}|], \forall i \in [1 k] \end{array} \end{array}$
Specifically, in the column number n, a result of the addition of the reception LLR:λ_n and a total value of the LLR:α_m'n ⁽¹⁾ other than the m-th row LLR updated in the first-time row processing is expressed as the updated LLR:β_mn' ⁽¹⁾. The above S_m' is multiplied by the sign (+ or -) of β_mn ⁽¹⁾ updated in the first-time column processing, thereby updating S_m to be used in the row processing. The two equations in Equation (10) prescribe the sort process (minimum k value) of B_mn(1).
To perform a hard decision for each n, the repetition first-time posterior value β_n ⁽¹⁾ of the bit n is updated by the following Equation (11);
$\begin{matrix} [Expression 8] \\ β_{n}^{(1)} = λ_{n} + \sum_{mʹ \in M (n)} α_{n}^{(1)} \end{matrix}$

(Stop regulation)

Thereafter, when the repetition first-time posterior value β_n ⁽¹⁾ of the bit n is "β_n ⁽¹⁾>0", for example, a decoding result is "x_n'=1" (where x' corresponds to the original transmission signal x). On the other hand, when "β_n ⁽¹⁾≤0", a decoding result is "x_n'=0", and a decoding result x'= (x₁', x₂', ... , X_N') is obtained.
When the result of parity check is "Hx'=0" or when the number of repetitions is "l=l_max" (when any one of these condition is satisfied), a decoding result x' in this case is output. When none of the two conditions is satisfied, "1=1+1" is set, and the process control returns to the above row processing. Thereafter, the calculation is sequentially performed.
A characteristic operation of the LDPC decoder 5 that performs the above "Cyclic approximated min algorithm" is explained in detail with reference to a configuration diagram.
Fig. 6 is a configuration example of the row processing unit 22 that performs row processing according to the "Cyclic approximated min algorithm". The row processing unit 22 includes a minimum-value selecting unit 31, a sign calculating unit 32, and an LLR calculating unit 33. In Fig. 6, a Min1LLR (minimum LLR of the m-th row) is B_mn(1), a Min2LLR (second minimum LLR of the m-th row) is B_mn(2), and these are the values retained in the intermediate-result retaining unit 21. In Fig. 6, S_m and the "sign of the LLR:β_mn of the m-th row and n-th column of the (1-1)-th time" are also the values retained in the intermediate-result retaining unit 21.
The minimum-value selecting unit 31 selects the Min2LLR(B_mn(2)) when the column number n to be row-processed coincides with the column number n (1) of the Min1LLR(B_mn(1)), and selects the Min1LLR(B_mn(1)) in other cases, and outputs the selected result. The sign calculating unit 32 multiplies the "S_m updated by the (1-1)-th time column processing" by the "sign of the LLR:β_mn of the m-th row and n-th column of the (1-1)-th time", and outputs S_m' as a result of the multiplication. In this case, S_m' is retained in the intermediate-result retaining unit 21. The LLR calculating unit 33 multiplies the minimum LLR obtained from the minimum-value selecting unit 31 by the multiplication result S_m' of the sign (+ or -) obtained from the sign calculating unit 32, thereby calculating LLR:α_mn ⁽¹⁾. Based on this, according to the "Min-Sum algorithm", the memory that has been necessary by the row weight portion can be reduced to the k value portion.
Fig. 7-1 is a configuration example of the column processing unit 23 that performs column processing according to the "Cyclic approximated min algorithm". This column processing unit 23 includes an α adding unit 41, a λ adding unit 42, a minimum-k-value comparing unit 43, and a sign calculating unit 44. In the present embodiment, k=3 is described as an example. In Fig. 7-1, LLR of a column weight portion, α_mn, λ_n, S_m', Min1LLR, Min2LLR, Min3LLR (the third-minimum LLR of the m-th row) are the values retained in the intermediate-result retaining unit 21.
In the column processing unit 23, the α adding unit 41 adds all LLR:α_m'n ⁽¹⁾ other than those of the m-th row LLR updated in the first-time row processing. Further, the λ adding unit 42 adds the reception LLR:λ_n to the result of the addition by the α adding unit 41, and outputs β_mn ⁽¹⁾. The minimum-k-value comparing unit 43 (k=3) receives |β_mn ⁽¹⁾|. Although not shown in Fig. 7-1, when n of the n-th column to be column processed coincides with any one of n(1), n(2), n(3) indicating the column numbers corresponding to B_mn(1); B_mn(2), B_mn(3), held in the Min1LLR, Min2LLR, Min3LLR respectively, for example, B_mn(i) of n=n(i) is thinned, and the operation as shown in Fig. 8 is performed. Specifically, information held in the Min2LLR is deleted, and information held in the Min3LLR is shifted to the Min2LLR. A maximum value "FFFF", for example (in the case of 16 bits), is stored in the Min3LLR. Accordingly, a comparison process excluding the column to be processed can be performed, and at least the Min3LLR can be necessarily updated by the column processing. After that, as shown in Fig. 7-1, |β_mn ⁽¹⁾| is compared with each of the Min1LLR, Min2LLR, Min3LLR. When "|β_mn ⁽¹⁾|<Min3LLR", the LLR of the minimum 3 value is updated. On the other hand, the sign of β_mn ⁽¹⁾ output by the λ adding unit 42 is retained in the intermediate-result retaining unit 21, as the "sign of the LLR: β_mn ⁽¹⁾ of the m-th row and n-th column of the first time". Further, the sign calculating unit 44 multiplies S_m' updated in the first-time row processing, by the sign of the above β_mn ⁽¹⁾, and updates S_m retained in the intermediate-result retaining unit 21, using a result of this multiplication. In comparing |β_mn ⁽¹⁾| with each of the Min1LLR, Min2LLR, Min3LLR, |β_mn ⁽¹⁾| is first compared with the Min2LLR as the center value of B_mn(i), and thereafter, comparison is performed in a tree shape as shown in Fig. 7-1. For example, there is an effect that the execution time becomes {(k+1)/2}/2 (where k is an odd number), as compared with the effect when |β_mn ⁽¹⁾| is compared first with the Min1LLR that becomes the minimum value. When k is an even number, there are two center values of B_mn(i). In this case, any one of the two values can be compared first. When k is an even number, there is an effect that the execution time becomes {k/2+1}/k (where k is an even number), as compared with the effect when |β_mn ⁽¹⁾| is compared first with the Min1LLR that becomes the minimum value.
The same process as described above can also be achieved with the configuration shown in Fig. 7-2. In this case, the α adding unit 41 performs only the addition of all the LLR of the column weight portion, and thereafter, the λ adding unit 42 adds λ_n, outputs a result of the addition to the decoding-result determining unit 24, and subtracts α_mn as the LLR of the m-th row. In this procedure, the same result as obtained in the above process can also be obtained. In this case, the configuration of the LDPC encoder becomes as shown in Fig. 5-2.
The flow of the process in the "Cyclic approximated min algorithm" according to the present embodiment is explained with reference to Fig. 9.
According to the "Cyclic approximated min algorithm", the reception-LLR calculating unit 11 calculates the reception LLR from the reception information (steps S11, S12), and sets a result of the calculation to the intermediate-result retaining unit 21, as an initial value (step S13). The controller 25 initializes the number of repetitions as 1=1 (step S13). The calculation of Equation (8) is cyclically performed from n=1 to n=N, using the λ adding unit 42, the minimum-k-value comparing unit 43, and the sign calculating unit 44, out of the column processing unit 23 (step S13).
Next, the decoding core unit 12 performs the first-time (first-time to the last-time) iterative decoding calculation (step S14). Specifically, as the first-time iterative decoding, the row processing unit 22 performs the row processing (using the reception LLR) to the row having "1" in the first column, and delivers a result of the calculation to the column processing unit 23. Thereafter, the column processing unit 23 performs the column processing of the first column, and retains (updates) B_mn(i) and S_m, as a result of the calculation, in the intermediate-result retaining unit 21. Thereafter, processing similar to the above is performed in the order of the second column, third column, ..., N-th column, and B_mn(i) and S_m are retained each time in the intermediate-result retaining unit 21 (corresponding to the iterative decoding first time). At the second and subsequent iterative decoding, the row processing is performed using the LLR and S_m updated in the processing one before. In other cases, decoding is performed as in the first time.
After executing the first-time iterative decoding, the decoding-result determining unit 24 performs a hard decision on the posterior value calculated at the repetition first time, determines this determination value as the decoding result x', and performs a parity check (stop regulation). In the stop regulation, when a result of the parity check is OK ("Hx'=0") or when the number of repetitions is l=1_max, the decoding result x' at this time is finally output (step S15). When the above two conditions are not satisfied, the controller 25 sets l=l+1, and the decoding core unit 12 performs the (l+1)-th time iterative decoding.
Deletion of the memory size according to a notation method of a column number is explained next. Fig. 10 depicts a column number notation according to the present embodiment. In the "Cyclic approximated min algorithm", column numbers are noted in the ascending order from n=0, for example. Conventionally, a column number n is expressed as the column number itself (absolute column number) of the parity check matrix. However, in the present embodiment, column numbers are expressed as relative column numbers, such as a minimum column number of "1" of the m-th row in the parity check matrix is expressed as n=0, a column number of the next "1" of the m-th row is expressed as n=1, and thereafter, the column numbers are expressed as n=2, 3, ..., at each "1". That is, conventionally, when the absolute column number of "1" in the parity check matrix is "32768", the number of bits necessary to express the column number is 15 bits. On the other hand, according to the present embodiment, when the row weight is eight, the memory size can be reduced to three bits which can express 0 to 7. When the row weight is 16, the memory size can be reduced to four bits which can express 0 to 15.
As described above, according to the present embodiment, the LDPC decoding is performed to minimize the absolute value |β_mn| of the LLR for the row processing, to the minimum k value in row unit by the cyclic structure. Therefore, the memory capacity required to store the absolute values can be substantially reduced. When the row weight is 20 and also k=3, for example, the required memory capacity can be reduced to 3/20 of the conventional capacity. Further, by changing the column number from the absolute column number (1, 3, 10, 15 ...) to the relative column number (0, 1, 2, 3 ...), the required memory capacity can be further reduced.
In the "Cyclic approximated min algorithm" according to the present embodiment, calculation and updating of probability information (LLR) by the row processing and column processing are performed cyclically for each one bit. Accordingly, probability propagation can be performed more efficiently than that according to the conventional "Min-Sum algorithm".
For example, Fig. 11 and Fig. 12 depict results of a comparison simulation between the "Cyclic approximated min algorithm" and the "Min-Sum algorithm". An LDPC code has a maximum row weight of 8 in the irregular EG code. In Fig. 11, the number of decoding iterations is fixed to 100 times, and the number of minimum values stored in the "Cyclic approximated min algorithm" is changed to 3, 4, 5, and the performance is compared with that of the "Cyclic approximated min algorithm". In Fig. 11, CyclicXmin is the "Cyclic approximated min algorithm" holding the minimum X value, and Min-Sum is the "Min-Sum algorithm". As is clear from Fig. 11, it can be confirmed that decoding performance is not degraded while decreasing the memory, by the "Cyclic approximated min algorithm" according to the present embodiment.
Fig. 12 depicts a result of comparing the average number of repetitions required until decoding succeeds, in the "Cyclic approximated min algorithm" and the "Min-Sum algorithm". In Fig. 12, CyclicXmin is the "Cyclic approximated min algorithm" holding the minimum X value, and Min-Sum is the "Min-Sum algorithm". As is clear from this result, probability propagation is performed efficiently in the "Cyclic approximated min algorithm", and the decoding number of repetitions can be substantially reduced. That is, according to the present embodiment, the calculations in decoding can be substantially reduced by the "Cyclic approximated min algorithm".
While, in the present embodiment, the LLR to be row processed has one value, the k number can be any number equal to or higher than two values. The present embodiment explains, by way of example and without limitation, that the row processing and the column processing are performed one time alternately, and the updating of the probability information (LLR) by the row processing and the column processing is cyclically performed each one bit. Alternatively, after the row processing is performed a plurality of times, the column processing can be performed by a plurality of times. That is, calculation and updating of probability information (LLR) by the row processing and the column processing can be performed cyclically for a plurality of bits each time.

Second Embodiment

A receiving device and a decoding method according to a second embodiment are explained next. LDPC decoding according to the present embodiment can be applied when the calculation and updating of the probability information (LLR) by the row processing and column processing are performed for each one bit or a predetermined plurality of bits. For example, the number of repetitions can be reduced by parallelizing calculations. In the present embodiment, the "Cyclic approximated min algorithm" is executed using what is called "Overlapped" B_mn ^c and S_m, by arranging such that the B_mn(i) and S_m of the intermediate-result retaining unit are one set regardless of the number of parallelization, and parallelized all processing units update the same B_mn ^c and S_m. The decoding algorithm according to the present embodiment is hereinafter called the "Overlapped cyclic approximated min algorithm".
The "Overlapped cyclic approximated min algorithm" executed by the receiving device according to the present embodiment is shown below.

(Initialization step)

First, the number of repetitions l=1 and the maximum number of repetitions l_max are set. Further, a reception LLR:λ_n is input, and B_mn(i) ^c is obtained as given by the following Equation (12), assuming an LLR of the minimum k value of the m-th row at the initial time is β_mn(i) ⁽⁰⁾. As a sign of the LLR:β_mn ⁽⁰⁾ in the m-th row at the initial time, sgn(λn) is input, and Sm is obtained as shown by the following Equation (12):
$\begin{array}{l} [Expression 9] \\ \begin{array}{l} B_{mnʹ}^{C} & = |β_{mn (i)}^{(0)}| = \min_{n \in N (m) \ \{n\} \{(1), n (2), \dots, n (i - 1)\}} [|λ_{n}|], \forall i \in [1 k] \\ S_{m} & = \prod_{n \in N (m)} sgn (λ_{n}) \\ n (i) & = \arg \min_{n \in N (m) \ \{n\} \{(1), n (2), \dots, n (i - 1)\}} [|λ_{n}|] \\ n \\ (0) & = φ \end{array} \end{array}$
where B_mn(i) ^c is an absolute value of the LLR:β_mn(i) of the minimum k value of the m-th row and is used in common in the parallel processing, and n(i) is a column number of the minimum i-th LLR in B_mn(i) ^c.

(Row processing step)

In the present embodiment, a starting column of each row processing is arbitrary. At the stage where the processing ends up to the final column, decoding is performed again cyclically from the first column. As the row processing, the repetition first-time LLR: α_mn ⁽¹⁾ of the bit n to be sent from the check node m to the bit node n is updated for 0≤g≤G-1, g·N_G+1≤n≤(g+1)·N_G, and for each m, where G is a parallel number, N_G is a column number that each parallelized decoding circuit processes, and G·N_g=N, by the following Equation (13):
$\begin{array}{l} [Expression 10] \\ \begin{array}{l} α_{mn}^{(1)} & = \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ < g \cdot N_{G} \end{array}} sgn (β_{mnʹ}^{(1)}) \cdot \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ > g \cdot N_{G} \end{array}} sgn (β_{mnʹ}^{(l - 1)}) \cdot \min_{nʹ \in N_{k} (m) \ n} [B_{mnʹ}^{C}] \\ = S_{m} \cdot sgn (β_{mnʹ}^{(l - 1)}) \cdot \min_{nʹ \in N_{k} (m) \ n} ⌊ B_{mnʹ}^{C} ⌋ \\ = S_{m}^{ʹ} \cdot \min_{nʹ \in N_{k} (m) \ n} [B_{mnʹ}^{C}] \\ S_{m}^{ʹ} & = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \end{array} \end{array}$
Specifically, for example, G row processing units allocated to the G columns, into which the column is divided for each column number: N_G, perform the row processing in parallel. The G row processing units execute the parallel processing, and perform the same operation as that of the "Cyclic approximated min algorithm", except that all the processing units use the same B_mn ^c.

(Column processing step)

Next, as the column processing, the repetition first-time LLR:β_mn ⁽¹⁾ of the bit n to be sent from the bit node n to the check node m is updated for 0≤g≤G-1, g·N_G+1≤n≤(g+1)·N_G, and for each m by the following Equation (14). That is, in the present embodiment, after the row processing is performed in parallel as described above, for respective columns are performed in parallel the column processing represented by the following Equation (14):
$\begin{array}{l} [Expression 11] \\ \begin{array}{l} β_{mn}^{(1)} & = λ_{n} + \sum_{mʹ \in M (n) \ m} α_{mʹn}^{(1)} \\ S_{m} & = S_{m}^{ʹ} \cdot sgn (β_{mn}^{(1)}) \\ n (i) & = \arg \min_{nʹ \in N_{k} (m) \ \{n\} \{(1), n (2), \dots, n (i - 1) n (i)\}} [B_{mnʹ}^{C}, |β_{m}^{(1)}|] \\ B_{mn (i)}^{C} & = \min_{nʹ \in N_{k} (m) \ \{n\} \{(1), n (2), \dots, n (i - 1) n (i)\}} [B_{mnʹ}^{C}, |β_{m}^{(1)}|], \forall i \in [1 k] \end{array} \end{array}$
To perform a hard decision for each n, the repetition first-time posterior value β_n ⁽¹⁾ of the bit n is updated by the following Equation (15):
$\begin{matrix} [Expression 12] \\ β_{n}^{(1)} = λ_{n} + \sum_{mʹ \in M (n)} α_{n}^{(1)} \end{matrix}$
The stop regulation is the same as that of the "Cyclic approximated min algorithm" described above.
Described below is a configuration and operation of the LDPC decoder 5 according to the second embodiment that achieves the above "Overlapped cyclic approximated min algorithm".
Fig. 13 is a configuration example of the LDPC decoder 5 according to the present embodiment. The LDPC decoder 5 includes the reception-LLR calculating unit 11 that calculates the reception LLR from the reception information, and a decoding core unit 12a that performs decoding of the present embodiment. The decoding core unit 12a includes an intermediate-result retaining unit 21a including a memory which stores therein an intermediate result (intermediate value) of decoding, row processing units 22-1 to 22-G that perform row processing (parallel processing) according to the present embodiment, column processing units 23-1 to 23-G that perform column processing (parallel processing) of the present embodiment, the decoding-result determining unit 24 that performs a hard decision of a posterior value in the column processing and an error determination of a parity check result, as a stop regulation according to the present embodiment, and a controller 25a that performs a repetition control of decoding.
In Fig. 13, the LDPC decoder 5 of the present embodiment uses in common B_mn ^c and S_m retained by the intermediate-result retaining unit 21a following Equations (12), (13), and (14), when respective row processing units and respective column processing units perform processing in parallel, thereby updating B_mn ^c and S_m, respectively. With this parallel processing, B_mn ^c and S_m are rapidly updated according to the parallel number, which substantially reduces the number of decoding iterations.
According to the present embodiment, in the parallel processing, when calculation of the same row occurs in the same clock and when the same buffer is referenced, various measures are taken, such as a memory access priority order is set to each processing unit, a memory bank is partitioned, and the timing of the memory access is adjusted using a shift register.
As described above, in the "Overlapped cyclic approximated min algorithm" according to the present embodiment, the row processing and the column processing are performed in parallel using the "Cyclic approximated min algorithm" described above. Further, the intermediate-result retaining unit that retains the minimum k value updated in each column processing performed in parallel is shared, and the minimum k value is updated in each column processing performed in parallel. With this arrangement, the number of decoding iterations can be substantially reduced as compared with the decrease according to the "Min-Sum algorithm" and the first embodiment described above.
Fig. 14 depicts a performance comparison regarding the number of repetitions. Specifically, the repetition performance of the "Overlapped cyclic approximated min algorithm" is compared with the repetition performance of the "Cyclic approximated min algorithm", and the "Min-Sum algorithm", respectively when the parallel number is 2, in the state that the number of decoding iterations is fixed. In Fig. 14, when the number of decoding iterations is limited to a small number, it can be confirmed that the decoding performance of the "Cyclic approximated min algorithm" is higher than the decoding performance of the conventional method of the "Min-Sum algorithm", and that the "Overlapped cyclic approximated min algorithm" has the decoding performance of the same level of the decoding performance by about the half number of decoding iterations of the "Cyclic approximated min algorithm". In Fig. 14, the number of decoding iterations is about a half because the parallel number is 2. When the "Overlapped cyclic approximated min algorithm" is used, the number of repetitions becomes "1/parallel number" of the "Cyclic approximated min algorithm".

Third Embodiment

A receiving device and a decoding method according to a third embodiment are explained below. In the present embodiment, the process of updating only the absolute value of the LLR of the minimum k value and the decoding using the approximate minimum value in the "Cyclic approximated min algorithm" according to the first embodiment or the "Overlapped cyclic approximated min algorithm" according to the second embodiment are cyclically applied to the "Normalized BP-based algorithm" as the known decoding algorithm using the "Min-Sum algorithm".
Before explaining the decoding algorithm of the present embodiment, the known "Normalized BP-based algorithm" that is the basis the decoding algorithm is shown below. The row processing different from that of the "Min-Sum algorithm" is explained.

(Row processing step)

The row processing of the above "Normalized BP-based algorithm" can be generalized by the following Equation (16). In this case, as the row processing, the repetition first-time LLR:α_mn ⁽¹⁾ is updated for each of m and n by the following Equation (16), where A is a constant called a normalization factor. In the "Normalized BP-based algorithm", the repetition first-time LLR obtained by the "Min-Sum algorithm" is corrected by the normalization factor A.
$\begin{array}{l} [Expression 13] \\ \begin{array}{l} α_{mn}^{(1)} & = 2 \tanh^{-1} (\prod_{nʹ \in N (m) \ n} \tanh (\frac{β_{mnʹ}^{(l - 1)}}{2})) \\ = 2 \tanh^{-1} (\prod_{nʹ \in N (m) \ n} sgn (β_{mnʹ}^{(l - 1)}) \cdot \prod_{nʹ \in N (m) \ n} \tanh (\frac{β_{mnʹ}^{(l - 1)}}{2})) \\ = \prod_{nʹ \in N (m) \ n} sgn (β_{mnʹ}^{(l - 1)}) \cdot 2 \tanh^{-1} (\prod_{nʹ \in N (m) \ n} \tanh (\frac{β_{mnʹ}^{(l - 1)}}{2})) \\ \approx \frac{1}{A} \prod_{nʹ \in N (m) \ n} sgn (β_{mnʹ}^{(l - 1)}) \cdot \min_{nʹ \in N (m) \ n} |β_{mnʹ}^{(l - 1)}| \end{array} \end{array}$
The decoding algorithm when the "Cyclic approximated min algorithm" or the "Overlapped cyclic approximated min algorithm" is applied to the "Normalized BP-based algorithm" is explained below. In the following, explanations are omitted for the processing (initialization, column processing, and stop regulation) similar to that of the "Cyclic approximated min algorithm" or the "Overlapped cyclic approximated min algorithm". The row processing different from that of the "Cyclic approximated min algorithm" or the "Overlapped cyclic approximated min algorithm" is explained below.

(Row processing step using Cyclic approximated min algorithm)

In the present embodiment, a starting column of the row processing is arbitrary. At the stage where the processing ends to the last column, decoding is performed again cyclically from the first column. The row processing of the decoding algorithm according to the present embodiment using the "Cyclic approximated min algorithm" can be generalized by the following Equation (17). In this case, as the row processing, the repetition first-time LLR: α_mn ⁽¹⁾ is updated for each of m and n by the following Equation (17). That is, the repetition first-time LLR obtained by the "Cyclic approximated min algorithm" is corrected by the normalization factor A in the following Equation (17):
$\begin{array}{l} [Expression 14] \\ α_{mn}^{(1)} & = \frac{1}{A} \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ < n \end{array}} sgn (β_{mnʹ}^{(l - 1)}) \cdot \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ > n \end{array}} sgn (β_{mnʹ}^{(l - 1)}) \cdot \min_{nʹ \in N_{k} (m) \ n} [B_{mnʹ}] \\ = \frac{1}{A} S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \min_{nʹ \in N_{k} (m) \ n} [B_{mnʹ}] \\ = \frac{1}{A} S_{m}^{ʹ} \cdot \min_{nʹ \in N_{k} (m) \ n} [B_{mnʹ}] . \end{array}$

(Row processing step using Overlapped cyclic approximated min algorithm)

The row processing of the decoding algorithm according to the present embodiment using the "Overlapped cyclic approximated min algorithm" can be generalized by the following Equation (18). In this case, as the row processing, the repetition first-time LLR:α_mn ⁽¹⁾ is updated for 0≤g≤G-1, g·N_G+1≤n≤(g+1)·N_G, and for each m by the following Equation (18). That is, the repetition first-time LLR obtained by the "Overlapped cyclic approximated min algorithm" is corrected by the normalization factor A in the following Equation (18):
$\begin{array}{l} [Expression 15] \\ \begin{array}{l} α_{mn}^{(1)} & = \frac{1}{A} \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ < g \cdot N_{G} \end{array}} sgn (β_{mnʹ}^{(l)}) \cdot \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ > g \cdot N_{G} \end{array}} sgn (β_{mnʹ}^{(l - 1)}) \cdot \min_{nʹ \in N_{k} (m) \ n} [{B^{C}}_{mnʹ}] \\ = \frac{1}{A} S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \min_{nʹ \in N_{k} (m) \ n} [{B^{C}}_{mnʹ}] \\ = \frac{1}{A} S_{m}^{ʹ} \cdot \min_{nʹ \in N_{k} (m) \ n} [{B^{C}}_{mnʹ}] \end{array} \end{array}$
In the decoding algorithm according to the present embodiment, after the row processing step is performed as described above, processing based on the column processing and the stop regulation similar to those of the "Cyclic approximated min algorithm" or the "Overlapped cyclic approximated min algorithm" is performed to obtain the final code result.
Characteristic operations of the row processing unit of the LDPC decoder 5 that executes the decoding algorithm of the present embodiment are explained below with reference to the drawings. The entire configuration of the LDPC decoder 5 is similar to that shown in Fig. 5 or Fig. 13.
Fig. 15 is a configuration example of row processing units 22, 22-1 to 22-G that perform row processing of the present embodiment. The row processing unit includes a minimum-value selecting unit 31a. Configurations similar to those explained with reference to Fig. 6 are denoted by like reference numerals, and explanations thereof are not repeated. The minimum value selecting unit 31a according to the present embodiment corrects the minimum value (Min1LLR or Min2LLR) of the LLR read from the intermediate-result retaining unit 21 (or 21a), using the normalization factor A, for example. Specifically, the minimum value selecting unit 31a performs the normalization by dividing the LLR minimum value by A.
As described above, according to the present embodiment, the "Cyclic approximated min algorithm" or the "Overlapped cyclic approximated min algorithm" is applied to the "Normalized BP-based algorithm" having the better performance than that of the "Min-Sum algorithm". With this arrangement, effects similar to those of the first and second embodiments can be obtained. Further, performance close to that of the "Sum-Product algorithm" can be achieved, regardless of the circuit amount substantially equivalent to that of the "Min-Sum algorithm".
In the present embodiment, the "Cyclic approximated min algorithm" or the "Overlapped cyclic approximated min algorithm" is applied to the "Normalized BP-based algorithm". Alternatively, the "Cyclic approximated min algorithm" or the "Overlapped cyclic approximated min algorithm" can also be applied to the known "Offset BP-based algorithm" or other algorithm. In this case also, effects similar to those described above can be obtained.

Fourth Embodiment

A receiving device and a decoding method according to a fourth embodiment are explained below. In the present embodiment, the process of updating only the absolute value of the LLR of the minimum k value and the decoding using the approximate minimum value in the "Cyclic approximated min algorithm" according to the first embodiment or the "Overlapped cyclic approximated min algorithm" according to the second embodiment are cyclically applied to the "δ min algorithm" as the known decoding algorithm having superior correction performance of LLR:β_mn to that of the "Normalized BP-based algorithm" or the "Offset BP-based algorithm".
Before explaining the decoding algorithm of the present embodiment, the known "δ min algorithm" that is the basis of the decoding algorithm is explained. The row processing different from that of the "Min-Sum algorithm" is explained below.

(Row processing step)

The row processing of the above "δ min algorithm" can be generalized by the following Equation (19). In this case, as the row processing, the repetition first-time LLR:α_mn ⁽¹⁾ is updated for each of m and n by the following Equation (19). In the row processing of the "δ min algorithm", α_mn ⁽¹⁾ is calculated by calculating Θ from the absolute value: |β_mn' ^(i-1)| of the LLR updated at the repetition 1-1-th time.
$\begin{array}{l} [Expression 16] \\ \begin{array}{l} α_{m, n}^{(i)} = \prod_{nʹ \in N (m) \ n} sgn (β_{mnʹ}^{(i - 1)}) \cdot \underset{nʹ \in N (m) \ n}{Θ} [|β_{m, nʹ}^{(i - 1)}|] \\ \underset{n \in A}{Θ} (I_{n}) \equiv I_{1} Θ I_{2} \dots Θ I_{|A|} \\ aΘb \equiv \max (\min (a b) - Δ, 0) \\ Δ \equiv \max (0.9 - |a - b| / 2, 0) \end{array} \end{array}$
The decoding algorithm when the "Cyclic approximated min algorithm" or the "Overlapped cyclic approximated min algorithm" is applied to the "δ min algorithm" is explained below. In the following, explanations are omitted for the processing (initialization, column processing, and stop regulation) similar to that of the "Cyclic approximated min algorithm" or the "Overlapped cyclic approximated min algorithm". The row processing different from that of the "Cyclic approximated min algorithm" or the "Overlapped cyclic approximated min algorithm" is explained below. In the present embodiment, a starting column of the row processing is arbitrary. At the stage where the processing ends to the last column, decoding is performed again cyclically from the first column.

(Row processing step using Cyclic approximated min algorithm)

For example, the row processing of the decoding algorithm according to the present embodiment using the "Cyclic approximated min algorithm" can be generalized by the following Equation (20). In this case, as the row processing, the repetition first-time LLR:α_mn ⁽¹⁾ is updated for 1≤n≤N and for each m by the following Equation (20). In the row processing of the decoding algorithm, α_mn ⁽¹⁾ is calculated by calculating Θ from the absolute value:B_mn' of the LLR of the minimum k value updated at the repetition l-1-th time.
$\begin{array}{l} [Expression 17] \\ \begin{array}{l} α_{mn}^{(1)} & = \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ < n \end{array}} sgn (β_{mnʹ}^{(l)}) \cdot \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ > n \end{array}} sgn (β_{mnʹ}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{Θ} [B_{mnʹ}] \\ = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{Θ} [B_{mnʹ}] \\ = S_{m}^{ʹ} \cdot \underset{nʹ \in N_{k} (m) \ n}{Θ} [B_{mnʹ}] \end{array} \end{array}$

(Row processing step using Overlapped cyclic approximated min algorithm)

The row processing of the decoding algorithm according to the present embodiment using the "Overlapped cyclic approximated min algorithm" can be generalized by the following Equation (21). In this case, as the row processing, the repetition first-time LLR: α_mn ⁽¹⁾ is updated for 0≤g≤G-1, g·N_G+1≤n≤(g+1)·N_G, and for each m by the following Equation (21). In the row processing of this decoding algorithm, α_mn ⁽¹⁾ is calculated by calculating Θ from the absolute value:B_mn' ^c of the LLR of the minimum k value updated by the parallel processing at the repetition l-1-th time.
$\begin{array}{l} [Expression 18] \\ \begin{array}{l} α_{mn}^{(1)} & = \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ < g \cdot N_{G} \end{array}} sgn (β_{mnʹ}^{(l)}) \cdot \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ > g \cdot N_{G} \end{array}} sgn (β_{mnʹ}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{Θ} ⌊ B_{mnʹ}^{C} ⌋ \\ = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{Θ} [B_{mnʹ}^{C}] \\ = S_{m}^{ʹ} \cdot \underset{nʹ \in N_{k} (m) \ n}{Θ} [B_{mnʹ}^{C}] \end{array} \end{array}$
In the decoding algorithm according to the present embodiment, after the row processing step is performed as described above, processing based on the column processing and the stop regulation similar to those of the "Cyclic approximated min algorithm" or the "Overlapped cyclic approximated min algorithm" is performed to obtain the final code result.
Characteristic operations of the row processing unit of the LDPC decoder 5 that executes the decoding algorithm of the present embodiment are explained below with reference to the drawings. The entire configuration of the LDPC decoder 5 is similar to that shown in Fig. 5 or Fig. 13.
Fig. 16 is a configuration example of the row processing units 22, 22-1 to 22-G that perform row processing of the present embodiment. Constituent elements similar to those described with reference to Fig. 6 are denoted by like reference numerals, and explanations thereof are not repeated. While the LDPC decoder 5 shown in Fig. 5 is explained as one example, the present embodiment can also be similarly applied to the LDPC decoder 5 shown in Fig. 13.
A minimum-value selecting unit 31b according to the present embodiment reads the Min1LLR(B_mn(1)), Min2LLR(B_mn(2)), MinkLLR(B_mnt(k)), and their column numbers from the intermediate-result retaining unit 21, and the calculating unit performs the Θ calculation. That is, in the minimum-value selecting unit 31b according to the present embodiment, the calculating unit performs the following calculation in the "δ min algorithm", to B_mn(k) in which the n-th column to be processed does not coincide with the column number n(k) of B_mn(k) retained in the intermediate-result retaining unit 21.
For example, the calculating unit obtains the updated value |α_mn ⁽¹⁾| (=Θ [(B_mn']) excluding the sign as represented by the following Equation (22):
$\begin{array}{l} [Expression 19] \\ \underset{nʹ \in N_{k} (m) \ n}{Θ} [B_{mnʹ}] \end{array}$
Further, by limiting the LLR to be calculated from the k value to the minimum 3 values, calculations can be reduced. The calculating unit obtains the updated value |α_mn ⁽¹⁾ |(=Θ[(B_mn']) excluding the sign as represented by the following Equation (23):
$\begin{array}{l} [\begin{matrix} Expression 20 \end{matrix}] \\ \begin{array}{l} if (n = n_{(1)}) \underset{nʹ \in N_{k} (m) \ n}{Θ} [B_{mnʹ}] = B_{{mn}_{(2)}} Θ B_{mn}_{(3)} \\ else if (n = n_{(2)}) \underset{nʹ \in N_{k} (m) \ n}{Θ} [B_{mnʹ}] = B_{{mn}_{(1)}} Θ B_{mn}_{(3)} \\ else \underset{nʹ \in N_{k} (m) \ n}{Θ} [B_{mnʹ}] = B_{{mn}_{(1)}} Θ B_{mn}_{(2)} \end{array} \end{array}$
While the LLR to be calculated is limited from the k value to the minimum 3 values in the above example, the embodiment can also be applied to the case that the LLR is limited to the minimum 4, 5, ... values.
As described above, according to the present embodiment, the "Cyclic approximated min algorithm" or the "Overlapped cyclic approximated min algorithm" is applied to the "δ min algorithm" having the better performance than that of the "Min-Sum algorithm". With this arrangement, effects similar to those of the first and second embodiments can be obtained. Further, performance close to that of the "Sum-Product algorithm" can be achieved, regardless of the circuit amount substantially equivalent to that of the "Min-Sum algorithm". In the present embodiment, description is made for the case that the minimum value of the absolute values of the LLR for the row processing is corrected to the optimum value based on a predetermined correction equation prescribed by the known "δ min algorithm". However, the correction equation is not limited to this, and the correction equation prescribed by the algorithm other than the "δ min algorithm" can also be used. In this case also, effects similar to those described above can be obtained.
Fig. 17 depicts a result of comparison between a decoding algorithm having the "Cyclic approximated min algorithm" or the "Overlapped cyclic approximated min algorithm" applied to the "δ min algorithm" and the "Sum-Product algorithm". For example, overlap5delta10 is a decoding algorithm (parallel number: 2, minimum 5 values, l=10) according to the present embodiment using the "Overlapped cyclic approximated min algorithm", and Cyclic5delta50 is a decoding algorithm (without parallel, minimum 5 values, 1=50) according to the present embodiment using the "Cyclic approximated min algorithm". Sum-Product100 is the "Sum-Product algorithm" (l=100). These are substantially overlapped. From this result, by applying the "Cyclic approximated min algorithm" or the "Overlapped cyclic approximated min algorithm" to the "δ min algorithm", performance approximately the same as that of the "Sum-Product algorithm" can be obtained. Further, the number of decoding iterations can also be substantially reduced.

Fifth Embodiment

A receiving device and a decoding method according to a fifth embodiment are explained below. In the present embodiment, the process of updating only the absolute value of the LLR of the minimum k value and the decoding using the approximate minimum value in the "Cyclic approximated min algorithm" according to the first embodiment or the "Overlapped cyclic approximated min algorithm" according to the second embodiment are cyclically applied to the "Sum-Product algorithm".
Before explaining the decoding algorithm of the present embodiment, the known "Sum-Product algorithm" that is the basis of the decoding algorithm is explained. In the present embodiment, a method of calculation by tabling the mathematical function, i.e., a general "Sum-Product algorithm" using a TLU (table lookup), is described. The row processing different from that of the "Sum-Product algorithm" explained in the conventional technology is described.

(Row processing step (1))

The row processing of the "Sum-Product algorithm" using the TLU can be generalized by the following Equation (24). In this case, as the row processing, the repetition first-time LLR: α_mn ⁽¹⁾ is updated for each of m and n by the following Equation (24). In the row processing of the "Sum-Product algorithm" using the TLU, a calculation using the TLU is performed to the absolute value: |β_mn' ^(l-1)| of the LLR updated at the repetition 1-1-th time.
$\begin{array}{l} [\begin{matrix} Expression 21 \end{matrix}] \\ \begin{array}{l} α_{m, n}^{(i)} = \prod_{nʹ \in N (m) \ n} sgn (β_{mnʹ}^{(i - 1)}) \cdot \underset{nʹ \in N (m) \ n}{TLU} [|β_{m, nʹ}^{(i - 1)}|] \\ \underset{n \in A}{TLU} (I_{n}) \equiv TLU (I_{1}, TLU (I_{2}, \dots TLU (I_{|A| - 1} I_{|A|}))) \\ TLU (a b) \equiv 2 \tanh^{-1} (\tanh \frac{a}{2} \cdot \tanh b \frac{}{2}) \end{array} \end{array}$

(Row processing step (2))

The row processing of the "Sum-Product algorithm" using the TLU can also be achieved by the method different from the above method. For example, the row processing of the "Sum-Product algorithm" using the TLU different from the above method can be generalized by the following Equation (25). In this case, as the row processing, the repetition first-time LLR:α_mn ⁽¹⁾ is updated for each of m and n by the following Equation (25):
$\begin{array}{l} [\begin{matrix} Expression 22 \end{matrix}] \\ \begin{array}{l} α_{m, n}^{(i)} = \prod_{nʹ \in N (m) \ n} sgn (β_{mnʹ}^{(i - 1)}) \cdot \underset{nʹ \in N (m) \ n}{Ξ} [|β_{m, nʹ}^{(i - 1)}|] \\ \underset{n \in A}{Ξ} (I_{n}) \equiv I_{1} Ξ I_{2} Θ \dots Ξ I_{|A|} \\ aΞb \equiv \min (a b) + TLU 1 (|a + b|) - TLU 1 (|a - b|) \end{array} \end{array}$
For the TLU1(x), a table is prepared in advance based on the following Equation (26): $TLU 1 (x) = in (1 + \exp (- x))$
In the "Sum-Product algorithm" using the TLU, the row processing represented by Equation (24) has a characteristic that while the table becomes large, the number of calculations is small. On the other hand, the row processing represented by Equation (25) has a characteristic that the number of calculations is large although the table becomes small.
The decoding algorithm when the "Cyclic approximated min algorithm" is applied to the "Sum-Product algorithm" using the TLU is explained below. In the following, explanations are omitted for the processing (initialization, column processing, and stop regulation) similar to that of the "Cyclic approximated min algorithm". The row processing different from that of the "Cyclic approximated min algorithm" is explained below. In the present embodiment, a starting column of the row processing is arbitrary, and at the stage where the processing ends up to the final column, decoding is performed again cyclically from the first column.

(Row processing step using Cyclic approximated min algorithm (1))

The row processing of the decoding algorithm according to the present embodiment having the "Cyclic approximated min algorithm" applied to the above row processing step (1) can be generalized by the following Equation (27). In this case, as the row processing, the repetition first-time LLR:α_mn ⁽¹⁾ is updated for 1≤n≤N and for each m by the following Equation (27). In the row processing of the decoding algorithm, a calculation using the TLU is performed to the absolute value: B_mn' of the LLR of the minimum k value updated at the repetition 1-1-th time.
$\begin{array}{l} [Expression 23] \\ \begin{array}{l} α_{mn}^{(1)} & = \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ < n \end{array}} sgn (β_{mnʹ}^{(l)}) \cdot \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ > n \end{array}} sgn (β_{mnʹ}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{TLU} [B_{mnʹ}] \\ = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{TLU} [B_{mnʹ}] \\ = S_{m}^{ʹ} \cdot \underset{nʹ \in N_{k} (m) \ n}{TLU} [B_{mnʹ}] \end{array} \end{array}$

(Row processing step using Cyclic approximated min algorithm (2))

The row processing of the decoding algorithm according to the present embodiment having the "Cyclic approximated min algorithm" applied to the above row processing step (2) can be generalized by the following Equation (28). In this case, as the row processing, the repetition first-time LLR:α_mn ⁽¹⁾ is updated for 1≤n≤N and for each m by the following Equation (28):
$\begin{array}{l} [Expression 24] \\ \begin{array}{l} α_{mn}^{(1)} & = \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ < n \end{array}} sgn (β_{mnʹ}^{(l)}) \cdot \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ > n \end{array}} sgn (β_{mnʹ}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{Ξ} [B_{mnʹ}] \\ = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{Ξ} [B_{mnʹ}] \\ = S_{m}^{ʹ} \cdot \underset{nʹ \in N_{k} (m) \ n}{Ξ} [B_{mnʹ}] \end{array} \end{array}$
The decoding algorithm when the "Overlapped cyclic approximated min algorithm" is applied to the "Sum-Product algorithm" using the TLU is explained below. In the following, explanations are omitted for the processing (initialization, column processing, and stop regulation) similar to that of the "Overlapped cyclic approximated min algorithm". The row processing different from that of the "Overlapped cyclic approximated min algorithm" is explained below.

(Row processing step using Overlapped cyclic approximated min algorithm (1))

The row processing of the decoding algorithm according to the present embodiment having the "Overlapped cyclic approximated min algorithm" applied to the above row processing step (1) can be generalized by the following Equation (29). In this case, as the row processing, the repetition first-time LLR:α_mn ⁽¹⁾ is updated for 0≤g≤G-1, g·N_G+1≤n≤(g+1)·N_G, and for each m by the following Equation (29). In the row processing of this decoding algorithm, a calculation using the TLU is performed to the absolute value: B_mn' ^c of the LLR of the minimum k value updated by the parallel processing at the repetition l-1-th time.
$\begin{matrix} [Expression 25] \\ α_{mn}^{(1)} & = \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ < g \cdot N_{G} \end{array}} sgn (β_{mnʹ}^{(l)}) \cdot \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ > g \cdot N_{G} \end{array}} sgn (β_{mnʹ}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{TLU} ⌊ B_{mnʹ}^{C} ⌋ \\ = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{TLU} [B_{mnʹ}^{C}] \\ = S_{m}^{ʹ} \cdot \underset{nʹ \in N_{k} (m) \ n}{TLU} [B_{mnʹ}^{C}] \end{matrix}$

(Row processing step using Overlapped cyclic approximated min algorithm (2))

The row processing of the decoding algorithm according to the present embodiment having the "Overlapped cyclic approximated min algorithm" applied to the above row processing step (2) can be generalized by the following Equation (30). In this case, as the row processing, the repetition first-time LLR: α_mn ⁽¹⁾ is updated for 0≤g≤G-1, g·N_G+1≤n≤(g+1)·N_G, and for each m by the following Equation (30) :
$\begin{array}{l} [Expression 26] \\ \begin{array}{l} α_{mn}^{(1)} & = \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ < g \cdot N_{G} \end{array}} sgn (β_{mnʹ}^{(l)}) \cdot \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ > g \cdot N_{G} \end{array}} sgn (β_{mnʹ}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{Ξ} ⌊ B_{mnʹ}^{C} ⌋ \\ = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{Ξ} [B_{mnʹ}^{C}] \\ = S_{m}^{ʹ} \cdot \underset{nʹ \in N_{k} (m) \ n}{Ξ} [B_{mnʹ}^{C}] \end{array} \end{array}$
Characteristic operations of the row processing unit of the LDPC decoder 5 that executes the decoding algorithm of the present embodiment are explained below with reference to the drawings. The entire configuration of the LDPC decoder 5 is similar to that shown in Fig. 5 or Fig. 13.
Fig. 18 is a configuration example of the row processing units 22, 22-1 to 22-G that perform row processing of the present embodiment. Constituent elements similar to those described with reference to Fig. 6 are denoted by like reference numerals, and explanations thereof are not repeated. While the LDPC decoder 5 shown in Fig. 5 is explained as one example, the present embodiment can also be similarly applied to the LDPC decoder 5 shown in Fig. 13.
A minimum-value selecting unit 31c according to the present embodiment reads the Min1LLR(B_mn(1)), Min2LLR(B_mn(2)), MinkLLR(B_mn(k)), and their column numbers from the intermediate-result retaining unit 21, and the calculating unit performs calculation using the TLU. That is, in the minimum-value selecting unit 31c according to the present embodiment, the calculating unit performs the following calculation in the "Sum-Product min algorithm", to B_mn(k) in which the n-th column to be processed does not coincide with the column number n(k) of B_mn(k) retained in the intermediate-result retaining unit 21.
For example, the calculating unit obtains the updated value excluding the sign as represented by the following Equation (31):
$\begin{array}{l} [Expression 27] \\ \underset{nʹ \in N_{k} (m) \ n}{TLU} [B_{mnʹ}] OR \underset{nʹ \in N_{k} (m) \ n}{Ξ} [B_{mnʹ}] \end{array}$
Further, by limiting the LLR to be calculated from the k value to the minimum 3 values, calculations can be reduced. The calculating unit obtains the updated value excluding the sign as represented by the following Equation (32) :
$\begin{array}{l} [Expression 28] \\ if (n = n_{(1)}) \underset{nʹ \in N_{k} (m) \ n}{TLU} [B_{mnʹ}] = TLU (B_{mn}) (_{(2)} B_{{mn}_{(3)}}) OR \underset{nʹ \in N_{k} (m) \ n}{Ξ} [B_{mnʹ}] = B_{{mn}_{(2)}} Ξ B_{mn}_{(3)} \\ else if (n = n_{(2)}) \underset{nʹ \in N_{k} (m) \ n}{TLU} [B_{mnʹ}] = TLU (B_{mn}) (_{(1)} B_{{mn}_{(3)}}) OR \underset{nʹ \in N_{k} (m) \ n}{Ξ} [B_{mnʹ}] = B_{{mn}_{(1)}} Ξ B_{mn}_{(3)} \\ else \underset{nʹ \in N_{k} (m) \ n}{TLU} [B_{mnʹ}] = TLU (B_{mn}) (_{(1)} B_{{mn}_{(2)}}) OR \underset{nʹ \in N_{k} (m) \ n}{Ξ} [B_{mnʹ}] = B_{{mn}_{(1)}} Ξ B_{mn}_{(2)} \end{array}$
While the LLR to be calculated is limited from the k value to the minimum 3 values in the above explanation as an example, the embodiment can also be applied to the case that the LLR is limited to the minimum 4, 5, ... values.
As described above, according to the present embodiment, the "Cyclic approximated min algorithm" or the "Overlapped cyclic approximated min algorithm" is applied to the "Sum-Product algorithm" using the TLU. With this arrangement, although calculations and the required memory capacity increase as compared with other embodiments, decoding performance can be improved. While the "Sum-Product algorithm" using the TLU is explained in the present embodiment, the principle can be similarly applied to other decoding algorithm for performing the TLU to the mathematical function. In the present embodiment, the TLU prescribed by the known "Sum-Product algorithm" is used for the minimum value of the absolute values of the LLR for the row processing. However, the TLU is not limited to the above, and the TLU other than the TLU prescribed by the "Sum-Product algorithm" can also be used. In this case also, effects similar to the above effects can be obtained.

Sixth Embodiment

A communication apparatus and a decoding method according to a sixth embodiment are explained below. According to the present embodiment, the number of repetitions can be further reduced by relating the decoding to a serial decoding in a complete bit unit.
As in the above embodiment, Fig. 5-1 depicts a configuration of the LDPC decoder 5 according to the present embodiment. The LDPC decoder 5 includes the reception-LLR calculating unit 11 that calculates the reception LLR from the reception information, and the decoding core unit 12 that performs decoding according to the present embodiment. The decoding core unit 12 includes the intermediate-result retaining unit 21 configured by a memory which stores therein an intermediate result (intermediate value) of decoding, the row processing unit 22 that performs row processing according to the present embodiment, the column processing unit 23 that performs column processing according to the present embodiment, the decoding-result determining unit 24 that performs a hard decision of a posterior value in the column processing and an error determination of a parity check result, as a stop regulation according to the present embodiment, and the controller 25 that performs a repetition control of decoding.
The decoding algorithm according to the present embodiment is a method of cyclically updating only the absolute value of the LLR of the minimum k value. Because this algorithm is the method of decoding using an approximate minimum value instead of an accurately minimum value and is the serial decoding method, this algorithm is hereinafter called the "Serial cyclic approximated min algorithm". The minimum k value represents "from the minimum value to the k-th value in the ascending order.
The "Serial cyclic approximated min algorithm" executed in the receiving device is shown below.

(Initialization step)

First, the number of repetitions l=1 and the maximum number of repetitions l_max are set. The LLR of the minimum k value of the m-th row at the initial time is set as β_mn(i) ⁽⁰⁾, and a reception LLR:λ_n is input, thereby obtaining B_mn(i) as represented by the following Equation (33). As a sign of the LLR:β_mn ⁽⁰⁾ of the m-th row at the initial time, sgn(λ_n) is input, thereby obtaining S_m as represented by the following Equation (33):
$\begin{array}{l} [Expression 29] \\ \begin{array}{l} B_{mn (i)} & = |β_{mn (i)}^{(0)}| = \min_{n \in N (m) \ \{n\} \{(1), n (2), \dots, n (i - 1)\}} [|λ_{n}|], \forall i \in [1 k] \\ S_{m} & = \prod_{n \in N (m)} sgn (λ_{n}) \\ n (i) & = \arg \min_{n \in N (m) \ \{n\} \{(1), n (2), \dots, n (i - 1)\}} [|λ_{n}|] \\ n \\ (0) & = φ \end{array} \end{array}$
where B_mn(i) is an absolute value of the LLR:B_mn(i) of the minimum k value of the m-th row, n(i) is a column number of the minimum i-th LLR in B_mn(i), and S_m is a product of signs (+ or -) of the LLR:β_mn of the m-th row.

(Row processing step 1)

In the present embodiment, a starting column of the row processing is arbitrary. At the stage where the processing ends to the last column, decoding is performed again cyclically from the first column. As the row processing, the repetition first-time LLR:α_mn ⁽¹⁾ of the bit n to be sent from the check node m to the bit node n is updated for 1≤n≤N and for each m by the following Equation (34) :
$\begin{array}{l} [Expression 30] \\ α_{mn}^{(l)} & = \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ < n \end{array}} sgn (β_{mnʹ}^{(l)}) \cdot \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ > n \end{array}} sgn (β_{mnʹ}^{(l - 1)}) \cdot \min_{nʹ \in N_{k} (m) \ n} [B_{mnʹ}] \\ = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \min_{nʹ \in N_{k} (m) \ n} [B_{mnʹ}] \\ = S_{m}^{ʹ} \cdot \min_{nʹ \in N_{k} (m) \ n} [B_{mnʹ}] \\ S_{m}^{ʹ} & = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \\ β_{n}^{(l)} & = λ_{n} + \sum_{m \in M (n) \ m} α_{mn}^{(l)} \end{array}$
Specifically, when the current column number is n, a column number that satisfies "n'<n" takes the product of signs of the LLR:β_mn' ⁽¹⁾ updated in the first-time column processing, and a column number that satisfies "n'>n" takes the product of signs of the LLR:β_mn' ^(1-1) updated in the (1-1)-th time column processing. A result of multiplying these results by the minimum LLR:min[β_mn'] in the minimum k value of the m-th row is set as the updated LLR:α_mn ⁽¹⁾ of the column number n. In the present embodiment, the term of multiplying the product of the signs of β_mn' ⁽¹⁾ by the product of the signs of β_mn' ^(l-1) is substituted by the term of multiplying S_m updated at the (1-1)-th time by the sign of β_mn' updated at the (1-1)-th time. With this arrangement, calculations and the required memory capacity can be reduced. N_k(m) in Equation (34) is the set of n(i) of the m-th row, and is expressed as N_k(m)={n(1), n(2), ..., n(k)}.

(Column processing step)

Next, as the column processing, the repetition first-time LLR:β_mn ⁽¹⁾ of the bit n to be sent from the bit node n to the check node m is updated by the following Equation (35) for each m of the column number n performed at the row processing step 1. At the subsequent column processing step and the row processing step 2, calculation is performed in order for each row starting from the one with the smallest row number, for example. However, when all rows having "1" standing are executed without overlapping, the calculation can be performed in any order.
$\begin{array}{l} [Expression 31] \\ \begin{array}{l} β_{mn}^{(l)} = λ_{n} + \sum_{mʹ \in M (n) \ m} {αʹ}_{mn}^{(l)} = β_{n}^{(l)} - α_{mn}^{(l)} \\ S_{m} = S_{m}^{ʹ} \cdot sgn (β_{mn}^{(l)}) \\ n_{i} = \arg \min_{nʹ \in N_{k} (m) \ \{n\} \{_{1} n_{2} \dots n_{i - 1} n_{i} n\}} [B_{mnʹ}, |β_{mn}^{(l)}|], \\ B_{{mn}_{i}} = \min_{nʹ \in N_{k} (m) \ \{n\} \{_{1} n_{2} \dots n_{i - 1} n_{i} n\}} [mnʹ, |β_{mn}^{(l)}|], \forall i \in [1 k] \end{array} \end{array}$
Specifically, in the column number n, a result of the addition of the reception LLR:λ_n and a total value of the LLR:α_m'n ⁽¹⁾ other than the m-th row LLR updated in the first-time row processing is expressed as the updated LLR:β_mn' ⁽¹⁾. This calculation can also be obtained by subtracting α_m'n ⁽¹⁾ from β_n ⁽¹⁾. The above S_m' is multiplied by the sign (+ or -) of β_m ⁽¹⁾ updated in the first-time column processing, thereby updating S_m to be used in the row processing. The two equations in Equation (35) prescribe the sort process (minimum k value) of B_mn(1).

(Row processing step 2)

Next, as the row processing again, the repetition first-time LLR: α'_mn ⁽¹⁾ of the bit n to be sent from the check node m to the bit node n is updated, for the same m executed in the column processing of the column number n, by the following Equation (36):
$\begin{array}{l} [Expression 32] \\ {αʹ}_{mn}^{(l)} & = S_{m} \cdot sgn (β_{mn}^{(l)}) \cdot \min_{nʹ \in N_{k} (m) \ n} [B_{mnʹ}] \\ S_{m}^{ʹ} & = S_{m} \cdot sgn (β_{mn}^{(l)}) \\ β_{n}^{(l)} & = β_{mn}^{(l)} + {αʹ}_{mn}^{(l)} \end{array}$
Specifically, as the row processing again, α'_mn ⁽¹⁾ is updated. The updated α'_mn ⁽¹⁾ is added to β_mn ⁽¹⁾ using the updated result, thereby updating β_n ⁽¹⁾. Thereafter, by returning to the column processing step, calculation is repeated until when the calculation is completed for all m of the column number n. When the processes at the column processing step and the row processing step end for all rows m having "1" standing in the check matrix of the column number n, the process control moves to the stop regulation.

(Stop regulation)

Thereafter, when the repetition first-time posterior value β_n ⁽¹⁾ of the bit n is "β_n ⁽¹⁾>0", for example, a decoding result is "x_n'=1" (where x' corresponds to the original transmission signal x). On the other hand, when "β_n ⁽¹⁾≤0", a decoding result is "x_n'=0", and a decoding result x'= (x₁', x₂', ..., X_N') is obtained.
When the result of parity check is "Hx'=0" or when the number of repetitions is "l=1_max" (when any one of these condition is satisfied), a decoding result x' in this case is output. When none of the two conditions is satisfied, "1=1+1" is set, and the process control returns to the above row processing step 1. Thereafter, the calculation is sequentially performed.
A characteristic operation of the LDPC decoder 5 that executes the above "Serial cyclic approximated min algorithm" is explained in detail with reference to a configuration diagram.
As in the above embodiment, Fig. 6 is a configuration example of the row processing unit 22 that performs row processing according to the "Serial cyclic approximated min algorithm". The row processing unit 22 includes the mininium-value selecting unit 31, the sign calculating unit 32, and the LLR calculating unit 33. In Fig. 6, a Min1LLR (minimum LLR of the m-th row) is B_mn(1), a Min2LLR (second minimum LLR of the m-th row) is B_mn(2), and these are the values retained in the intermediate-result retaining unit 21. In Fig. 6, S_m and the "sign of the LLR:β_mn of the m-th row and n-th column of the (1-1)-th time" are also the values retained in the intermediate-result retaining unit 21.
The minimum-value selecting unit 31 selects the Min2LLR(B_mn(2)) when the column number n to be row-processed coincides with the column number n(1) of the Min1LLR (B_mn(1)), and selects the Min1LLR (B_mn(1)) in other cases, and outputs the selected result. The sign calculating unit 32 multiplies the "S_m updated by the (1-1)-th time column processing" by the "sign of the LLR:β_mn of the m-th row and n-th column of the (1-1)-th time", and outputs S_m' as a result of the multiplication. In this case, S_m' is retained in the intermediate-result retaining unit 21. The LLR calculating unit 33 multiplies the minimum LLR obtained from the minimum-value selecting unit 31 by the multiplication result S_m' of the sign (+ or -) obtained from the sign calculating unit 32, thereby calculating LLR: α_mn ⁽¹⁾. Based on this, according to the "Min-Sum algorithm", the memory that has been necessary by the row weight portion can be reduced to the k value portion.
Fig. 19 is a configuration example of the column processing unit 23 that performs column processing according to the "Serial cyclic approximated min algorithm". This column processing unit 23 includes the α adding unit 41, the λ adding unit 42, the minimum-k-value comparing unit 43, and the sign calculating unit 44. In the present embodiment, k=3 is described as an example. In Fig. 19, LLR of a column weight portion, α'_mn, α_mn, λ_n, S_m', Min1LLR, Min2LLR, Min3LLR (third-minimum LLR of the m-th row) are the values retained in the intermediate-result retaining unit 21.
In the column processing unit 23, the α adding unit 41 adds all LLR: α_mn ⁽¹⁾ including the m-th row LLR updated in the first-time row processing. Further, the λ adding unit 42 adds the reception LLR:λ_n to the result of the addition by the α adding unit 41, controls a switch 45 to be first connected to a block below, and outputs β_mn ⁽¹⁾ by subtracting α_mn ⁽¹⁾ from the added result. The minimum-k-value comparing unit 43 (k=3) receives |β_mn ⁽¹⁾|.
Although not shown in Fig. 19, as in the embodiment described above, when n of the n-th column to be column processed coincides with any one of n(1), n(2), n(3) indicating the column numbers corresponding to B_mn(1), B_mn(2), B_mn(3), stored in the Min1LLR, Min2LLR, Min3LLR respectively, for example, B_mn(1) of n=n(i) is thinned, and the operation as shown in Fig. 8 is performed. Specifically, information held in the Min2LLR is deleted, and information held in the Min3LLR is shifted to the Min2LLR. A maximum value "FFFF", for example (in the case of 16 bits), is stored in the Min3LLR. Accordingly, a comparison process excluding the column to be processed can be performed, and at least the Min3LLR can be necessarily updated in the column processing.
After this processing, as shown in Fig. 19, |β_mn ⁽¹⁾| is compared with each of the Min1LLR, Min2LLR, Min3LLR. When "|β_mn ⁽¹⁾|<Min3LLR", the LLR of the minimum 3 value is updated. On the other hand, the sign of β_mn ⁽¹⁾ output by the λ adding unit 42 is retained in the intermediate-result retaining unit 21, as the "sign of the LLR:β_mn ⁽¹⁾ of the m-th row and n-th column of the first time". Further, the sign calculating unit 44 multiplies S_m' updated in the first-time row processing, by the sign of the above β_mn ⁽¹⁾ , and updates S_m retained in the intermediate-result retaining unit 21, using a result of this multiplication. In comparing |β_mn ⁽¹⁾| with each of the Min1LLR, Min2LLR, Min3LLR, |β_mn ⁽¹⁾| is first compared with the Min2LLR as the center value of B_mn(i), and thereafter, comparison is performed in a tree shape as shown in Fig. 19. For example, there is an effect that the execution time becomes {(k+1)/2}/2 (where k is an odd number), as compared with the effect when |β_mn ⁽¹⁾| is compared first with the Min1LLR that becomes the minimum value. When k is an even number, there are two center values of B_mn(i). In this case, any one of the two values can be compared first. When k is an even number, there is an effect that the execution time becomes {k/2+1}/k (where k is an even number), as compared with the effect when |β_mn ⁽¹⁾| is compared first with the Min1LLR that becomes the minimum value. From the Min1LLR and Min2LLR of this comparison result, the circuit shown in Fig. 6 obtains α'_mn ⁽¹⁾, and adds this to β_mn ⁽¹⁾, thereby calculating β_n ⁽¹⁾, and the process control moves to the next column processing by the switch 45.
The flow of the processing in the "Serial cyclic approximated min algorithm" according to the present embodiment is explained next with reference to a flowchart shown in Fig. 9. In Fig. 9, it is described that the "row processing", "column processing", "row processing", ..., "column processing" are performed in the "iterative decoding first time", "iterative decoding second time", ..., "iterative decoding last time". In the present embodiment, after the "row processing step 1", the "column processing step" and the "row processing step 2" are repeated until the calculation is completed for all m of the column number n. That is, the processing is performed in the order of the "row processing step 1", "column processing step", "row processing step 2", "column processing step", "row processing step 2", "column processing step", ..., "row processing step 2", "row processing step 1", "column processing step", "row processing step 2", "column processing step", "row processing step 2", "column processing step", .., "row processing step 2".
In the above "Serial cyclic approximated min algorithm", the reception-LLR calculating unit 11 first calculates the reception LLR from the reception information (steps S11, S12), and sets a result of the calculation to the intermediate-result retaining unit 21, as an initial value (step S13). The controller 25 initializes the number of repetitions as 1=1 (step S13). The calculation of Equation (33) is cyclically performed from n=1 to n=N, using the λ adding unit 42, the minimum-k-value comparing unit 43, and the sign calculating unit 44, out of the column processing unit 23 (step S13).
Next, the decoding core unit 12 performs the first-time (first-time to the last-time) iterative decoding calculation (step S14). Specifically, as the first-time iterative decoding, the row processing unit 22 performs the row processing (using the reception LLR) to the row having "1" in the first column, and delivers a result of the calculation to the column processing unit 23. Thereafter, the column processing unit 23 performs the column processing of the first column, and retains (updates) B_mn(i) and S_m as a result of the calculation, in the intermediate-result retaining unit 21. Thereafter, the row processing unit 22 executes the row processing step 2, and delivers a result of the calculation to the column processing unit 23. The row processing unit 22 and the column processing unit 23 repeat the column processing step and the row processing step 2. Thereafter, processing similar to the above processing is performed in the order of the second column, third column, ..., N-th column. B_mn(i) and S_m are retained in the intermediate-result retaining unit 21 (corresponding to the iterative decoding first time). At the second and subsequent iterative decoding, the row processing is performed using the LLR and S_m updated by the processing one before. Thereafter, decoding is performed in the similar manner as in the first time.
After executing the first-time iterative decoding, the decoding-result determining unit 24 performs a hard decision on the posterior value calculated at the repetition first time, determines this determination value as the decoding result x', and performs a parity check (stop regulation). In the stop regulation, when a result of the parity check is OK ("Hx'=0") or when the number of repetitions is l=1_max, the decoding result x' at this time is finally output (step S15). When the above two conditions are not satisfied, the controller 25 sets 1=1+1, and the decoding core unit 12 performs the (1+1)-th time iterative decoding.
Deletion of the memory size according to a notation method of a column number is explained next, as in the embodiment described above. Fig. 10 depicts a column number notation according to the present embodiment. In the "Serial cyclic approximated min algorithm", column numbers are noted in the ascending order from n=0, for example. Conventionally, a column number n is expressed as the column number itself (absolute column number) of the parity check matrix. However, in the present embodiment, column numbers are expressed as relative column numbers, such as a minimum column number of "1" of the m-th row in the parity check matrix is expressed as n=0, a column number of the next "1" of the m-th row is expressed as n=1, and thereafter, the column numbers are expressed as n=2, 3, ..., at each "1". That is, conventionally, when the absolute column number of "1" in the parity check matrix is "32768", the number of bits necessary to express the column number is 15 bits. On the other hand, according to the present embodiment, when the row weight is eight, the memory size can be reduced to three bits which can express 0 to 7. When the row weight is 16, the memory size can be reduced to four bits which can express 0 to 15.
As described above, in the present embodiment, the LDPC decoding is performed to minimize the absolute value |β_mn| of the LLR for the row processing, to the minimum k value in row unit by the cyclic structure. Therefore, the memory capacity required to store the absolute values can be substantially reduced. When the row weight is 20 and also k=3, for example, the required memory capacity can be reduced to 3/20 of the conventional capacity. Further, by changing the column number from the absolute column number (1, 3, 10, 15 ...) to the relative column number (0, 1, 2, 3 ...), the required memory capacity can be further reduced.
In the "Serial cyclic approximated min algorithm" according to the present embodiment, calculation and updating of probability information (LLR) by the row processing and column processing are performed cyclically for each one bit. Accordingly, probability propagation can be performed more efficiently than that according to the conventional "Min-Sum algorithm".
In the "Serial cyclic approximated min algorithm" according to the present embodiment, as the row processing step 2, α'_mn ⁽¹⁾ is updated. The updated α'_mn ⁽¹⁾ is added to β_mn ⁽¹⁾ using the updated result, thereby updating β_n ⁽¹⁾. Therefore, the decoding can be related to the serial decoding in the complete bit unit, and the number of repetitions can be further reduced.
In the present embodiment, while the LLR to be row processed has one value, the k number can be any number equal to or higher than two values. In the present embodiment, it is explained that after the row processing step 1 is performed, the column processing step and the row processing step 2 are performed alternately. The updating of the probability information (LLR) by the row processing and the column processing is cyclically performed for each one bit. However, the execution is not limited to the above. Alternatively, calculation and updating of the probability information (LLR) by the row processing and the column processing can be performed cyclically for a plurality of bits each time.

Seventh Embodiment

A receiving device and a decoding method according to a seventh embodiment are explained next. The LDPC decoding according to the present embodiment can be applied when the calculation and updating of the probability information (LLR) by the row processing and column processing are performed for each one bit or a predetermined plurality of bits. For example, the number of repetitions can be' reduced by parallelizing calculations. In the present embodiment, the "Serial cyclic approximated min algorithm" is executed using what is called "Overlapped" B_mn ^c and S_m, by arranging such that the B_mn(i) and S_m of the intermediate-result retaining unit are one set regardless of the number of parallelization, and parallelized all processing units update the same B_mn ^c and S_m. The decoding algorithm according to the present embodiment is hereinafter called the "Overlapped serial cyclic approximated min algorithm".
The "Overlapped serial cyclic approximated min algorithm" executed by the receiving device according to the present embodiment is shown below.

(Initialization step)

First, the number of repetitions 1=1 and the maximum number of repetitions l_max are set. Further, a reception LLR:λ_n is input, and B_mn(i)^c is obtained as given by the following Equation (37), where β_mn(i) ⁽⁰⁾ is an LLR of the minimum k value of the m-th row at the initial time. As a sign of the LLR:β_mn ⁽⁰⁾ in the m-th row at the initial time, sgn(λn) is input, and S_m is obtained as shown by the following Equation (37):
$\begin{array}{l} [Expression 33] \\ \begin{array}{l} B_{mnʹ}^{C} & = |β_{mn (i)}^{(0)}| = \min_{n \in N (m) \ \{n\} \{(1), n (2), \dots, n (i - 1)\}} [|λ_{n}|], \forall i \in [1 k] \\ S_{m} & = \prod_{n \in N (m)} sgn (λ_{n}) \\ n (i) & = \arg \min_{n \in N (m) \ \{n\} \{(1), n (2), \dots, n (i - 1)\}} [|λ_{n}|] \\ n \\ (0) & = φ \end{array} \end{array}$
where B_mn(i) ^c is an absolute value of the LLR:β_mn(i) of the minimum k value of the m-th row, and is used in common in the parallel processing, n(i) is a column number of the minimum i-th LLR in B_mn(i) ^c.

(Row processing step 1)

In the present embodiment, a starting column of each row processing is arbitrary. At the stage where the processing ends up to the final column, decoding is performed again cyclically from the first column. As the row processing, the repetition first-time LLR:α_mn ⁽¹⁾ of the bit n to be sent from the check node m to the bit node n is updated for 0≤g≤G-1, g·N_G+1≤n≤(g+1)·N_G, where G is a parallel number, N_G is a column number that each parallelized decoding circuit processes, and G·N_g=N, and for each m, by the following Equation (38):
$\begin{array}{l} [Expression 34] \\ \begin{array}{l} α_{mn}^{(l)} & = \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ < g \cdot N_{G} \end{array}} sgn (β_{mnʹ}^{(l)}) \cdot \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ > g \cdot N_{G} \end{array}} sgn (β_{mnʹ}^{(l - 1)}) \cdot \min_{nʹ \in N_{k} (m) \ n} ⌊ B_{mnʹ}^{C} ⌋ \\ = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \min_{nʹ \in N_{k} (m) \ n} [B_{mnʹ}^{C}] \\ = S_{m}^{ʹ} \cdot \min_{nʹ \in N_{k} (m) \ n} [B_{mnʹ}^{C}] \\ S_{m}^{ʹ} & = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \\ β_{n}^{(l)} & = λ_{n} + \sum_{m \in M (n) \ m} {αʹ}_{mn}^{(l)} \end{array} \end{array}$
Specifically, for example, G row processing units allocated to the G columns, into which the column is divided for each column number: N_G, perform the row processing in parallel. The G row processing units perform the parallel processing, and perform the same operation as that of the "Serial cyclic approximated min algorithm", except that all the processing units use the same B_mn ^c.

(Column processing step)

Next, as the column processing, the repetition first-time LLR:β_mn ⁽¹⁾ of the bit n to be sent from the bit node n to the check node m is updated, for each m of the column number n performed at the row processing step 1, by the following Equation (39). That is, in the present embodiment, the column processing represented by the following Equation (39) is performed in parallel, for each column after the row processing is performed in parallel as described above. However, in performing the column processing in parallel, at the subsequent column processing step and the row processing step 2, the calculation is performed for each row in order starting from the smallest row number of the row number m, for example. However, when all rows having "1" standing are executed without overlapping the order of the row numbers to be executed, the calculation can be performed in any order.
$\begin{array}{l} [Expression 35] \\ \begin{array}{l} β_{mn}^{(l)} = λ_{n} + \sum_{mʹ \in M (n) \ m} {αʹ}_{m^{'} n}^{(l)} = β_{n}^{(l)} - α_{mn}^{(l)} \\ S_{m} = S_{m}^{ʹ} \cdot sgn (β_{mn}^{(l)}) \\ n_{i} = \arg \min_{nʹ \in N_{k} (m) \ \{n\} \{_{1} n_{2} \dots n_{i - 1} n_{i} n\}} [B_{mnʹ}^{C}, |β_{mn}^{(l)}|] \\ B_{{mn}_{i}} = \min_{nʹ \in N_{k} (m) \ \{n\} \{_{1} n_{2} \dots n_{i - 1} n_{i} n\}} [B_{mnʹ}^{C}, |β_{mn}^{(l)}|], \forall i \in [1 k] \end{array} \end{array}$

(Row processing step 2)

Further, as the row processing again, the repetition first-time LLR:α'_mn ⁽¹⁾ of the bit n to be sent from the check node m to the bit node n is updated, for the same m of the row executed in the column processing of the column number n, by the following Equation (40):
$\begin{array}{l} [Expression 36] \\ \begin{array}{l} {αʹ}_{mn}^{(l)} = S_{m} \cdot sgn (β_{mn}^{(l)}) \cdot \min_{nʹ \in N_{k} (m) n} ⌊ B_{mnʹ}^{C} ⌋ \\ {Sʹ}_{m} = S_{m} \cdot sgn (β_{mn}^{(l)}) \\ β_{n}^{(l)} = β_{mn}^{(l)} + {αʹ}_{mn}^{(l)} \end{array} \end{array}$
Specifically, as the row processing again, α'_mn (1) is updated. The updated α'_mn (1) is added to β_mn ⁽¹⁾ using the updated result, thereby updating β_n ⁽¹⁾. Thereafter, by returning to the column processing step, calculation is repeated until when the calculation is completed for all m of the column number n. When the processes at the column processing step and the row processing step end for all rows m having "1" standing in the check matrix of the column number n, the process control moves to the stop regulation.
The stop regulation is similar to that of the "Serial cyclic approximated min algorithm" described above.
A configuration and operation of the LDPC decoder 5 according to the seventh embodiment that achieves the above "Overlapped serial cyclic approximated min algorithm" is explained below.
Fig. 13 is a configuration example of the LDPC decoder 5 according to the present embodiment, which is similar to the configuration of the embodiment described above. This LDPC decoder 5 includes the reception-LLR calculating unit 11 that calculates the reception LLR from the reception information, and the decoding core unit 12a that performs decoding of the present embodiment. The decoding core unit 12a includes the intermediate-result retaining unit 21a configured by a memory which stores therein an intermediate result (intermediate value) of decoding, the row processing units 22-1 to 22-G that perform row processing (parallel processing) according to the present embodiment, the column processing units 23-1 to 23-G that execute column processing (parallel processing) according to the present embodiment, the decoding-result determining unit 24 that performs a hard decision of a posterior value in the column processing and an error determination of a parity check result, as a stop regulation according to the present embodiment, and the controller 25a that performs a repetition control of decoding.
In Fig. 13, the LDPC decoder 5 according to the present embodiment uses in common B_mn ^c and S_m of the intermediate-result retaining unit 21a, following the above Equations (37), (38), (39), and (40), when each row processing unit and each column processing unit perform processing in parallel, thereby updating B_mn ^c and S_m, respectively. Based on this parallel processing, B_mn ^c and S_m are rapidly updated according to the parallel number, which substantially reduces the number of iterative decodings.
According to the present embodiment, in the parallel processing, when calculation of the same row occurs in the same clock and when the same buffer is referenced, various measures are taken, such as a memory access priority order is set to each processing unit, a memory bank is partitioned, and the timing of the memory access is adjusted using a shift register.
As described above, in the "Overlapped serial cyclic approximated min algorithm" according to the present embodiment, the row processing and the column processing are performed in parallel, using the "Serial cyclic approximated min algorithm" described above. Further, the intermediate-result retaining unit that retains the minimum k value updated in each column processing performed in parallel is shared, and the minimum k value is updated in each column processing performed in parallel. With this arrangement, the decoding number of repetitions can be substantially reduced, as compared with the decrease according to the "Min-Sum algorithm" and the above sixth embodiment.
In the "Overlapped serial cyclic approximated min algorithm" according to the present embodiment, as the row processing step 2, α'_mn ⁽¹⁾ is updated, and the updated α'_mn ⁽¹⁾ is added to β_mn ⁽¹⁾ using the updated result, thereby updating β_n ⁽¹⁾. Therefore, the decoding can be related to the serial decoding in the complete bit unit, and the number of repetitions can be further reduced, as compared with the decrease in the second embodiment.

Eighth Embodiment

A receiving device (communication apparatus) and a decoding method according to an eighth embodiment are explained below. In the present embodiment, the process of updating only the absolute value of the LLR of the minimum k value and the decoding using the approximate minimum value in the "Serial cyclic approximated min algorithm" according to the sixth embodiment or the "Overlapped serial cyclic approximated min algorithm" according to the seventh embodiment are cyclically applied to the "Normalized BP-based algorithm" as the known decoding algorithm using the "Min-Sum algorithm".
Before explaining the decoding algorithm of the present embodiment, the known "Normalized BP-based algorithm" that is the basis of the decoding algorithm is shown below. The row processing different from that of the "Min-Sum algorithm" is explained.

(Row processing step 1)

A row processing step 1 of the "Normalized BP-based algorithm" can be generalized by the following Equation (41). In this case, as the row processing step 1, the repetition first-time LLR:α_mn ⁽¹⁾ is updated for each of m and n by the following Equation (41), where A is a constant called a normalization factor. In the "Normalized BP-based algorithm", the repetition first-time LLR obtained by the "Min-Sum algorithm" is corrected by the normalization factor A.
$\begin{array}{l} [Expression 37] \\ \begin{array}{l} α_{mn}^{(1)} & = 2 \tanh^{-1} (\prod_{nʹ \in N (m) \ n} \tanh (\frac{β_{mnʹ}^{(l - 1)}}{2})) \\ = 2 \tanh^{-1} (\prod_{nʹ \in N (m) \ n} sgn (β_{mnʹ}^{(l - 1)}) \cdot \prod_{nʹ \in N (m) \ n} \tanh (\frac{β_{mnʹ}^{(l - 1)}}{2})) \\ = \prod_{nʹ \in N (m) \ n} sgn (β_{mnʹ}^{(l - 1)}) \cdot 2 \tanh^{-1} (\prod_{nʹ \in N (m) \ n} \tanh (\frac{β_{mnʹ}^{(l - 1)}}{2})) \\ \approx \frac{1}{A} \prod_{nʹ \in N (m) \ n} sgn (β_{mnʹ}^{(l - 1)}) \cdot \min_{nʹ \in N (m) \ n} |β_{mnʹ}^{(l - 1)}| \end{array} \end{array}$
The decoding algorithm when the "Serial cyclic approximated min algorithm" or the "Overlapped serial cyclic approximated min algorithm" is applied to the "Normalized BP-based algorithm" is explained below. In the following, explanations are omitted for the processing (initialization, column processing, and stop regulation) similar to that of the "Serial cyclic approximated min algorithm" or the "Overlapped serial cyclic approximated min algorithm". The row processing step 1 different from that of the "Serial cyclic approximated min algorithm" or the "Overlapped serial cyclic approximated min algorithm" is explained below.

(Row processing step 1 using Serial cyclic approximated min algorithm)

In the present embodiment, a starting column of the row processing is arbitrary. At the stage where the processing ends to the last column, decoding is performed again cyclically from the first column. The α_mn ⁽¹⁾ and α'_mn ⁽¹⁾ of the row processing steps 1 and 2 of the decoding algorithm according to the present embodiment using the "Serial cyclic approximated min algorithm" can be generalized by the following Equation (42). In this case, as the row processing step 1, the repetition first-time LLR:α_mn ⁽¹⁾ is updated for each of m and n by the following Equation (42). That is, the repetition first-time LLR obtained by the "Serial cyclic approximated min algorithm" is corrected by the normalization factor A in the following Equation (42):
$\begin{array}{l} [Expression 38] \\ \begin{array}{l} α_{mn}^{(l)} & = \frac{1}{A} \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ < n \end{array}} sgn (β_{mnʹ}^{(l)}) \cdot \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ > n \end{array}} sgn (β_{mnʹ}^{(l - 1)}) \cdot \min_{nʹ \in N_{k} (m) \ n} [B_{mnʹ}] \\ = \frac{1}{A} S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \min_{nʹ \in N_{k} (m) \ n} [B_{mnʹ}] \\ = \frac{1}{A} S_{m}^{ʹ} \cdot \min_{nʹ \in N_{k} (m) \ n} [B_{mnʹ}] \\ {αʹ}_{mn}^{(l)} & = \frac{1}{A} S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \min_{nʹ \in N_{k} (m) \ n} [B_{mnʹ}] \end{array} \end{array}$

(Row processing step 1 using Overlapped serial cyclic approximated min algorithm)

The α_mn ⁽¹⁾ and α'_mn ⁽¹⁾ of the row processing steps 1 and 2 of the decoding algorithm according to the present embodiment using the "Overlapped serial cyclic approximated min algorithm" can be generalized by the following Equation (43). In this case, as the row processing step 1, the repetition first-time LLR:α_mn ⁽¹⁾ is updated for 0≤g≤G-1, g·N_G+1≤n≤(g+1)·N_G, and for each m by the following Equation (43). That is, in the following Equation (43), the repetition first-time LLR obtained by the "Overlapped serial cyclic approximated min algorithm" is corrected by the normalization factor A.
$\begin{array}{l} [Expression 39] \\ \begin{array}{l} α_{mn}^{(l)} & = \frac{1}{A} \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ < g \cdot N_{G} \end{array}} sgn (β_{mnʹ}^{(l)}) \cdot \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ > g \cdot N_{G} \end{array}} sgn (β_{mnʹ}^{(l - 1)}) \cdot \min_{nʹ \in N_{k} (m) \ n} [{B^{C}}_{mnʹ}] \\ = \frac{1}{A} S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \min_{nʹ \in N_{k} (m) \ n} [{B^{C}}_{mnʹ}] \\ = \frac{1}{A} S_{m}^{ʹ} \cdot \min_{nʹ \in N_{k} (m) \ n} [{B^{C}}_{mnʹ}] . \\ {αʹ}_{mn}^{(l)} & = \frac{1}{A} S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \min_{nʹ \in N_{k} (m) \ n} [{B^{C}}_{mnʹ}] \end{array} \end{array}$
In the decoding algorithm according to the present embodiment, after the row processing step 1 is performed as described above, processing based on the column processing and the stop regulation similar to those of the "Serial cyclic approximated min algorithm" or the "Overlapped serial cyclic approximated min algorithm" is performed to obtain the final code result.
Characteristic operations of the row processing unit of the LDPC decoder 5 that executes the decoding algorithm of the present embodiment are explained below with reference to the drawings. The entire configuration of the LDPC decoder 5 is similar to that shown in Fig. 5 or Fig. 13.
Fig. 15 is a configuration example of the row processing units 22, 22-1 to 22-G that perform row processing of the present embodiment, which is similar to the example of the above embodiments. The row processing unit includes the minimum value selecting unit 31a. Configurations similar to those explained with reference to Fig. 6 are denoted by like reference numerals, and explanations thereof are not repeated. The minimum value selecting unit 31a according to the present embodiment corrects the minimum value (Min1LLR or Min2LLR) of the LLR read from the intermediate-result retaining unit 21 (or 21a), using the normalization factor A, for example. Specifically, the minimum value selecting unit 31a performs the normalization by dividing the LLR minimum value by A.
As described above, according to the present embodiment, the "Serial cyclic approximated min algorithm" or the "Overlapped serial cyclic approximated min algorithm" is applied to the "Normalized BP-based algorithm" having the better performance than that of the "Min-Sum algorithm". With this arrangement, effects similar to those of the sixth and seventh embodiments can be obtained. Further, performance close to that of the "Sum-Product algorithm" can be achieved, regardless of the circuit amount substantially equivalent to that of the "Min-Sum algorithm".
In the present embodiment, the "Serial cyclic approximated min algorithm" or the "Overlapped serial cyclic approximated min algorithm" is applied to the "Normalized BP-based algorithm". Alternatively, the "Serial cyclic approximated min algorithm" or the "Overlapped serial cyclic approximated min algorithm" can also be applied to the known "Offset BP-based algorithm" or other algorithm. In this case, effects similar to those described above can also be obtained.

Ninth Embodiment

A receiving device (communication apparatus) and a decoding method according to a ninth embodiment are explained below. In the present embodiment, the process of updating only the absolute value of the LLR of the minimum k value and the decoding using the approximate minimum value in the "Serial cyclic approximated min algorithm" according to the sixth embodiment or the "Overlapped serial cyclic approximated min algorithm" according to the seventh embodiment are cyclically applied to the "δ min algorithm" as the known decoding algorithm having superior correction performance of LLR:β_mn to that of the "Normalized BP-based algorithm" or the "Offset BP-based algorithm".
Before explaining the decoding algorithm of the present embodiment, the known "δ min algorithm" that is the basis of the decoding algorithm is explained. The row processing different from that of the "Min-Sum algorithm" is explained below.

(Row processing step 1)

The α_mn ⁽¹⁾ and α'_mn ⁽¹⁾ of the row processing steps 1 and 2 of the "δ min algorithm" can be generalized by the following Equation (44). In this case, as the row processing step 1, the repetition first-time LLR:α_mn ⁽¹⁾ is updated for each of m and n by the following Equation (44). At the row processing step 1 of the "δ min algorithm", α_mn ⁽¹⁾ is calculated by calculating Θ from the absolute value: |β_mn' ^(i-1)| of the LLR updated at the repetition l-1-th time.
$\begin{array}{l} [Expression 40] \\ \begin{array}{l} α_{m, n}^{(i)} = \prod_{nʹ \in N (m) \ n} sgn (β_{mnʹ}^{(i - 1)}) \cdot \underset{nʹ \in N (m) \ n}{Θ} [|β_{m, nʹ}^{(i - 1)}|] \\ \underset{n \in A}{Θ} (I_{n}) \equiv I_{1} Θ I_{2} \dots Θ I_{|A|} \\ a Θ b \equiv \max (\min (a b) - Δ, 0) \\ Δ \equiv \max (0.9 - |a - b| / 2, 0) \\ {αʹ}_{mn}^{(l)} = \prod_{nʹ \in N_{k} (m) \ n} sgn (β_{mnʹ}^{(l)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{Θ} [β_{mnʹ}] \end{array} \end{array}$
The decoding algorithm when the "Serial cyclic approximated min algorithm" or the "Overlapped serial cyclic approximated min algorithm" is applied to the "δ min algorithm" is explained below. In the following, explanations are omitted for the processing (initialization, column processing, and stop regulation) similar to that of the "Serial cyclic approximated min algorithm" or the "Overlapped serial cyclic approximated min algorithm". The row processing step 1 different from that of the "Serial cyclic approximated min algorithm" or the "Overlapped serial cyclic approximated min algorithm" is explained below. In the present embodiment, a starting column of the row processing is arbitrary. At the stage where the processing ends to the last column, decoding is performed again cyclically from the first column.

(Row processing step 1 using Serial cyclic approximated min algorithm)

The α_mn ⁽¹⁾ and α'_mn ⁽¹⁾ of the row processing steps 1 and 2 of the decoding algorithm of the present embodiment using the "Serial cyclic approximated min algorithm" can be generalized by the following Equation (45). In this case, as the row processing step 1, the repetition first-time LLR: α_mn ⁽¹⁾ is updated for 1≤n≤N and for each m by the following Equation (45). In the row processing step 1 of the decoding algorithm, α_mn ⁽¹⁾ is calculated by calculating Θ from the absolute value: B_mn' of the LLR of the minimum k value updated at the repetition 1-1-th time.
$\begin{array}{l} [Expression 41] \\ \begin{array}{l} α_{mn}^{(l)} & = \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ < n \end{array}} sgn (β_{mnʹ}^{(l)}) \cdot \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ > n \end{array}} sgn (β_{mnʹ}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{Θ} [B_{mnʹ}] \\ = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{Θ} [B_{mnʹ}] \\ = S_{m}^{ʹ} \cdot \underset{nʹ \in N_{k} (m) \ n}{Θ} [B_{mnʹ}] \\ {αʹ}_{mn}^{(l)} & = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{Θ} [β_{mnʹ}] \end{array} \end{array}$

The α_mn ⁽¹⁾ and α'_mn ⁽¹⁾ of the row processing steps 1 and 2 of the decoding algorithm of the present embodiment using the "Overlapped serial cyclic approximated min algorithm" can be generalized by the following Equation (46). In this case, as the row processing step 1, the repetition first-time LLR:α_mn ⁽¹⁾ is updated for 0≤g≤G-1, g·N_G+1≤n≤(g+1)·N_G, and for each m by the following Equation (46). At the row processing step 1 of this decoding algorithm, α_mn ⁽¹⁾ is calculated by calculating Θ from the absolute value: B_mn' ^c of the LLR of the minimum k value updated by the parallel processing at the repetition 1-1-th time.
$\begin{array}{l} [Expression 42] \\ α_{mn}^{(l)} & = \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ < g \cdot N_{G} \end{array}} sgn (β_{mnʹ}^{(l)}) \cdot \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ > g \cdot N_{G} \end{array}} sgn (β_{mnʹ}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{Θ} ⌊ B_{mnʹ}^{C} ⌋ \\ = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{Θ} [B_{mnʹ}^{C}] \\ = S_{m}^{ʹ} \cdot \underset{nʹ \in N_{k} (m) \ n}{Θ} [B_{mnʹ}^{C}] \\ {αʹ}_{mn}^{(l)} & = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{Θ} [B_{mnʹ}^{C}] \end{array}$
In the decoding algorithm according to the present embodiment, after the row processing step 1 is performed as described above, processing based on the column processing, the row processing step 2, and the stop regulation similar to those of the "Serial cyclic approximated min algorithm" or the "Overlapped serial cyclic approximated min algorithm" is executed, thereby obtaining the final code result.
Characteristic operations of the row processing unit of the LDPC decoder 5 that executes the decoding algorithm of the present embodiment are explained below with reference to the drawings. The entire configuration of the LDPC decoder 5 is similar to that shown in Fig. 5 or Fig. 13.
Fig. 16 is a configuration example of the row processing units 22, 22-1 to 22-G that perform row processing of the present embodiment, which is similar to that described in the above embodiments. This row processing unit includes the minimum-value selecting unit 31b. Constituent elements similar to those described with reference to Fig. 6 are denoted by like reference numerals, and explanations thereof are not repeated. While the LDPC decoder 5 shown in Fig. 5 is explained as one example, the present embodiment can also be similarly applied to the LDPC decoder 5 shown in Fig. 13.
The minimum-value selecting unit 31b according to the present embodiment reads the Min1LLR (B_mn(1)), Min2LLR(B_mn(2)), MinkLLR(B_mn(k)), and their column numbers from the intermediate-result retaining unit 21, and the calculating unit performs the Θ calculation. That is, in the minimum-value selecting unit 31b according to the present embodiment, the calculating unit performs the following calculation in the "δ min algorithm", to B_mn(k) in which the n-th column to be processed does not coincide with the column number n(k) of B_mn(k) retained in the intermediate-result retaining unit 21.
For example, the calculating unit obtains the updated value |α_mn ⁽¹⁾| (=Θ[(B_mn']) excluding the sign as represented by the following Equation (47):
$\begin{array}{l} [Expression 43] \\ \underset{nʹ \in N_{k} (m) \ n}{Θ} [B_{mnʹ}] \end{array}$
Further, by limiting the LLR to be calculated from the k value to the minimum 3 values, the calculations can be reduced. The calculating unit obtains the updated value |α_mn ⁽¹⁾ |(=Θ[(B_mn']) excluding the sign as represented by the following Equation (48):
$\begin{array}{l} [\begin{matrix} Expression 44 \end{matrix}] \\ \begin{array}{l} if (n = n_{(1)}) \underset{nʹ \in N_{k} (m) \ n}{Θ} [B_{mnʹ}] = B_{{mn}_{(2)}} Θ B_{mn}_{(3)} \\ else if (n = n_{(2)}) \underset{nʹ \in N_{k} (m) \ n}{Θ} [B_{mnʹ}] = B_{{mn}_{(1)}} Θ B_{mn}_{(3)} \\ else \underset{nʹ \in N_{k} (m) \ n}{Θ} [B_{mnʹ}] = B_{{mn}_{(1)}} Θ B_{mn}_{(2)} \end{array} \end{array}$
While the LLR to be calculated is limited from the k value to the minimum 3 values in the above example, the embodiment can also be applied to the case that the LLR is limited to the minimum 4, 5, ... values.
As described above, according to the present embodiment, the "Serial cyclic approximated min algorithm" or the "Overlapped serial cyclic approximated min algorithm" is applied to the "δ min algorithm" having the better performance than that of the "Min-Sum algorithm". With this arrangement, effects similar to those of the sixth and seventh embodiments can be obtained. Further, performance close to that of the "Sum-Product algorithm" can be achieved, regardless of the circuit amount substantially equivalent to that of the "Min-Sum algorithm". In the present embodiment, description is made for the case that the minimum value of the absolute values of the LLR for the row processing is corrected to the optimum value based on a predetermined correction equation prescribed by the known "δ min algorithm". However, the correction equation is not limited to this, and the correction equation prescribed by the algorithm other than the "δ min algorithm" can also be used. In this case, effects similar to those described above can also be obtained.

Tenth Embodiment

A receiving device (communication apparatus) and a decoding method according to a tenth embodiment are explained below. In the present embodiment, the process of updating only the absolute value of the LLR of the minimum k value and the decoding using the approximate minimum value in the "Serial cyclic approximated min algorithm" according to the sixth embodiment or the "Overlapped serial cyclic approximated min algorithm" according to the seventh embodiment are cyclically applied to the "Sum-Product algorithm".
Before explaining the decoding algorithm of the present embodiment, the known "Sum-Product algorithm" that is the basis of the decoding algorithm is explained. In the present embodiment, a method of calculation by tabling the mathematical function, i.e., a general "Sum-Product algorithm" using a TLU (table lookup), is described. The row processing different from that of the "Sum-Product algorithm" explained in the conventional technology is described.

(Row processing step 1 (1))

The α_mn ⁽¹⁾ and α'_mn ⁽¹⁾ of the row processing steps 1 and 2 of the "Sum-Product algorithm" using a TLU can be generalized by the following Equation (49). In this case, as the row processing step 1, the repetition first-time LLR:α_mn ⁽¹⁾ is updated for each of m and n by the following Equation (49). In the row processing step 1 of the "Sum-Product algorithm" using the TLU, a calculation using the TLU is performed to the absolute value: |β_mn' ^(l-1)| of the LLR updated at the repetition 1-1-th time.
$\begin{array}{l} [\begin{matrix} Expression 45 \end{matrix}] \\ \begin{array}{l} α_{m, n}^{(i)} = \prod_{nʹ \in N (m) \ n} sgn (β_{mnʹ}^{(i - 1)}) \cdot \underset{nʹ \in N (m) \ n}{TLU} [|β_{m, nʹ}^{(i - 1)}|] \\ \underset{n \in A}{TLU} (I_{n}) \equiv TLU (I_{1}, TLU (I_{2}, \dots TLU (I_{|A| - 1} I_{|A|}))) \\ TLU (a b) \equiv 2 \tanh^{-1} (\tanh \frac{a}{2} \cdot \tanh \frac{b}{2}) \\ {αʹ}_{m, n}^{(l)} = \prod_{nʹ \in N_{k} (m) \ n} sgn (β_{mn}^{(l)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{TLU} [|β_{mnʹ}^{(l)}|] \end{array} \end{array}$

(Row processing step 1 (2))

The row processing step 1 of the "Sum-Product algorithm" using the TLU can also be achieved by the method different from the above method. For example, the α_mn ⁽¹⁾ and α'_mn ⁽¹⁾ of the row processing steps 1 and 2 of the "Sum-Product algorithm" using a TLU different from the above algorithm can be generalized by the following Equation (50). In this case, as the row processing step 1, the repetition first-time LLR:α_mn ⁽¹⁾ is updated for each of m and n by the following Equation (50):
$\begin{array}{l} [\begin{matrix} Expression 46 \end{matrix}] \\ \begin{array}{l} α_{m, n}^{(i)} = \prod_{nʹ \in N (m) \ n} sgn (β_{mnʹ}^{(i - 1)}) \cdot \underset{nʹ \in N (m) \ n}{Ξ} [|β_{m, nʹ}^{(i - 1)}|] \\ \underset{n \in A}{Ξ} (I_{n}) \equiv I_{1} Ξ I_{2} Θ \dots Ξ I_{|A|} \\ a Ξ b \equiv \min (a b) + TLU 1 (|a + b|) - TLU 1 (|a - b|) \\ {αʹ}_{m, n}^{(l)} = \prod_{nʹ \in N_{k} (m) \ n} sgn (β_{mn}^{(l)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{Ξ} [|β_{mnʹ}^{(l)}|] \end{array} \end{array}$
For the TLU1(x), a table is prepared in advance based on the following (51). $TLU 1 (x) = \ln (1 + \exp (- x))$
In the "Sum-Product algorithm" using the TLU, the row processing step 1 represented by the above Equation (49) has a characteristic that while the table becomes large, the number of calculations is small. On the other hand, the row processing step 1 represented by the above Equation (50) has a characteristic that the number of calculations is large although the table becomes small.
The decoding algorithm when the "Serial cyclic approximated min algorithm" is applied to the "Sum-Product algorithm" using the TLU is explained below. In the following, explanations are omitted for the processing (initialization, column processing, and stop regulation) similar to that of the "Serial cyclic approximated min algorithm". The row processing step 1 different from that of the "Serial cyclic approximated min algorithm" is explained below. In the present embodiment, a starting column of the row processing is arbitrary, and at the stage where the processing ends up to the final column, decoding is performed again cyclically from the first column.

(Row processing step 1 (1) using Serial cyclic approximated min algorithm)

The α_mn ⁽¹⁾ and α'_mn ⁽¹⁾ of the row processing steps 1 and 2 of the decoding algorithm according to the present embodiment having the "Serial cyclic approximated min algorithm" applied to the row processing step (1) can be generalized by the following Equation (52). In this case, as the row processing step 1, the repetition first-time LLR:α_mn ⁽¹⁾ is updated for 1≤n≤N and for each m by the following Equation (52). In the row processing step 1 of the decoding algorithm, a calculation using the TLU is performed to the absolute value: B_mn' of the LLR of the minimum k value updated at the repetition 1-1-th time.
$\begin{array}{l} [Expression 47] \\ \begin{array}{l} α_{mn}^{(l)} & = \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ < n \end{array}} sgn (β_{mnʹ}^{(l)}) \cdot \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ > n \end{array}} sgn (β_{mnʹ}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{TLU} [B_{mnʹ}] \\ = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{TLU} [B_{mnʹ}] \\ = S_{m}^{ʹ} \cdot \underset{nʹ \in N_{k} (m) \ n}{TLU} [B_{mnʹ}] \\ {αʹ}_{mn}^{(l)} & = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{TLU} [B_{mnʹ}] \end{array} \end{array}$

(Row processing step using Serial cyclic approximated min algorithm 1 (2))

The α_mn ⁽¹⁾ and α'_mn ⁽¹⁾ of the row processing steps 1 and 2 of the decoding algorithm according to the present embodiment having the "Serial cyclic approximated min algorithm" applied to the row processing step 1(2) can be generalized by the following Equation (53). In this case, as the row processing step 1, the repetition first-time LLR:α_mn ⁽¹⁾ is updated for 1≤n≤N and for each m by the following Equation (53):
$\begin{array}{l} [Expression 48] \\ \begin{array}{l} α_{mn}^{(l)} & = \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ < n \end{array}} sgn (β_{mnʹ}^{(l)}) \cdot \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ > n \end{array}} sgn (β_{mnʹ}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{Ξ} [B_{mnʹ}] \\ = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{Ξ} [B_{mnʹ}] \\ = S_{m}^{ʹ} \cdot \underset{nʹ \in N_{k} (m) \ n}{Ξ} [B_{mnʹ}] \\ {αʹ}_{mn}^{(l)} & = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{Ξ} [B_{mnʹ}] \end{array} \end{array}$
The decoding algorithm when the "Overlapped serial cyclic approximated min algorithm" is applied to the "Sum-Product algorithm" using the TLU is explained below. In the following, explanations are omitted for the processing (initialization, column processing, and stop regulation) similar to that of the "Overlapped serial cyclic approximated min algorithm". The row processing step 1 different from that of the "Overlapped serial cyclic approximated min algorithm" is explained below.

(Row processing step using Overlapped serial cyclic approximated min algorithm 1(1))

The α_mn ⁽¹⁾ and α'_mn ⁽¹⁾ of the row processing steps 1 and 2 of the decoding algorithm according to the present embodiment having the "Overlapped serial cyclic approximated min algorithm" applied to the row processing step 1(1) can be generalized by the following Equation (54). In this case, as the row processing step 1, the repetition first-time LLR: α_mn ⁽¹⁾ is updated for 0≤g≤G-1, g·NG+1≤n≤(g+1)·N_G, and for each in by the following Equation (54). In the row processing step 1 of this decoding algorithm, a calculation using the TLU is performed to the absolute value: B_mn' ^c of the LLR of the minimum k value updated by the parallel processing at the repetition 1-1-th time.
$\begin{array}{l} [Expression 50] \\ \begin{array}{l} α_{mn}^{(l)} & = \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ < g \cdot N_{G} \end{array}} sgn (β_{mnʹ}^{(l)}) \cdot \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ > g \cdot N_{G} \end{array}} sgn (β_{mnʹ}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{TLU} ⌊ B_{mnʹ}^{C} ⌋ \\ = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{TLU} [B_{mnʹ}^{C}] \\ = S_{m}^{ʹ} \cdot \underset{nʹ \in N_{k} (m) \ n}{TLU} [B_{mnʹ}^{C}] \\ {αʹ}_{mn}^{(l)} & = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{TLU} [B_{mnʹ}^{C}] \end{array} \end{array}$

(Row processing step using Overlapped serial cyclic approximated min algorithm 1(2))

The α_mn ⁽¹⁾ and α'_mn ⁽¹⁾ of the row processing steps 1 and 2 of the decoding algorithm according to the present embodiment having the "Overlapped serial cyclic approximated min algorithm" applied to the row processing step 1(2) can be generalized by the following Equation (55). In this case, as the row processing step 1, the repetition first-time LLR: α_mn ⁽¹⁾ is updated for 0≤g≤G-1, g·N_G+1≤n≤(g+1)·N_G, and for each m by the following Equation (55) :
$\begin{array}{l} [Expression 50] \\ \begin{array}{l} α_{mn}^{(l)} & = \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ < g \cdot N_{G} \end{array}} sgn (β_{mnʹ}^{(l)}) \cdot \prod_{\begin{array}{l} nʹ \in N (m) \ n \\ nʹ > g \cdot N_{G} \end{array}} sgn (β_{mnʹ}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{Ξ} [B_{mnʹ}^{C}] \\ = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{Ξ} [B_{mnʹ}^{C}] \\ = S_{m}^{ʹ} \cdot \underset{nʹ \in N_{k} (m) \ n}{Ξ} [B_{mnʹ}^{C}] \\ {αʹ}_{mn}^{(l)} & = S_{m} \cdot sgn (β_{mn}^{(l - 1)}) \cdot \underset{nʹ \in N_{k} (m) \ n}{Ξ} [B_{mnʹ}^{C}] \end{array} \end{array}$
Characteristic operations of the row processing unit of the LDPC decoder 5 that executes the decoding algorithm of the present embodiment are explained below with reference to the drawings. The entire configuration of the LDPC decoder 5 is similar to that shown in Fig. 5 or Fig. 13.
Fig. 18 is a configuration example of the row processing units 22, 22-1 to 22-G that perform row processing of the present embodiment, which is similar to the configuration of the embodiment described above. The row processing unit includes the minimum-value selecting unit 31c. Constituent elements similar to those described with reference to Fig. 6 are denoted by like reference numerals, and explanations thereof are not repeated. While the LDPC decoder 5 shown in Fig. 5 is explained as one example, the present embodiment can also be similarly applied to the LDPC decoder 5 shown in Fig. 13.
The minimum-value selecting unit 31c according to the present embodiment reads the Min1LLR(B_mn(1)), Min2LLR(B_mn(2)), MinkLLR(B_mn(k)), and their column numbers from the intermediate-result retaining unit 21, and the calculating unit performs calculation using the TLU. That is, in the minimum-value selecting unit 31c according to the present embodiment, the calculating unit performs the following calculation in the "Sum-Product min algorithm", to B_mn(k) in which the n-th column to be processed does not coincide with the column number n(k) of B_mn(k) retained in the intermediate-result retaining unit 21.
For example, the calculating unit obtains the updated value excluding the sign, as represented by the following Equation (56):
$\begin{array}{l} [Expression 51] \\ \underset{nʹ \in N_{k} (m) \ n}{TLU} [B_{mnʹ}] OR \underset{nʹ \in N_{k} (m) \ n}{Ξ} [B_{mnʹ}] \end{array}$
Further, by limiting the LLR to be calculated from the k value to the minimum 3 values, the calculations can be reduced. The calculating unit obtains the updated value excluding the sign as represented by the following Equation (57):
$\begin{array}{l} [Expression 52] \\ \begin{array}{l} if (n = n_{(1)}) \underset{nʹ \in N_{k} (m) \ n}{TLU} [B_{mnʹ}] = TLU (B_{mn}) (_{(2)} B_{mn_{(3)}}) OR \underset{nʹ \in N_{k} (m) \ n}{Ξ} [B_{mnʹ}] = B_{mn_{(2)}} Ξ B_{mn_{(3)}} \\ else if (n = n_{(2)}) \underset{nʹ \in N_{k} (m) \ n}{TLU} [B_{mnʹ}] = TLU (B_{mn}) (_{(1)} B_{mn_{(3)}}) OR \underset{nʹ \in N_{k} (m) \ n}{Ξ} [B_{mnʹ}] = B_{{mn}_{(1)}} Ξ B_{mn_{(3)}} \\ else \underset{nʹ \in N_{k} (m) \ n}{TLU} [B_{mnʹ}] = TLU (B_{mn}) (_{(1)} B_{mn_{(2)}}) OR \underset{nʹ \in N_{k} (m) \ n}{Ξ} [B_{mnʹ}] = B_{mn_{(1)}} Ξ B_{mn_{(2)}} \end{array} \end{array}$
While the LLR to be calculated is limited from the k value to the minimum 3 values in the above example, the embodiment can also be applied to the case that the LLR is limited to the minimum 4, 5, ... values.
As described above, according to the present embodiment, the "Serial cyclic approximated min algorithm" or the "Overlapped serial cyclic approximated min algorithm" is applied to the "Sum-Product algorithm" using the TLU. With this arrangement, although calculations and the required memory capacity increase as compared with other embodiments, decoding performance can be improved. While the "Sum-Product algorithm" using the TLU is explained in the present embodiment, the principle can be similarly applied to other decoding algorithm for performing the TLU to the mathematical function. In the present embodiment, the TLU prescribed by the known "Sum-Product algorithm" is used for the minimum value of the absolute values of the LLR for the row processing. However, the TLU is not limited to the above, and the TLU other than the TLU prescribed by the "Sum-Product algorithm" can also be used. In this case, effects similar to the effects described above can also be obtained.
In the above embodiments, the processing is performed in the ascending order with the starting column of the row processing set as 1. However, for example, the starting column can be arbitrary, and the processing can be performed to an arbitrary column which is not overlapped. At the stage where the processing ends for all columns, iterative decoding can be performed again in the same order. Alternatively, the starting column of the row processing can be set arbitrary, and the processing can be performed to an arbitrary column which is not overlapped. At the stage where the processing ends for all columns, iterative decoding can be performed again in a different order to the arbitrary column not overlapped until the processing ends for all columns. In these cases, effects similar to those of each of the above embodiments can also be obtained.
While the use of the logarithmic likelihood ratio (LLR) as the probability information is explained in the above embodiments, other information than the logarithmic likelihood ratio (LLR) can also be used as the probability information.

INDUSTRIAL APPLICABILITY

As described above, the receiving device and the decoding method according to the present invention are effective for error correction technologies in the digital communication, and are particularly suitable for a communication apparatus that decodes the LDPC encoded signal.

Claims

A communication apparatus that decodes an LDPC-encoded codeword, using a check matrix, the communication apparatus comprising:
a retaining unit that retains an intermediate value obtained by a predetermined process in a decoding algorithm;

a row processing unit that performs row processing of calculating a logarithmic likelihood ratio (logarithmic likelihood ratio to be sent from a check node to a bit node: column-processing LLR) used in the column processing, based on an absolute value of a logarithmic likelihood ratio (logarithmic likelihood ratio to be sent from a bit node to a check node: row-processing LLR) corresponding to a row weight in a check matrix; and

a column processing unit that calculates a row-processing LLR to be used in the row processing, using a column-processing LLR corresponding to a column weight, and stores a minimum value of absolute values of the row-processing LLR in the retaining unit, wherein

the column processing unit performs a decoding while updating the minimum k value of the row.
The communication apparatus according to claim 1, wherein the apparatus divides the row of the check matrix into a predetermined number of columns, executes the row processing and the column processing in parallel in a matrix unit after the division, shares a region of the retaining unit that retains the minimum k value, and updates the minimum k value in each of column processes performed in parallel.
The communication apparatus according to claim 1, wherein the row processing unit multiplies a minimum value of absolute values of the row-processing LLR corresponding to the row weight by a multiplication result of signs of the row-processing LLR, thereby obtaining a column-processing LLR to be used in the next column process.
The communication apparatus according to claim 3, wherein the row processing unit further corrects the minimum value of absolute values of the row-processing LLR by a fixed normalization factor prescribed in advance, and obtains a column-processing LLR using a corrected value.
The communication apparatus according to claim 1, wherein the row processing unit corrects a minimum value of absolute values of the row-processing LLR corresponding to the row weight, to an optimum value, based on a predetermined correction equation, and multiplies the corrected value by a multiplication result of signs of the row-processing LLR, thereby obtaining a column-processing LLR to be used in the next column process.
The communication apparatus according to claim 1, wherein the row processing unit performs a predetermined calculation using a TLU (table lookup) to a minimum value of absolute values of the row-processing LLR corresponding to the row weight, and multiplies the calculated value by a multiplication result of signs of the row-processing LLR, thereby obtaining a column-processing LLR to be used in the next column process.
The communication apparatus according to any one of claims 3 to 6, wherein, at the repetition first time, when the row processing unit multiplies signs of the row-processing LLR corresponding to the row weight in a specific row, the row processing unit multiplies signs of the row-processing LLR updated by the repetition first-time column process, for a column number smaller than the column number to be processed, and multiplies signs of the row-processing LLR updated by the repetition (1-1)-th time column process, for a column number larger than the column number to be processed, and further multiplies results of these multiplications together.
The communication apparatus according to any one of claims 3 to 6, wherein, at the repetition first time, when the row processing unit multiplies signs of the row-processing LLR corresponding to the row weight in a specific row, the row processing unit multiplies a multiplication result S of signs of the row-processing LLR corresponding to the row weight updated by the repetition (l-1)-th time column process, by signs of the row-processing LLR updated by the repetition (1-1)-th time column process corresponding to the column number to be processed, and stores a result of this multiplication S' in the retaining unit.
The communication apparatus according to claim 8, wherein, at the repetition first time, when the column processing unit performs a column process of a specific column,
the column processing unit adds a reception LLR corresponding to a column number to be processed and a total value of column-processing LLR corresponding to the column weight other than the row number to be processed, sets a result of this addition as a row-processing LLR, and when an absolute value of the row-processing LLR is smaller than at least one of minimum k values to be processed, the column processing unit updates the minimum k value, and
the column processing unit multiplies a sign of the row-processing LLR as the addition result by a multiplication result S' of the sign held in the retaining unit, and updates a result of the multiplication as a multiplication result S of a sign used in the repetition (1+1)-th time row process.
A communication apparatus that decodes an LDPC-encoded codeword, using a check matrix, the communication apparatus comprising:
a row processing unit that performs row processing of calculating a logarithmic likelihood ratio (a logarithmic likelihood ratio to be sent from a check node to a bit node: called a column-processing LLR) used in the column process, based on an absolute value of a logarithmic likelihood ratio (a logarithmic likelihood ratio to be sent from a bit node to a check node: called a row-processing LLR) corresponding to a row weight in a check matrix; and

a column processing unit that performs column processing of calculating a row-processing LLR used in the row process, using a column-processing LLR corresponding to a column weight, wherein

the row processing unit and the column processing unit alternately execute the process by a predetermined number of times, thereby cyclically updating the row-processing LLR and the column-processing LLR.
The communication apparatus according to claim 10, wherein the row processing unit multiplies a minimum value of absolute values of the row-processing LLR corresponding to the row weight by a multiplication result of signs of the row-processing LLR, thereby obtaining a column-processing LLR to be used in the next column process.
The communication apparatus according to claim 11, wherein the row processing unit further corrects the minimum value of absolute values of the row-processing LLR by a fixed normalization factor prescribed in advance, and obtains a column-processing LLR using a corrected value.
The communication apparatus according to claim 10, wherein the row processing unit corrects a minimum value of absolute values of the row-processing LLR corresponding to the row weight, to an optimum value, based on a predetermined correction equation, and multiplies the corrected value by a multiplication result of signs of the row-processing LLR, thereby obtaining a column-processing LLR to be used in the next column process.
The communication apparatus according to claim 10, wherein the row processing unit performs a predetermined calculation using a TLU (table lookup) to a minimum value of absolute values of the row-processing LLR corresponding to the row weight, and multiplies the calculated value by a multiplication result of signs of the row-processing LLR, thereby obtaining a column-processing LLR to be used in the next column process.
The communication apparatus according to any one of claims 10 to 14, wherein, at the repetition first time, when the row processing unit multiplies signs of the row-processing LLR corresponding to the row weight in a specific row, the row processing unit multiplies signs of the row-processing LLR updated by the repetition first-time column process, for a column number smaller than the column number to be processed, and multiplies signs of the row-processing LLR updated by the repetition (1-1)-th time column process, for a column number larger than the column number to be processed, and further multiplies results of these multiplications together.
The communication apparatus according to claim 1 or 10, wherein the row processing unit uses a minimum value of absolute values of a reception LLR as the minimum value, at the repetition first-time decoding.
The communication apparatus according to claim 1 or 10, wherein the column processing unit calculates a posterior value at each time of executing the column process, executes a hard decision of the posterior value, and
outputs a result of the hard decision as a decoding result, when a result of a parity check is OK or when the number of repetitions is a prescribed largest number of times.
The communication apparatus according to claim 1 or 10, wherein a starting column of the row process is arbitrary, and performs iterative decoding from the first column again, when the process ends to the last column.
The communication apparatus according to claim 1 or 10, wherein a starting column of the row process is arbitrary, the process is performed to an arbitrary column which is not' overlapped, and the iterative decoding is performed in the same order again, at the stage where the process ends for all columns.
The communication apparatus according to claim 1 or 10, wherein a starting column of the row process is arbitrary, the process is performed to an arbitrary column which is not overlapped, and the iterative decoding is performed to an arbitrary column not overlapped, in a different order, until when the process ends for all columns.
The communication apparatus according to claim 1 or 10, wherein a column number of the row weight in a check matrix is noted in the ascending order starting from zero in the order of a small column number.
A decoding method for decoding an LDPC-encoded codeword, using a check matrix, the decoding method for performing a decoding by executing:
a row processing step of calculating a logarithmic likelihood ratio (a logarithmic likelihood ratio to be sent from a check node to a bit node: called a column-processing LLR) used in the column process, based on an absolute value of a logarithmic likelihood ratio (a logarithmic likelihood ratio to be sent from a bit node to a check node: called a row-processing LLR) corresponding to a row weight in a check matrix; and

a column processing step of calculating a row-processing LLR to be used in the row process, using a column-processing LLR corresponding to a column weight calculated by the row process, and further holding a minimum k value of absolute values of the row-processing LLR corresponding to the row weight

while updating the minimum k value of the row.
A decoding method for decoding an LDPC-encoded codeword, using a check matrix, the decoding method for alternately executing, by a predetermined number of times:
a row processing step of calculating a logarithmic likelihood ratio (a logarithmic likelihood ratio to be sent from a check node to a bit node: called a column-processing LLR) used in the column process, based on an absolute value of a logarithmic likelihood ratio (a logarithmic likelihood ratio to be sent from a bit node to a check node: called a row-processing LLR) corresponding to a row weight in a check matrix; and

a column processing step of calculating a row-processing LLR to be used in the row process, using a column-processing LLR corresponding to a column weight calculated by the row process,

thereby cyclically updating the row-processing LLR and the column-processing LLR.
The decoding method according to claim 22 or 23, wherein at the row processing step, a multiplication result of signs of the row-processing LLR is further used, to calculate the column-processing LLR.
The decoding method according to claim 24, wherein at the row processing step, at the repetition first time, when the signs of the row-processing LLR corresponding to the row weight in a specific row are multiplied, signs of the row-processing LLR updated by the repetition first-time column process are multiplied, for a column number smaller than the column number to be processed, and signs of the row-processing LLR updated by the repetition (1-1)-th time column process are multiplied, for a column number larger than the column number to be processed, and further results of these multiplications are multiplied together.
The decoding method according to claim 24, wherein at the row processing step, at the repetition first time, when the signs of the row-processing LLR corresponding to the row weight in a specific row are multiplied, a multiplication result S of signs of the row-processing LLR corresponding to the row weight updated by the repetition (1-1)-th time column process is multiplied by signs of the row-processing LLR updated by the repetition (1-1)-th time column process corresponding to the column number to be processed, and a result of this multiplication S' is held in a specified region of a memory.
The decoding method according to claim 26, wherein, at the repetition first time, when a column process of a specific column is performed,
a reception LLR corresponding to a column number to be processed is added to a total value of column-processing LLR corresponding to the column weight other than the row number to be processed, a result of this addition is set as a row-processing LLR, and when an absolute value of the row-processing LLR is smaller than at least one of minimum k values to be processed, the minimum k value is updated, and
a sign of the row-processing LLR as the addition result is multiplied by a multiplication result S' of the sign held in the specific region of the memory, and a result of the multiplication is updated as a multiplication result S of a sign used in the repetition (1+1)-th time row process.
The decoding method according to claim 22 or 23, wherein, at the repetition first-time decoding, a minimum value of absolute values of the reception LLR is used as the minimum value.
The decoding method according to claim 22 or 23, wherein a posterior value is calculated at each time of executing the column processing step, a hard decision of the posterior value is performed, and a result of the hard decision is output as a decoding result, when a result of a parity check is OK or when the number of repetitions is a prescribed largest number of times.
The communication apparatus according to claim 10, wherein each time when the row processing unit and the column processing unit alternately perform the process by a predetermined number of times, the communication apparatus updates the row-processing LLR and the column-processing LLR.