EP1867048A1 - Dispositif electronique - Google Patents

Dispositif electronique

Info

Publication number
EP1867048A1
EP1867048A1 EP06727751A EP06727751A EP1867048A1 EP 1867048 A1 EP1867048 A1 EP 1867048A1 EP 06727751 A EP06727751 A EP 06727751A EP 06727751 A EP06727751 A EP 06727751A EP 1867048 A1 EP1867048 A1 EP 1867048A1
Authority
EP
European Patent Office
Prior art keywords
power domain
output
electronic device
supply voltage
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06727751A
Other languages
German (de)
English (en)
Inventor
Chau B. Pham
Johannes P. M. Verdaasdonk
Michel C. Korenhof
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Priority to EP06727751A priority Critical patent/EP1867048A1/fr
Publication of EP1867048A1 publication Critical patent/EP1867048A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only

Definitions

  • the invention is related to an electronic device with a first power domain having a first supply voltage and a second power domain having a second supply voltage.
  • CMOS elements may be combined which may be operating while others will be in a steady off-state. These elements in the steady off-state also consume a certain amount of power leading to a static power consumption.
  • Fig. 4 shows a block diagram of an electronic device based on CMOS technology.
  • three different power domains A, B and C are shown which are supplied by three different supply voltages VDDl, VDD2 and VDD3, respectively.
  • VDDl supply voltage
  • VDD2 supply voltage
  • VDD3 supply voltage
  • the input signal for the power domain block C will also have a full CMOS-level, leading to minimum leakage current.
  • the supply voltage VDD2 is switched off by the switch S such that the power domain block B will not consume power. Accordingly, all outputs of the power domain blocks will be floating which can cause a significant amount of leakage current in the power domain block C.
  • JP 2002-319630 describes an efficient way to implement the switching off a second supply voltage VDD2 to a second power domain block within an electronic device having multiple power domains.
  • a static memory device is described here.
  • the current for a memory matrix is reduced to VCL2/R by an additional transistor Tl, which is controlled by a signal LM.
  • a voltage supply VCLl is switched off by a transistor T2, which is controlled by a PD signal, in order to reduce the power consumption of a circuit block 5D.
  • a supply voltage VCL2 will still be present because of the data-retention requirement.
  • the circuit has two inputs, namely A and B.
  • Two PMOS transistors PlO, Pl 1 are connected in parallel.
  • the gate of the PMOS transistor PlO is coupled to input A and the gate of the PMOS transistor Pl 1 is coupled to input B.
  • NMOS transistors Nl 2, Nl 3 are arranged, wherein the NMOS transistor Nl 3 is coupled to ground gnd and the NMOS transistor Nl 2 is coupled between the NMOS transistor Nl 3 and the output terminal Z.
  • the circuitry of Fig. 5 is used to implement an AND function, i.e. the input A as well as the input B must be high such that the output is high. Accordingly, by applying a low state to one of the input signals A or B a defined 'low' state can be achieved the output and accordingly at the input of a power domain. In other words a floating signal is overruled. However, as the output of a previous power domain is only one of the two input signal a further control signal is required. To effectively provide this control signal the information whether the power domain is switched- off or not must be known. Therefore, the provision of such a control signal is very difficult.
  • an electronic device which comprises at least one first power domain having a first supply voltage and at least one second power domain having a second supply voltage.
  • the second power domain comprises an input circuitry for coupling the output of the first power domain to the second power domain.
  • the input circuitry comprises a leakage current reduction means for reducing the leakage current through the input circuitry.
  • the leakage current reduction means is controlled by the output of the second power domain.
  • the leakage current reduction circuit is controlled by the output of the input circuitry, a feedback loop is established. Even if the circuitry is switched on, the input will correspond to a defined potential, i.e. will not be floating. Furthermore, the solution is easy to implement and is directly arranged within the respective power domain. No additional control signal will be needed.
  • the leakage current reduction means comprises an NMOS transistor which couples the input circuitry to ground. Therefore, the reduction of the leakage current can be performed by the introduction of a NMOS transistor which is controlled by the output of the second power domain.
  • the second power domain comprises a first stage and a second stage.
  • the first stage corresponds to the input circuitry.
  • the output of the first stage is coupled to the input of the second stage.
  • the first and second stage are each coupled between the second supply voltage and ground. The reduction of the leakage current can be realized by the introduction of the input circuitry in addition to the second stage.
  • Fig. Ia shows a circuit diagram of an electronic device with two power domains
  • Fig. Ib shows a cross section of a PMOS transistor Pl from Fig. Ia
  • Fig. 2 shows a circuit diagram of an electronic device according to a first embodiment
  • Fig. 3 shows a simulation of a buffer according to the state of the art as well as a buffer according to the first embodiment
  • Fig. 4 shows a block diagram of an electronic device according to the prior art
  • Fig. 5 shows a circuit diagram of an input circuitry according to the prior art.
  • Fig. Ia shows a circuit diagram of an electronic device with two power domains, supplied by the supply voltages VDDl and VDD2, respectively.
  • a first PMOS transistor Pl and second NMOS transistor Nl are coupled between the first supply voltage VDDl and ground, wherein the inputs thereof are coupled together, forming a first stage.
  • a third PMOS transistor P2 and fourth NMOS transistor N2 are coupled between the second supply voltage VDD2 and ground forming a second stage, wherein the inputs thereof are also coupled together and are furthermore connected to a signal path CS which in turn corresponds to the output of the first power domain block.
  • Fig. Ib shows a cross section of the first PMOS transistor Pl in Fig. Ia.
  • the first PMOS transistor Pl is implemented by an N- well, a p+ region for connecting the output CS and a further p+ neighboring a n+ region, which are connected to a terminal for the first supply voltage VDDl.
  • the first supply voltage VDDl as well as the second supply voltage VDD2 are set to a high level. If this circuitry is implemented by CMOS technology then the first and second supply voltage VDDl, VDD2 will correspond to 1,8 volt. However, if a power saving mode is activated, the first supply voltage VDDl is set to a VSS level, i.e. 0 volt.
  • the output signal CS of the first power domain block will be discharged via the junction diode Dl-level if the N-well is shorted to ground, i.e. approximately 0,6 - 0,7 volt.
  • the leakage current of the fourth NMOS transistor N2 in the second power domain block PD2 can impose a significant problem in accordance of the actual threshold value Vtn of the fourth NMOS transistor N2.
  • the threshold value Vtn can be 0,6 volt such that the fourth NMOS transistor N2 is in danger of conducting, when the output of the first power domain block is discharged to the level of the diode Dl, i.e. 0,6 - 0,7 volt.
  • Fig. 2 shows a circuit diagram of an electronic device according to a first embodiment.
  • the electronic device comprises a first and second power domain block PDl, PD2.
  • the first power domain block PDl corresponds to the power domain block of Fig. Ia and is supplied with a first supply voltage VDDl.
  • the second power domain block PD2 is supplied by the second power supply voltage VDD2.
  • a third PMOS transistor P2, fourth and fifth NMOS transistor N2 and N3 are coupled in series between the second supply voltage VDD2 and ground gnd.
  • the inputs of the third and fourth transistor P2, N2 are coupled together and are connected to the output CS of the first power domain block PDl .
  • the arrangement of the third and fourth transistor P2, N2 substantially corresponds to the arrangement of third and fourth transistor according to Fig. Ia.
  • a fifth NMOS transistor N3 is now coupled between ground gnd and the fourth NMOS transistor N2.
  • a sixth transistor PMOS P3 and a seventh NMOS transistor N4 are also coupled between the second supply voltage VDD2 and ground gnd, wherein their inputs are coupled together and are connected to the output P of the first stage, i.e. here the first power domain PDl, comprising the third PMOS, fourth NMOS and fifth NMOS transistor P2, N2, N3, respectively.
  • the node between the sixth and seventh transistor P3, N4 constitutes the output O of the second power domain block PD2. This output signal O is coupled to the input of the fifth transistor N3.
  • the output CS of the first power domain block PDl is in a floating level, i.e. ⁇ 0,6 volt and VDDl is set to VSS in a power saving mode.
  • the third transistor P2 will therefore be in a conducting mode and the output P of the first stage IM will become high, then the output node O will become low.
  • the NMOS transistor N3 will be switched off such that current path through the fourth NMOS transistor N2 is prevented.
  • Fig. 3 shows a simulation of a buffer Bl according to the prior art as well as a buffer B2 according to the first embodiment.
  • the voltage and on the y-axis the current is shown.
  • the leakage currents of the two buffers are shown.
  • the leakage current of a buffer B2 according to the first embodiment will only be 18 pA.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

Un dispositif électronique est proposé qui comprend au moins un premier domaine de puissance (PD1) ayant une première tension d’alimentation (VDD1) et au moins un deuxième domaine de puissance (PD2) ayant une deuxième tension d’alimentation (VDD2). Le deuxième domaine de puissance (PD2) comprend un circuit d’entrée (IM) pour coupler la sortie (CS) du premier domaine de puissance (PD1) au deuxième domaine de puissance (PD2). Le circuit d’entrée (IM) comprend un moyen de réduction du courant de fuite (N3) pour la réduction du courant de fuite à travers le circuit d’entrée (IM). Le moyen de réduction du courant de fuite (N3) est commandé au moyen de la sortie (O) du deuxième domaine de puissance (PD2).
EP06727751A 2005-03-31 2006-03-28 Dispositif electronique Withdrawn EP1867048A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP06727751A EP1867048A1 (fr) 2005-03-31 2006-03-28 Dispositif electronique

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP05102554 2005-03-31
EP06727751A EP1867048A1 (fr) 2005-03-31 2006-03-28 Dispositif electronique
PCT/IB2006/050934 WO2006103624A1 (fr) 2005-03-31 2006-03-28 Dispositif electronique

Publications (1)

Publication Number Publication Date
EP1867048A1 true EP1867048A1 (fr) 2007-12-19

Family

ID=36609311

Family Applications (1)

Application Number Title Priority Date Filing Date
EP06727751A Withdrawn EP1867048A1 (fr) 2005-03-31 2006-03-28 Dispositif electronique

Country Status (2)

Country Link
EP (1) EP1867048A1 (fr)
WO (1) WO2006103624A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103066976B (zh) * 2012-12-13 2015-05-27 广州慧智微电子有限公司 一种低关断态电流晶体管电路

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5304867A (en) * 1991-12-12 1994-04-19 At&T Bell Laboratories CMOS input buffer with high speed and low power
DE19719448A1 (de) * 1997-05-07 1998-11-12 Siemens Ag Inverterschaltung
FI20010404A0 (fi) * 2001-02-28 2001-02-28 Nokia Mobile Phones Ltd Logiikkatason siirtopiiri

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2006103624A1 *

Also Published As

Publication number Publication date
WO2006103624A1 (fr) 2006-10-05

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