EP1856804A2

EP1856804A2 - Low noise divider

Info

Publication number: EP1856804A2
Application number: EP06736045A
Authority: EP
Inventors: John Wood
Original assignee: Multigig Inc
Current assignee: Multigig Inc
Priority date: 2005-02-23
Filing date: 2006-02-23
Publication date: 2007-11-21
Also published as: WO2006091826A3; CN101199120A; WO2006091826A2; EP1856804A4

Abstract

A system and method for dividing a clock in a way that achieves low phase noise. In one embodiment, a multi-phase oscillator (20) such as a rotary traveling wave oscillator operates a state machine (26) which determines times at which a transition coupled phase signal of the multi-phase oscillator should be suppressed. Suppression of the transition is performed by a transition structure that holds the phase signal at a high or low so that the transition does not occur at the output. Fewer transitions in the ph signal create a divided clock. In another embodiment, a decoder (24) determines times for suppressing transitions in a true and complement clock and a polarity flip-flop determines the correct polarity for suppressing edges on both clocks. In yet another embodiment, a multiplexer is used to selectively pass either a true or complement clock to an output load.

Description

LOW NOISE DIVIDER

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to U.S. Provisional Application 60/656,065 titled "LOW NOISE DIVIDER," and filed on Feb. 23, 2005, which application is incorporated by reference into the present application.

FIELD OF THE INVENTION

The present invention relates generally to clock divides and more particularly to low noise clock dividers .

DESCRIPTION OF THE RELATED ART

Frequency dividers usually fall into two broad classes. One class is digital, built from flip-flop or latch-based state machines. The other is regenerative. Ones in this class resemble low-Q oscillators, tuned to a divisor of the input frequency, which pump energy into a regnerative divider, forcing it to lock to some subharmonic.

Both classes of dividers, when driven by a VCO, exhibit a theoretical phase noise spectrum that looks identical to the input phase noise spectrum of the oscillator but shifted downwards by 20 log(N) decibels. For example, if a 1 GHz VCO has a SSB phase noise of - 150 dBc/Hz at 5 MHz offset, then feeding this through a perfect divide-by-2 circuit should give a 500 MHz output with phase noise of -156 dBc/Hz at 5 MHz offset. This assumes that the divider adds no noise of its own to the output signal and also that the output signal level is well above the fundamental thermal noise floor, which sets a hard limit of -177 dBc/Hz at 0 dBm power level in a 50 ohm system. Increased power avoids this limit proportionally, e.g., +10 dBm allows a -187 dBc/Hz floor, in theory.

Digital dividers are preferred over regenerative dividers for ease of integration on- chip as they can take advantage of MOS device scaling. Regenerative dividers, on the other hand, typically include a resonant component to be pumped, such as a spiral inductor, the dimension of which is set by the L and Q needed and is non-scalable with finer process geometries.

Although digital dividers are preferred, it is difficult to achieve phase noise floors below -160 dBc/Hz with CMOS divider circuits when they are part of a complete, practical frequency synthesizer operating at low power levels. The problem comes from the phase noise generated by the uncertainty of the transition time in the switching signals as they undergo buffering and division. FIG. 1 shows a prior art clock divider system. The system includes an LC tank oscillator 10, a pair of oscillator buffers 12, and a CMOS divider 14 (using CMOS flip-flops). The LC tank oscillator 10 provides a pair of oscillator outputs, OSC and *OSC, which are buffered by the oscillator buffers 12 and divided by the CMOS divider 14. Shown in the inset of FIG. 1 is the standard CMOS buffer circuit 16 typically used within CMOS buffers and gates such as those used in a divider. These buffer circuits set the noise floor.

Low-noise designs can perhaps make use of better circuits than the simple CMOS stages including source-follower, CML gate, differential amplifier, pseudo-NMOS gates and dynamic CMOS gates, but all of these circuits have in common the feature that the FET devices spend some of their time in the highly noisy saturation region of operation with pinched-off channels causing uncertainly in edge positioning and therefore phase noise. Increasing device size can reduce the noise, but this comes at the expense of power; the oscillator, the buffer and the dividers must be up-sized far beyond the minimum and very little of the capacitance in the circuits is adiabatically driven, increasing the power needed from the supplies.

Thus, there is a need for a low phase noise regenerative divider that avoids the use of FET devices in their highly noisy regions.

BRIEF SUMMARY OF THE INVENTION The present invention is directed towards such a need. The divider has low phase noise at the divided-down frequencies of interest.

One embodiment of the present invention is a clock divider that includes a generating means, coupling means, and hold signal providing means. The generating means generates a plurality of state signals indicative of the several phases of a multi-phase oscillator in response to at least one of the phase signals of the multi-phase oscillator. The coupling means couples a phase signal of the multi-phase oscillator to an output node to provide a clock output and the providing means provides a hold signal on the output node in response to the state signals such that the output node produce a divided clock at the output, where divided clock has a frequency equal to the frequency of the multiphase oscillator divided by an integer greater than one.

Another embodiment is a clock divider that includes a generating means, a coupling means and a hold signal providing means, where the generating means generates a plurality of state signals indicative of the several phases of a multi-phase oscillator in response to at least one of the phase signals of the multi-phase oscillator, the coupling means couples a pair of phase signals of the multi-phase oscillator to a pair of output nodes to provide a true and complement clock output, and the hold signal providing means provides a pair of hold signals on the output nodes in response to the state signals such that the output nodes produce a true and complement divided clock at the output, where the divided clock has a frequency equal to the frequency of the multiphase oscillator divided by an integer greater than one. Yet another embodiment is a clock divider that includes a multiplexer, a state machine and a load. The multiplexer receives first true and complement clocks from a multi-phase oscillator and selectively passes to an output in response to a plurality of selection signals either a transition of the first true or first complement clocks or no transition. The state machine is operative to provide the selection signals to the multiplexer so as to set up the multiplexer to selectively pass a transition to the multiplexer output in response to a second true and complement clock from the multi-phase oscillator, where the second true and complement clocks lead in phase the first true and complement clocks. The load is connected to the output of the multiplexer.

Yet another embodiment is a method for dividing a clock. The method includes (i) providing a signal that indicates a set of transitions of the clock to be suppressed, (ii) coupling at least one clock signal to an output node, and (iii) actively driving the output node in response to the providing signal to suppress the set of transitions, such that the coupled signal with the set of suppressed transitions is a divided version of the clock.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where: '

FIG. 1 shows a prior art clock divider system; FIG. 2A shows a block diagram of one embodiment of a low noise clock divider;

FIG. 2B shows a circuit implementation, with waveforms, for the clock divider of FIG. 2A;

FIG. 2C is a diagram of a multi-phase rotary clock layout for use with four-transistor regeneration elements; FIG. 3A shows a block diagram of another embodiment of a low noise clock divider;

FIG. 3B shows a circuit implementation for the clock divider of FIG. 3 A; FIG. 3C shows waveforms for the various signals of FIG. 3B; and FIG. 4 shows a block diagram of yet another embodiment of a low noise clock divider. DETAILED DESCRIPTION OF THE INVENTION

FIG. 2A shows a block diagram of one embodiment of a low noise clock divider. The block diagram includes a multi-phase oscillator 20, such as a rotary traveling wave oscillator of U.S. Patent No. 6,556,089 (which is incorporated by reference into the present application), a divider structure 22, a decoder 24, a state machine 26, and clock buffers 28. A tap of the multi-phase oscillator is connected via a capacitor 30 directly to the divider structure 22, whose output is the DIVCLK. The divider structure 22 receives a pair of signals, nHoldl and HoIdO, from the decoder 24 that determine when the DIVCLK output is allowed to follow the multi-phase oscillator 20. The decoder 24 receives signals from a state machine 26 that is clocked from the multi-phase oscillator 20 along with the clocks, via the clock buffers 28, from the multi-phase oscillator 20. The state machine 26 is driven from the same pair of clocks as the decoder 24. In one version, the state machine is a "one-hot" state machine, i.e., it advances a single "1" (or "0") bit through a number of stages.

FIG. 2B shows a circuit implementation, with waveforms, for the clock divider of FIG. 2A. The clock divider structure 22 is implemented as a pair of transistors, (1) a pmos transistor 30 having its channel connected between the DIVCLK output and Vdd and (2) an nmos transistor 32 having its channel connected between the DIVCLK output and ground. The gate of the pmos transistor 30 is connected to nHoldl and the gate of the nmos transistor 32 is connected to the signal HoIdO, which are derived from the decoder 34a, b. Each decoder 34a,b is implemented as a stack of MOS transistors connected between the supply and ground. The two transistors at the top of the stack 34a are pmos transistors 40, 42 and the two at the bottom are nmos transistors 44 and 46. The two transistors at the top of the stack 34b are pmos transistor 50, 52, and the two at the bottom of the stack are nmos transistors 54, 56. The pmos transistors 40, 42, implement an AND gate of the clock CLK and a signal nQ4. The pmos transistors 50 52 implement an AND gate of the inverted clock *CLK and a signal nQ3. The nmos transistors 44, 46 implement an AND gate of the inverted clock *CLK and a signal QO. The nmos transistors 54, 56 implement an AND gate of the clock CLK and a signal Ql. In the example shown, which is a divide by 3, the HoIdO signal is goes high when CLK is low and when nQ4 from the state machine is low. This condition selects period 5 of the rotaryCLK signal, shown in the waveform section of the figure. When HoIdO is high, the nmos transistor 32 of the clock divider holds the DIVCLK signal low, preventing it from following the rotary clock. The HoIdO signal is returned low when *CLK and QO are both active high, which selects period 1 of the rotaryCLK signal. Keeping with the same example, the nHoldl signal is programmed to go low when Ql and CLK are both active high, thus selecting period 2 of the rotaryCLK signal. The nHoldl signal is programmed to go high when *CLK and nQ3 are both active low, which selects period 4 of the rotaryCLK signal. The net effect of the decoding is that the rotaryCLK edge between periods 1 and 2 and the edge between periods 4 and 5 are permitted to pass through to the DIVCLK output. This causes a divide-by-three of the rotaryCLK to appear at the DIVCLK output. It should be noted that while there may be noise caused by this decoding process on the RotaryCLK, the noise is not important for the signal of interest, which is the DIVCLK signal. In the example given, the noise is at a frequency that is three times the DIVCLK frequency. Therefore, the DIVCLK has a very low phase noise characteristic.

FIG. 2C shows a preferred layout of the rotary traveling wave oscillator and the use of four transistor regeneration elements (conditional inverters) that are shown in the insert. Two differential pairs are routed in an interleaved pattern to make quadrature clocks available as shown. Conditional inverters CI 60, 62, 64, 66 are used to decode the proper pair of quadrature clocks for regeneration of the traveling wave. For example, as the traveling approaches the tap position Tl signals b and c are decoded in CI 60 to drive a, signals d and a are decoded in CI 64 to drive c. Additionally, signals c and d are decoded in CI 62 to drive b and signals a and b are decoded in CI 66 to drive d. The advantage of this arrangement is that there is very little conduction between Vdd and GND in the CI device. (A small amount of conduction may occur due to capacitance in the conditional inverter CI.) This helps eliminate a source of phase noise on the rotary traveling wave oscillator. Furthermore, this preferred layout improves the Z to R ratio of the oscillator.

FIG. 3A shows a block diagram of another embodiment of a low noise clock divider. This embodiment is a variation of that shown in FIG. 2A. The embodiment includes a multiphase oscillator 70, such as a rotary traveling wave oscillator, a shift register 72, a decoder 74, logic circuitry 76 including a toggle flip-flop 82, a pair of three-state buffers 78, and a pair of coupling capacitors 80. A true and complement clock are tapped from the multi-phase oscillator 70 to operate the shift register 72. The decoder 74 decodes the states of the shift register 72 to provide a hold_edge signal that enables the three-state buffers 78 and drives the logic circuitry 76. The pair of coupling capacitors 80 couples a set of clocks from the multiphase oscillator to the three-state buffers 78 and the output of the circuit is taken from the output of the three-state buffers 78.

In operation, the shift register 72 keeps track of the state of the multi-phase oscillator regarding which transitions from clk45 and clk225 (the taps of the multi-phase oscillator that are to be altered by the three-state buffers 78) are to be suppressed from those clocks. At the proper time in the sequence, the hold_edge signal is asserted. This enables the three-state buffers 78 to suppress a transition on the clocks, clk45 and clk225. The hold_edge signal also operates a toggle flip-flop 82 in the logic circuitry so that the three-state buffers 78 are driven properly by the polarity signal to suppress the transition in each of the clocks.

FIG. 3B shows a circuit implementation for the clock divider of FIG. 3A and FIG. 3C shows waveforms for the various signals of FIG. 3B. The circuit implementation includes shift register 72 made from a number of flip-flops connected to form a ring, decoder 74, which includes a NAND gate, logic circuitry 76 which includes a NAND gate and a flip-flop, three-state buffers 78, coupling capacitors 80, a rotary traveling wave oscillator 70 (including regeneration elements), and a reset circuit 82. An output circuit 84 is used to obtain a high quality, low noise output. This circuit includes a pair of low noise buffers (LMH5559) for the modified clocks that are output from the three-state buffers 78, a transformer that is ac coupled, via coupling capacitors, to the low noise buffers, and a balanced load on the secondary of the transformer, one of which is an SMA connector. Other output circuits are possible.

More particularly, the shift register operates from CLK and *CLK tapped off of the rotary oscillator. NAND Gates U7 are used to decode the enable signal that determines when CLK45 and CLK225 pass through to the low noise buffers 78. The toggle flip-flop U6 is clocked from the inversion of the hold_edge signal. The 47 pf capacitors are the coupling capacitors 80. The three-state buffers U5 78 are used to block or allow the CLK45 and CLK245 signals from the rotary oscillator. The state machine 72 is a feedback shift register 72 and the decoding logic 74 consists of gate U7 which 'OR's QO and Q3 from the shift register 72 to create the hold_edge signal. A toggle-flip flop toggles on the negative edge of the hold_edge signal to create the polarity signal, which has the desired frequency. However, the polarity signal is in phase with CLK and *CLK. By using the CLK45 and the CLK225, the divide-by-three output clock is in phase with CLK 45 and CLK225 instead and the polarity signal is properly phased to control the edges of CLK46 and CLK225 that pass through the capacitors.

FIG. 3C shows waveforms for the various signals of FIG. 3B. As mentioned above, the hold_edge signal indicates that certain transitions, in this case, the transitions starting and ending interval 0.5 and the transitions starting and ending interval 2 of the CLK signal, are to be suppressed on the div3 output. The polarity signal indicates the proper polarity needed at the output of each of the three-state drivers to suppress the indicated transition. An alternative output waveform permits only the edges for the 0.5 and 2.0 CLK intervals to pass to the output. All other edges are suppressed.

FIG. 4 shows a block diagram of yet another embodiment of a low noise clock divider. This diagram includes a multi-phase oscillator 90 such as a rotary clock, a multiplexer 92, and a state machine 94. The state machine 94 receives a pair of clocks from the multi-phase oscillator 90 and generates select signals for operating the multiplexer 92. The multiplexer 92 accepts a pair of clocks from the multi-phase oscillator 90 and generates an output clock, depending on the state of the select inputs si and s2. In the example shown, a divide-by-2 circuit is implemented and the load 96 is non-edge sensitive. In that case, the multiplexer 92 has elements such as the one shown in the inset 98. At step 1, the rising edge of the CLK- signal is selected. At step 2, the output of the multiplexer 92 is disconnected from the inputs. At step 3, the falling edge of the CLK+ signal is selected. At step 4, the output of the multiplexer 92 is disconnected and at step 5, the rising edge of the CLK- signal is selected.

If the load 96 is edge-sensitive, then the multiplexer circuitry can be simplified, because the duty cycle is not important. The high time of the CLK- signal can be used to set the duty cycle of the output signal. Thus, the output signal, o (alternative) in FIG. 4, simply follows the selected clock during its high time. Preferably, the clocks that operate the state machine lead the clocks that are passed through the multiplexer, by a sufficient amount to set up the switches 98 so that the CLK+ or CLK- signals from the multi-phase oscillator pass through the multiplexer 92 without encountering a switching delay in the pass transistors. This makes the output clock have edges that are closer to the edges of the multi-phase clock. Although the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the preferred versions contained herein.

Claims

CLAIMSWhat is claimed is:

1. A clock divider comprising: means for generating a plurality of state signals indicative of the several phases of a multi-phase oscillator in response to at least one of the phase signals of the multi-phase oscillator; means for coupling a phase signal of the multi-phase oscillator to an output node to provide a clock output; and means for providing a hold signal on the output node in response to the state signals such that the output node produce a divided clock at the output, said divided clock having a frequency equal to the frequency of the multiphase oscillator divided by an integer greater than one.

2. A clock divider as recited in claim 1, wherein .said generating means includes a state machine.

3. A clock divider as recited in claim 1, wherein said coupling means includes a capacitor.

4. A clock divider as recited in claim 1, wherein said providing means includes: a decoder that decodes the states signals of the generating means to provide one or more hold control signals; and a transistor structure that is operative in response to the hold control signals to suppress a clock transition at the output node.

5. A clock divider as recited in claim 4, wherein the decoder provides two hold control signals; and wherein said transistor structure includes a PMOS transistor and an NMOS transistor, each transistor having a gate, source and drain, a channel being defined between the source and drain, said channels being connected in series between a supply voltage and ground and having a junction that connects to the output node, said gate of the NMOS transistor being connected to a first hold control signal, said gate of PMOS transistor being connected to a second hold control signal.

6. A clock divider comprising: means for generating a plurality of state signals indicative of the several phases of a multi-phase oscillator in response to at least one of the phase signals of the multi-phase oscillator; means for coupling pair of phase signals of the multi-phase oscillator to a pair of output nodes to provide a true and complement clock output; and means for providing a pair of hold signals on the output nodes in response to the state signals such that the output nodes produce a true and complement divided clock at the output, said divided clock having a frequency equal to the frequency of the multiphase oscillator divided by an integer greater than one.

7. A clock divider as recited in claim 6, wherein means for generating includes a feedback shift register.

8. A clock divider as recited in claim 6, wherein means for coupling includes a pair of capacitors.

9. A clock divider as recited in claim 6, wherein the providing means includes: a pair of three state drivers, each operative to prevent transitions in one of the coupled phase signals from occurring in response to an enable signal and a polarity signal, wherein said enable signal specifies one or more transitions of the coupled phase signals to be suppressed at the pair of output nodes and said polarity signal determines a polarity for each of the three state drivers that suppresses a transition in each of the coupled phase signals when said enable signal is activated; a decoder operative to decode the state signals to activate said enable signal; and a toggle flip-flop operative to provide said polarity signal in response to each transition of said enable signal.

10. A clock divider comprising: a state machine operative to receive one or more phase signals from a multi-phase oscillator and generate a plurality of state signals indicative of the phase signals of the multi- phase oscillator; a decoder operative to decode the plurality of state signals and generate a set of control signals; a coupling capacitor for coupling the phase signal of the multi-phase oscillator to an output node; and a divider transistor structure that receives the set of control signals and generates, in response to the control signals, on the output node, a divided clock having a frequency that is the product of the frequency of the multi-phase oscillator and the reciprocal of an integer greater than one.

11. A clock divider as recited in claim 10, wherein the divider transistor structure includes: a p-channel transistor having its channel connected between a first supply voltage and the output node and its gate connected to a first of the control signals from the decoder, and an n-channel transistor having its channel connected between a second supply voltage and the output node and its gate connected to a second of the control signals from the decoder; and wherein said first and second control signals determine times at which the output node is connected to either the first or second supply voltages or the phase signal of the multi- phase oscillator.

12. A clock divider comprising: a feedback shift register operative to generate a plurality of signals indicative of the several phases of a multi-phase oscillator in response to at least one of the phase signals of the multi-phase oscillator; a pair of coupling capacitors that couple a pair of phase signals of the multi-phase oscillator to a pair of output nodes to provide a true and complement clock output; and state circuitry that receives the set of control signals and activates, in response to the control signals, on the output node, a pair of hold signals to prevent transitions of the coupled phase signals of the multi-phase oscillator from occurring at the output nodes, such that the output nodes produce the true and complement divided clock at the output, said divided clock having a frequency equal to the frequency of the multiphase oscillator divided by an integer greater than one.

13. A clock divider as recited in claim 12, wherein the state circuitry includes a pair of three state drivers, each operative to prevent transitions in one of the coupled phase signals from occurring in response to an enable signal and a polarity signal, wherein said enable signal specifies one or more transitions of the coupled phase signals to be suppressed at the pair of output nodes and said polarity signal determines a polarity for each of the three state drivers that suppresses a transition in each of the coupled phase signals when said enable signal is active; a decoder operative to decode the signals of the feedback shift register to activate said enable signal; and a toggle flip-flop operative to provide said polarity signal in response to each transition of said enable signal.

14. A method for dividing a clock, the method comprising providing a signal that indicates a set of transitions of the clock to be suppressed; coupling at least one clock signal to an output node; and actively driving the output node in response to the providing signal to suppress the set of transitions, such that the coupled signal with the set of suppressed transitions is a divided version of the clock.

15. A clock divider comprising: a multiplexer that receives first true and complement clocks from a multi-phase oscillator, said multiplexer selectively passing to an output in response to a plurality of selection signals either a transition of the first true or first complement clocks or no transition; a state machine that is operative to provide the selection signals to said multiplexer so as to set up said multiplexer to selectively pass a transition to the multiplexer output in response to a second true and complement clock from the multi-phase oscillator, the second true and complement clocks leading in phase the first true and complement clocks; and a load connected to the output of the multiplexer.

16. A clock divider as recited in claim 15, wherein the load is transition sensitive.

17. A clock divider as recited in claim 15, wherein the load is not transition sensitive.

18. A method for dividing a clock, the method comprising providing selection signals that indicate a set of transitions of the clock to be transmitted; and selectively passing transitions of true and complement clocks of a multi-phase oscillator to an output node in response to the selection signals, such that the output signal having the transmitted transitions is a divided version of the clock.