CN101199120A - Low noise divider - Google Patents
Low noise divider Download PDFInfo
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- CN101199120A CN101199120A CNA2006800056068A CN200680005606A CN101199120A CN 101199120 A CN101199120 A CN 101199120A CN A2006800056068 A CNA2006800056068 A CN A2006800056068A CN 200680005606 A CN200680005606 A CN 200680005606A CN 101199120 A CN101199120 A CN 101199120A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/18—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance
- H03B5/1841—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance the frequency-determining element being a strip line resonator
- H03B5/1847—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance the frequency-determining element being a strip line resonator the active element in the amplifier being a semiconductor device
- H03B5/1852—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance the frequency-determining element being a strip line resonator the active element in the amplifier being a semiconductor device the semiconductor device being a field-effect device
Abstract
A system and method for dividing a clock in a way that achieves low phase noise. In one embodiment, a multi-phase oscillator such as a rotary traveling wave oscillator operates a state machine which determines times at which a transition of a coupled phase signal of the multi-phase oscillator should be suppressed. Suppression of the transition is performed by a transistor structure that holds the phase signal at a high or a low so that the transition does not occur at the output. Fewer transitions in the phase signal create a divided clock. In another embodiment, a decoder determines times for suppressing transitions in a true and complement clock and a polarity flip-flop determines the correct polarity for suppressing edges on both clocks. In yet another embodiment, a multiplexer is used to selectively pass either a true or complement clock to an output load.
Description
The cross reference of related application
The application's case is advocated the priority of the 60/656th, No. 065 U.S. Provisional Application case that is entitled as " LOW NOISE DIVIDER " of application on February 23rd, 2005, and described provisional application case is incorporated this paper by reference into.
Technical field
The present invention relates generally to clock division, and more particularly relate to the low noise Clock dividers.
Background technology
Frequency divider is divided into two big classes usually.One class is digital, puts by building based on the state machine of trigger or latch.Another kind of regeneration.This type of frequency divider be similar to be tuned to the low Q oscillator of divisor of incoming frequency, it pumps to energy in the regenerative frequency divider, forces it to lock onto certain sub-harmonic wave.
When being driven by VCO, two class frequency dividers all represent theoretic phase noise spectrum, and it looks the input phase noise spectrum that is equal to oscillator, but 20log (N) decibel that has been shifted downwards.For instance, if 1GHz VCO has in 5MHz skew place-the SSB phase noise of 150dBc/Hz, so it is presented by perfect 2 frequency dividing circuits and will be given in the 500MHz output that 5MHz skew place has the phase noise of-156 dBc/Hz.This supposition frequency divider does not add the noise of itself to output signal, and also suppose output signal level far above basic thermal noise background, and described elementary heat Noise Background has been set the hard-limiting of 0dBm power level place-177dBc/Hz in 50 ohm of systems.The power that increases is avoided this amplitude limit pro rata, for example in theory+and 10dBm permission-187dBc/Hz background.
Digital frequency divider is better than regenerative frequency divider owing to being easy to be integrated on the chip, because it can utilize the mos device convergent-divergent.On the other hand, regenerative frequency divider comprises resonance assembly to be aspirated (for example, spiral inductor) usually, and the size of described resonance assembly is set by required L and Q, and can not carry out convergent-divergent with meticulousr procedure geometric.
Although digital frequency divider is preferred, when it is difficult to as with complete, the actual frequency synthesizer of low-power level operation a part of the time be lower than-the phase noise background of 160dBc/Hz with the realization of CMOS divider circuit.Problem comes from when switching signal experience buffering and frequency division the phase noise that the uncertainty owing to the fringe time in the switching signal produces.
Fig. 1 shows prior art Clock dividers system.Described system comprises LC tank oscillator 10, a pair of oscillator buffers 12 and CMOS frequency divider 14 (using the CMOS trigger).LC tank oscillator 10 provide a pair of oscillator output OSC and
*OSC, it is by oscillator buffers 12 bufferings and by CMOS frequency divider 14 frequency divisions.Show standard CMOS buffer circuits 16 in the illustration of Fig. 1, it is used in the cmos buffer device and gate circuit that for example uses in frequency divider usually.These buffer circuits set Noise Background.
Design of Low Noise is also permitted and is utilized than the better circuit of simple CMOS level that comprises source follower, CML door, differential amplifier, pseudo-NMOS door and dynamic CMOS door, but the common trait that all these circuit have: the FET device spends the height noise zone of saturation that some times in its time are used to operate, and wherein the pinch off raceway groove causes the uncertainty in the location, edge and therefore causes phase noise.Increase the big I of device and reduce noise, but this is cost with power; Oscillator, buffer and frequency divider must arrive considerably beyond minimum dimension greatly, and the minimum electric capacity in the circuit also driven adiabaticly, thereby increase the power that power supply station needs.
Therefore, need a kind of low phase noise regenerative frequency divider, it avoids using the FET device in its height noise region.
Summary of the invention
The present invention is directed to this kind needs.Described frequency divider has low phase noise at the frequency place of relevant downward frequency division.
One embodiment of the present of invention are a kind of Clock dividers, and it comprises generation member, coupling component and inhibit signal provides member.Produce member and produce a plurality of status signals of some phase places of the described multiphase oscillator of indication with in response in the phase signal of multiphase oscillator at least one.Coupling component is coupled to output node so that clock output to be provided with the phase signal of described multiphase oscillator, and provide member on described output node, to provide inhibit signal in response to described status signal, make described output node produce frequency-dividing clock in output place, described frequency-dividing clock has the frequency that equals described multiphase oscillator divided by the frequency greater than one integer.
Another embodiment is a kind of Clock dividers, it comprises the generation member, coupling component and inhibit signal provide member, wherein produce member and produce a plurality of status signals of some phase places of the described multiphase oscillator of indication with in response in the phase signal of multiphase oscillator at least one, coupling component is coupled to a pair of output node so that true and complementary clock output to be provided with a pair of phase signal of described multiphase oscillator, and inhibit signal provides member to provide a pair of inhibit signal with in response to described status signal on described output node, make described output node produce true and complementary frequency-dividing clock in output place, described frequency-dividing clock has the frequency that equals described multiphase oscillator divided by the frequency greater than one integer.
Another embodiment is a kind of Clock dividers, and it comprises multiplexer, state machine and load.Multiplexer receives the first true and complementary clock from multiphase oscillator, and the transformation of optionally true with described first or first complementary clock or do not change is delivered to output with in response to a plurality of selection signals.State machine operation is to provide described selection signal to described multiplexer, to change the output that optionally is delivered to described multiplexer with in response to from second of described the multiphase oscillator true and complementary clock so that described multiplexer is set, the described second true and complementary clock is the leading described first true and complementary clock on phase place.Described load is connected to the output of described multiplexer.
Another embodiment is a kind of method that is used for clock is carried out frequency division.Described method comprises: one group of signal that changes that the clock of indication with suppressing (i) is provided; (ii) at least one clock signal is coupled to output node; And (iii) the described output node of active drive makes that to suppress described group of transformation in response to the described signal that provides having the described group of coupled signal through suppressing to change is the frequency division version of described clock.
Description of drawings
Consider following description, appended claims and accompanying drawing, will understand these and other feature of the present invention, aspect and advantage better, wherein:
Fig. 1 shows prior art Clock dividers system;
Fig. 2 A shows the block diagram of an embodiment of low noise Clock dividers;
The circuit embodiment with waveform of the Clock dividers of Fig. 2 B exploded view 2A;
Fig. 2 C is the figure that is used for the heterogeneous rotary clock layout used with four transistors regeneration element;
Fig. 3 A shows the block diagram of another embodiment of low noise Clock dividers;
The circuit embodiment of the Clock dividers of Fig. 3 B exploded view 3A;
The waveform of each signal of Fig. 3 C exploded view 3B; And
Fig. 4 shows the block diagram of the another embodiment of low noise Clock dividers.
Embodiment
Fig. 2 A shows the block diagram of an embodiment of low noise Clock dividers.Block diagram comprises multiphase oscillator 20 (for example rotary traveling wave oscillator of the 6th, 556, No. 089 United States Patent (USP) (incorporating the application's case by reference into)), fraction frequency device 22, decoder 24, state machine 26 and clock buffer 28.A branch of multiphase oscillator is directly connected to fraction frequency device 22 via capacitor 30, and it is output as DIVCLK.Fraction frequency device 22 receives a pair of signal nHold1 and Hold0 from decoder 24, and described signal determines when and allows DIVCLK output to follow multiphase oscillator 20.Decoder 24 is from by multiphase oscillator 20 state machine 26 received signals regularly, and via clock buffer 28 from multiphase oscillator 20 receive clocks.State machine 26 is driven by the same a pair of clock identical with decoder 24.In a version, state machine is " a heat sign indicating number (one-hot) " state machine, that is, it advances past many levels with position, single " 1 " (or " 0 ").
The circuit embodiment with waveform of the Clock dividers of Fig. 2 B exploded view 2A.Clock dividers structure 22 is implemented as pair of transistor: (1) pmos transistor 30, its raceway groove are connected between DIVCLK output and the Vdd and (2) nmos transistor 32, and its raceway groove is connected between DIVCLK output and the ground connection.The grid of pmos transistor 30 is connected to nHold1, and the grid of nmos transistor 32 is connected to signal Hold0, and described signal derives from decoder 34a, b.Each decoder 34a, b are implemented as piling up of the MOS transistor that is connected between power supply and the ground connection.Two transistors that pile up 34a top place are pmos transistors 40,42, and two of place, bottom are nmos transistor 44 and 46.Two transistors that pile up 34b top place are pmos transistors 50,52, and to pile up two of place, bottom be nmos transistor 54 and 56.Pmos transistor 40,42 is implemented the AND door of clock CLK and signal nQ4.Pmos transistor 50,52 is implemented the counter-rotating clock
*The AND door of CLK and signal nQ3.Nmos transistor 44,46 is implemented the counter-rotating clock
*The AND door of CLK and signal Q0.Nmos transistor 54,56 is implemented the AND door of clock CLK and signal Q1.Shown in 3 frequency division examples in, when CLK be low and when from the nQ4 of state machine when low, the Hold0 signal becomes height.This situation is selected the cycle 5 of rotation CLK signal, as shown in the waveform segment of figure.As Hold0 when being high, the nmos transistor 32 of Clock dividers remains the DIVCLK signal low, prevents that it from following rotary clock.When
*CLK and Q0 are effective when high, and the Hold0 signal returns low, and it selects the cycle 1 of rotation CLK signal.Still referring to same instance, the nHold1 signal is programmed for effectively becomes when high lowly when Q1 and CLK are, therefore select cycle 2 of rotation CLK signal.NHold1 signal program bit is worked as
*CLK and nQ3 are and become height when effectively hanging down, and it selects the cycle 4 of rotation CLK signal.The clean effect of decoding is that rotation CLK edge and the edge transfer between cycle 4 and 5 between permission cycle 1 and 2 exported to DIVCLK.This impels the three frequency division of rotation CLK to appear at DIVCLK output place.Although it should be noted that the noise that may exist on the CLK decode procedure thus to cause in rotation, described noise is unimportant for coherent signal (DIVCLK signal).In the example that provides, noise is in the frequency place that is three times in the DIVCLK frequency.Therefore, DIVCLK has low-down phase noise characteristic.
The use of four transistors regeneration elements (condition inverter) of showing in the preferable layout of Fig. 2 C displaying rotary traveling wave oscillator and the illustration.With two differential pairs of interlaced pattern route to obtain available orthogonal clock as shown.The orthogonal clock that it is suitably right that condition inverter CI 60,62,64,66 is used to decode is to be used to the capable ripple of regenerating.For instance, advancing when approaching branch location T1, decoded signal b and c are to drive a in CI 60, and decoded signal d and a are to drive c in CI 64.In addition, in CI 62 decoded signal c and d driving b, and in CI 66 decoded signal a and b to drive d.The advantage of this configuration is to have few conduction between the Vdd and GND in the CI device.(owing to the electric capacity among the condition inverter CI a small amount of conduction may take place.) this helps to eliminate the source of phase noise on the rotary traveling wave oscillator.In addition, this preferable layout has been improved the Z of oscillator and the ratio of R.
Fig. 3 A shows the block diagram of another embodiment of low noise Clock dividers.This embodiment is the variant of Fig. 2 A illustrated embodiment.Described embodiment comprises multiphase oscillator 70 (for example rotary traveling wave oscillator), shift register 72, decoder 74, the logical circuit 76 that comprises two-position toggle switch 82, a pair of tristate buffer 78 and a pair of coupling capacitor 80.From true and complementary clock of multiphase oscillator 70 taps with operate shift register 72.The state of decoder 74 decode shift register 72 is to provide hold_edge signal, and it enables tristate buffer 78 and drive logic 76.Describedly will be coupled to tristate buffer 78 from one group of clock of multiphase oscillator, and obtain the output of circuit from the output of tristate buffer 78 coupling capacitor 80.
In operation, shift register 72 about will be from clock clk45 and clk225 (branch that will change by tristate buffer 78 of multiphase oscillator) inhibition follow the tracks of the state of multiphase oscillator from which transformation of described clock.Appropriate time in sequence is established the hold_edge signal.This enables tristate buffer 78 to suppress the transformation on clock clk45 and the clk225.The hold_edge signal is the two-position toggle switch 82 in the operation logic circuit also, makes suitably to drive tristate buffer 78 by polar signal, to suppress the transformation in each described clock.
The circuit embodiment of the Clock dividers of Fig. 3 B exploded view 3A, and the waveform of each signal of Fig. 3 C exploded view 3B.The circuit embodiment comprises by the shift register of forming with the many triggers that form ring through connection 72, the decoder 74 that comprises the NAND door, the logical circuit 76 that comprises NAND door and trigger, tristate buffer 78, coupling capacitor 80, rotary traveling wave oscillator 70 (comprising the regeneration element) and resets circuit 82.Output circuit 84 is used to obtain high-quality, low noise output.This circuit comprises a pair of low noise buffers (LMH5559) that is used for from the modification clock of tristate buffer 78 output, be coupled to the balanced load on the secondary side of the transformer of low noise buffers and transformer via coupling capacitor ac, and one in the described balanced load is SMA connectors.Other output circuit is possible.
More particularly, shift register according to the CLK that breaks away from gyrate shaker branch and
*The CLK operation.NAND door U7 is used to the enable signal of decoding, and described signal determines when CLK45 and CLK225 are delivered to low noise buffers 78.Two-position toggle switch U6 comes regularly by the counter-rotating of hold_edge signal.Coupling capacitor 80 is 47pf capacitors.Tristate buffer U5 78 is used to block or allow CLK45 and the CLK245 signal from gyrate shaker.State machine 72 is feedback shift registers 72, and decode logic 74 is made up of door U7, and described door U7 carries out " exclusive disjunction " to produce the hold_edge signal to Q0 and the Q3 from shift register 72.Two-position toggle switch bifurcation on the marginal edge of hold_edge signal triggers the polar signal that has the frequency of being wanted with generation.Yet, described polar signal and CLK and
*The CLK homophase.By using CLK45 and CLK225, three frequency division output clock alternatively with CLK 45 and CLK225 homophase, and polar signal through suitable phase modulation with control by the CLK46 of capacitor and the edge of CLK225.
The waveform of each signal of Fig. 3 C exploded view 3B.Mention as mentioned, the hold_edge signal indicates some transformation (the transformation start and end time interval 0.5 of CLK signal and transformation start and end time interval 2 in the case) to be suppressed in div3 output.Polar signal indication output place of each in described three-state driver needs in order to suppress the suitable polarity of indicated transformation.The output waveform that substitutes only allow 0.5 and the edge transfer in the 2.0CLK time interval to output.All other edges are suppressed.
Fig. 4 shows the block diagram of the another embodiment of low noise Clock dividers.This figure comprises multiphase oscillator 90 (for example, rotary clock), multiplexer 92 and state machine 94.The a pair of clock that state machine 94 receives from multiphase oscillator 90, and produce the selection signal that is used to operate multiplexer 92.The a pair of clock that multiplexer 92 receives from multiphase oscillator 90, and foundation is selected the state of input s1 and s2 and is produced the output clock.In the example shown, implement 2 frequency dividing circuits, and 96 pairs of edges of load are insensitive.In the case, multiplexer 92 has for example element of the element shown in the illustration 98.In step 1, select the rising edge of CLK-signal.In step 2, disconnect the output of multiplexer 92 from input.In step 3, select the trailing edge of CLK+ signal.In step 4, disconnect the output of multiplexer 92, and, select the rising edge of CLK-signal in step 5.
If 96 pairs of edge sensitive of load can be simplified multiplexer circuit, so because duty cycle is inessential.The CLK-signal is the duty cycle that the high time can be used for setting output signal.Therefore, the output signal o among Fig. 4 (replacing) only follows selected clock at it for high time durations.
Preferably, the clock of state machine is the enough amounts of clock by multiplexer in advance, so that switch 98 to be set, make can not meet with switching delay in the turn-on transistor by multiplexer 92 from the CLK+ of multiphase oscillator or CLK-signal.This makes the output clock have the edge near the edge of multi-phase clock.
Although described in detail the present invention with reference to some preferred version of the present invention, other version also is possible.Therefore, the spirit and scope of claims should not be limited to the description of the preferred version that this paper is comprised.
Claims (18)
1. Clock dividers, it comprises:
Produce member, its a plurality of status signals of some phase places that are used for producing the indication multiphase oscillator are with in response at least one of the phase signal of described multiphase oscillator;
Coupling component, it is used for the phase signal of described multiphase oscillator is coupled to output node so that clock output to be provided; And
Member is provided, it is used for providing on described output node inhibit signal with in response to described status signal, make described output node produce frequency-dividing clock in described output place, described frequency-dividing clock has the frequency that equals described multiphase oscillator divided by the frequency greater than one integer.
2. Clock dividers according to claim 1, wherein said generation member comprises state machine.
3. Clock dividers according to claim 1, wherein said coupling component comprises capacitor.
4. Clock dividers according to claim 1, the wherein said member that provides comprises:
Decoder, the described status signal of its described generation member of decoding is to provide one or more retentive control signals; And
Transistor arrangement, it changes with the clock that suppresses described output node place in response to described retentive control signal through operation.
5. Clock dividers according to claim 4,
Wherein said decoder provides two retentive control signals; And
Wherein said transistor arrangement comprises a PMOS transistor and a nmos pass transistor, each transistor has grid, source electrode and drain electrode, between described source electrode and drain electrode, define raceway groove, described raceway groove is connected in series between supply voltage and the ground connection, and has the node that is connected to described output node, the described grid of described nmos pass transistor is connected to the first retentive control signal, and the transistorized described grid of described PMOS is connected to the second retentive control signal.
6. Clock dividers, it comprises:
Produce member, its a plurality of status signals of some phase places that are used for producing the indication multiphase oscillator are with in response at least one of the phase signal of described multiphase oscillator;
Coupling component, it is used for the phase signal of described multiphase oscillator is exported so that true and complementary clock to be provided being coupled to a pair of output node; And
Member is provided, it is used for providing on described output node a pair of inhibit signal with in response to described status signal, make described output node produce true and complementary frequency-dividing clock in described output place, described frequency-dividing clock has the frequency that equals described multiphase oscillator divided by the frequency greater than one integer.
7. Clock dividers according to claim 6, wherein said generation member comprises feedback shift register.
8. Clock dividers according to claim 6, wherein said coupling component comprises a pair of capacitor.
9. Clock dividers according to claim 6, the wherein said member that provides comprises:
A pair of three-state driver, its each generation in operating with one in the phase signal that prevents described coupling changes to come in response to enable signal and polar signal, wherein said enable signal is specified will be in described one or more transformations that the output node place suppressed the phase signal of described coupling, and described polar signal is identified for each the polarity in the described three-state driver, when activating described enable signal, described polarity suppresses the transformation in the phase signal of described coupling each;
Decoder, it is through operating with the described status signal of decoding to activate described enable signal; And
Two-position toggle switch, it is through operating to provide described polar signal next each transformation in response to described enable signal.
10. Clock dividers, it comprises:
State machine, it receiving one or more phase signals from multiphase oscillator, and produces a plurality of status signals of the phase signal of the described multiphase oscillator of indication through operation;
Decoder, its through operation to decode described a plurality of status signal and produce one group of control signal;
Coupling capacitor, it is used for the phase signal of described multiphase oscillator is coupled to output node; And
The frequency divider transistor arrangement, it receives described group of control signal, and on described output node, producing frequency-dividing clock in response to described control signal, described frequency-dividing clock has the frequency that equals described multiphase oscillator and frequency greater than the product of the inverse of one integer.
11. Clock dividers according to claim 10,
Wherein said frequency divider transistor arrangement comprises:
P channel transistor, its raceway groove are connected between first supply voltage and the described output node, and its grid is connected to from first in the described control signal of described decoder; And
N channel transistor, its raceway groove are connected between second source voltage and the described output node, and its grid be connected to from in the described control signal of described decoder the two; And
Wherein said first and second control signals determine that described output node is connected to described first or time of the phase signal of second source voltage or described multiphase oscillator.
12. a Clock dividers, it comprises:
Feedback shift register, its through operation with a plurality of signals of some phase places of producing the indication multiphase oscillator with in response in the phase signal of described multiphase oscillator at least one;
A pair of coupling capacitor, its a pair of phase signal with described multiphase oscillator is coupled to a pair of output node, so that true and complementary clock output to be provided; And
Status circuit, it receives one group of control signal, and on described output node, activate a pair of inhibit signal in response to described control signal, phase signal with the described coupling that prevents described multiphase oscillator changes at described output node place, make described output node produce true and complementary frequency-dividing clock in described output place, described frequency-dividing clock has the frequency that equals described multiphase oscillator divided by the frequency greater than one integer.
13. Clock dividers according to claim 12, wherein said status circuit comprises:
A pair of three-state driver, its each generation in operating with one in the phase signal that prevents described coupling changes to come in response to enable signal and polar signal, wherein said enable signal is specified will be in described one or more transformations that the output node place suppressed the phase signal of described coupling, and described polar signal is identified for each the polarity in the described three-state driver, when described enable signal was effective, described polarity suppressed the transformation in the phase signal of described coupling each;
Decoder, its through operation with the signal of the described feedback shift register of decoding to activate described enable signal; And
Two-position toggle switch, it is through operating to provide described polar signal next each transformation in response to described enable signal.
14. a method that is used for clock is carried out frequency division, described method comprises:
The signal with repressed one group of transformation of the described clock of indication is provided;
At least one clock signal is coupled to output node; And
The described output node of active drive makes that to suppress described group of transformation in response to the described signal that provides the coupled signal with described group of repressed transformation is the frequency division version of described clock.
15. a Clock dividers, it comprises:
Multiplexer, it receives the first true and complementary clock from multiphase oscillator, the transformation of described multiplexer or first complementary clock optionally true with described first in response to a plurality of selection signals or do not change and be delivered to output;
State machine, it is through operating so that described selection signal is provided to described multiplexer, optionally transformation is delivered to the output of described multiplexer with in response to from second of described the multiphase oscillator true and complementary clock so that described multiplexer is set, the described second true and complementary clock is the leading described first true and complementary clock on phase place; And
Load, it is connected to the output of described multiplexer.
16. Clock dividers according to claim 15, wherein said load is to changing sensitivity.
17. Clock dividers according to claim 15, wherein said load is insensitive to changing.
18. a method that is used for clock is carried out frequency division, described method comprises:
One group of selection signal that changes that will be transmitted of the described clock of indication is provided; And
The transformation of the true and complementary clock of multiphase oscillator optionally is delivered to output node with in response to described selection signal, makes that the output signal with described transformation that is transmitted is the frequency division version of described clock.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US65606505P | 2005-02-23 | 2005-02-23 | |
| US60/656,065 | 2005-02-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101199120A true CN101199120A (en) | 2008-06-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006800056068A Pending CN101199120A (en) | 2005-02-23 | 2006-02-23 | Low noise divider |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP1856804A4 (en) |
| CN (1) | CN101199120A (en) |
| WO (1) | WO2006091826A2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103988407A (en) * | 2011-12-12 | 2014-08-13 | 美国亚德诺半导体公司 | RTWO-based pulse width modulator |
| CN110226148A (en) * | 2017-02-24 | 2019-09-10 | 超威半导体公司 | Clock dividers devices and methods therefor |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8742857B2 (en) * | 2008-05-15 | 2014-06-03 | Analog Devices, Inc. | Inductance enhanced rotary traveling wave oscillator circuit and method |
| US11264949B2 (en) | 2020-06-10 | 2022-03-01 | Analog Devices International Unlimited Company | Apparatus and methods for rotary traveling wave oscillators |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2666706B1 (en) * | 1990-09-12 | 1993-08-06 | Sgs Thomson Microelectronics | FAST COUNTER / DIVIDER AND APPLICATION TO A SWALLOW COUNTER. |
| US6114914A (en) * | 1999-05-19 | 2000-09-05 | Cypress Semiconductor Corp. | Fractional synthesis scheme for generating periodic signals |
-
2006
- 2006-02-23 WO PCT/US2006/006619 patent/WO2006091826A2/en active Search and Examination
- 2006-02-23 CN CNA2006800056068A patent/CN101199120A/en active Pending
- 2006-02-23 EP EP06736045A patent/EP1856804A4/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103988407A (en) * | 2011-12-12 | 2014-08-13 | 美国亚德诺半导体公司 | RTWO-based pulse width modulator |
| CN103988407B (en) * | 2011-12-12 | 2016-12-21 | 美国亚德诺半导体公司 | Pulse-width modulator based on RTWO |
| CN110226148A (en) * | 2017-02-24 | 2019-09-10 | 超威半导体公司 | Clock dividers devices and methods therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1856804A2 (en) | 2007-11-21 |
| WO2006091826A3 (en) | 2006-12-21 |
| WO2006091826A2 (en) | 2006-08-31 |
| EP1856804A4 (en) | 2008-10-15 |
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Open date: 20080611 |