EP1837905A2 - Verbindungsstruktur mit Hohlräumen im Dielektrikum - Google Patents

Verbindungsstruktur mit Hohlräumen im Dielektrikum Download PDF

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Publication number
EP1837905A2
EP1837905A2 EP07112163A EP07112163A EP1837905A2 EP 1837905 A2 EP1837905 A2 EP 1837905A2 EP 07112163 A EP07112163 A EP 07112163A EP 07112163 A EP07112163 A EP 07112163A EP 1837905 A2 EP1837905 A2 EP 1837905A2
Authority
EP
European Patent Office
Prior art keywords
layer
polymer
interconnect stack
trench
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07112163A
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English (en)
French (fr)
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EP1837905A3 (de
Inventor
Joaquin Torres
Laurent-Georges Gosset
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Crolles 2 SAS
NXP BV
Original Assignee
STMicroelectronics Crolles 2 SAS
NXP BV
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Crolles 2 SAS, NXP BV, Koninklijke Philips Electronics NV filed Critical STMicroelectronics Crolles 2 SAS
Priority to EP07112163A priority Critical patent/EP1837905A3/de
Publication of EP1837905A2 publication Critical patent/EP1837905A2/de
Publication of EP1837905A3 publication Critical patent/EP1837905A3/de
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to the fabrication of integrated circuits, and in particular, the invention relates to integration and control of IC interconnect air cavities within interconnect stacks.
  • a semiconductor device such as an IC (integrated circuit) has electronic circuit elements such as transistors, diodes and resistors fabricated integrally on a single body of semiconductor material. Advances in semiconductor materials and processing techniques have resulted in reducing the overall size of the IC circuit elements while increasing their number on a single body. Additional miniaturization is highly desirable for improved IC performance and cost reduction.
  • VLSI Very Large Scale Integrated
  • ULSI Ultra-Large Scale Integrated
  • Conductive vias are formed in the interlevel dielectric to provide interlevel contacts between the wiring traces and form vertical connections between the electronic circuit elements, resulting in layered connections.
  • RC time constants are due to RC time constants ('R' is the resistance of the on-chip wiring, and 'C' is the effective capacitance between the signal lines and the surrounding conductors in the multilevel interconnection stack).
  • RC time constants are reduced by lowering the specific resistance of the wiring material, and by using interlevel and intralevel dielectrics (ILDs) with lower dielectric constants k.
  • a typical metal/dielectric combination for low RC interconnect structures is copper (Cu) with a dielectric such as silicon dioxide SiO 2 (dielectric constant of about 4.0).
  • metal patterns which are inset in a layer of dielectric, are formed by the steps of etching holes (for vias) or trenches (for wiring) into the interlevel or intralevel dielectric, optionally, lining the holes or trenches with one or more adhesion or diffusion barrier layers, overfilling the holes or trenches with a metal wiring material (e.g., copper), and removing the metal overfill by a planarizing process such as chemical-mechanical polishing (CMP), leaving the metal even with the upper surface of the dielectric.
  • CMP chemical-mechanical polishing
  • Dual damascene Fabrication of interconnect structures by damascene processing can be substantially simplified by using a process variation known as "dual damascene," in which patterned cavities for the wiring level and its underlying via level are filled in with metal in the same deposition step. Dual damascene reduces the number of metal polishing steps by a factor of two, providing substantial cost savings. Dual damascene simply includes forming a trench and an underlying via hole.
  • low k dielectric materials are in heavy demand as they reduce the capacitance between interconnects and improve the switching speed of IC's.
  • one or more low k dielectric materials are deposited and pattern etched to form the vertical interconnects, e.g., vias, and horizontal interconnects, e.g., lines.
  • BEOL back-end-of-line
  • integration schemes for forming air cavities within an interconnect stack are based on a removal technique, adapted to the sacrificial material used for the integration. For example, on an interconnect stack 10 as shown in FIG.
  • a region 24 is specified for the introduction of air cavities (see FIG. 1B).
  • the region 24 is found only in dense areas with narrow lines, where the best and highest propagation performances are required (FIG. 1 B).
  • FIG. 1 B An example of a resulting stack after a diluted HF attack mechanism has been performed is illustrated in Fig. 1 B, in association with the hard mask 18 with the large open area 24 to define the surface region of the stack 10 initially exposed to the HF attack 20.
  • the cavities 22 are first introduced at the upper-metal level.
  • the regions with the air cavities 22 may become much larger than initially required (FIG. 1B).
  • the treatment duration may affect the metal line integrity due to the long removal process, for example, the long HF attack 20 exposure in the case of TiN (Titanium Nitride), a Physical Vapor Deposition technique such as Vacuum Deposited Coating, or TaN Cu (Tantalum Nitride Copper seed) diffusion barriers may affect the copper interconnect reliability.
  • TiN Tianium Nitride
  • a Physical Vapor Deposition technique such as Vacuum Deposited Coating
  • TaN Cu Talum Nitride Copper seed
  • the invention aims to provide a solution to these problems.
  • one object of the invention is to provide a method of fabricating an integrated circuit by the steps of providing an interconnect stack having a substrate with at least one layer of sacrificial dielectric material formed thereon; of etching at least a trench in the dielectric layer; depositing polymer material to form a polymer liner within the trench; of removing excess polymer material so that the polymer liner remains at least on an edge of the trench; at least partially filling the trench with a metallization layer; of planarizing the interconnect stack by removing any overfill of said metallization layer; and of forming a self-aligned barrier above the metallization layer to finally form at least one air cavity within the interconnect stack by partially removing the sacrificial dielectric material using a removal agent.
  • method also includes repeating as many times as there are levels in the interconnect stack, the steps of etching the trench in the dielectric layer, depositing the polymer material liner within the trench, removing the excess polymer liner, partially filling the trench with the metallization layer, planarizing the interconnect stack, and forming the self-aligned barrier, prior to the step of forming the air cavity.
  • the polymer liner includes a material comprising at least one low dielectric constant organic polymer resin.
  • the low-dielectric constant organic polymer resin may include an aromatic hydrocarbon based polymer material or a benzocyclobutene based material.
  • partially removing the sacrificial dielectric material includes isotropically treating the dielectric material using a wet or gaseous chemical treatment to remove the sacrificial dielectric material.
  • the method further includes defining a portion on the surface of the substrate of the stack as being specific to air cavity introduction and the defined portion is smaller than the surface of the substrate.
  • the sacrificial dielectric material within the interconnect stack includes a multi-layer structure made of a hybrid material having a low or ultra-low dielectric constant material and a permeable material permitting diffusion of the removal agent through it.
  • the method may also include replacing the steps of removing the polymer liner, filling the trench with the metallization layer, and forming the self-aligned barrier with the steps of depositing a hard mask on a surface of the interconnect stack prior to depositing the permeable polymer layer to fill the trench; removing the excess permeable polymer layer including the hard mask layer; and depositing another hard mask layer and etching therein a defined area for the diffusion of the removal agent.
  • an integrated circuit includes a semiconductor interconnect stack having at least one sacrificial dielectric material; at least one trench (26) in the dielectric layer; a polymer liner deposited on an edge of the trench that is subsequently partially filled with a metallization layer; a self-aligned barrier formed above a planarized metallization layer having no overfill of said metallization layer; and at least one air cavity within the interconnect stack formed by partially removing the sacrificial dielectric material by using a removal agent.
  • the polymer liner is a material based on low-dielectric constant organic polymer resins.
  • the low-dielectric constant organic polymer resin includes an aromatic hydrocarbon based polymer material or a benzocyclobutene based material.
  • the sacrificial dielectric material within the interconnect stack is a multi-layer structure made of a hybrid material having a low or ultra-low dielectric constant material and a permeable material permitting diffusion of the removal agent through it.
  • Embodiments may have one or more of the following advantages.
  • the present method provides an improved integrated circuit and integrated circuit fabrication method to introduce highly controlled air cavities within high-speed copper interconnects based on the introduction of a polymer material on the edges of the interconnect lines and vias within the interconnect stack, which incorporates and controls air cavities formation, thus enhancing the signal propagation performances of the semiconductor interconnects.
  • the interconnect stack includes the substrate 12 that supports a dielectric liner 13 (e.g., SiN or SiC), a sacrificial layer of dielectric material 16 (e.g., UGS SiO 2 ) another dielectric hard mask liner 18 and a lithographic etching layer 19.
  • a dielectric liner 13 e.g., SiN or SiC
  • a sacrificial layer of dielectric material 16 e.g., UGS SiO 2
  • another dielectric hard mask liner 18 e.g., UGS SiO 2
  • a lithography process is carried out on the interconnect stack 10 to pattern several trenches 26.
  • a thin liner of low-dielectric constant organic polymer resin 27 either SiLK TM (aromatic hydrocarbon based polymer) or BCB TM (benzocyclobutene), both manufactured by Dow Chemical® of Midland (Michigan), USA, is deposited using CVD (chemical vapour deposition) or PECVP (plasma enhanced chemical vapour deposition) techniques on the surface 28 of the interconnect stack 10 (FIG. 2C).
  • the liner 27 remains only on the edges 26a of the trenches 26 but not on the bottom 26b of the trenches 26, as illustrated in FIG. 2D.
  • the organic polymer chosen has the characteristics of permitting a high HF diffusion or attack on the interconnect stack 10.
  • a metallization step depositing a layer of copper metal 14 is carried out, immediately followed by a copper layer processing, namely, a CMP (chemical mechanical polishing) process.
  • CMP is an enabling technology for copper damascene providing adequate local and global surface planarization (see FIG. 2F).
  • a self-aligned barrier (SAB) 30 such as CoWP (cobalt tungsten phosphide) cap is deposited above the metal lines 14 to encapsulate the copper and protect it from the next removal treatment (FIG. 2G).
  • a HF diffusion or attack 20 is carried out by submitting the interconnect stack 10 to a chemical treatment, for example, the HF removal treatment, by either wet or gaseous means, as illustrated in FIG. 2H1.
  • the HF removal treatment by either wet or gaseous means, as illustrated in FIG. 2H1.
  • the HF diffuses through the polymer line 27 to the lower regions of the stack 10
  • the removal of the sacrificial layer of dielectric material 16 e.g., UGS SiO 2
  • the USG layer 16 is completely removed from the interconnect stack 10 (FIG. 2H2).
  • FIG. 3A shows a defined portion 52 on a surface 51 of the substrate 12 of the integrated circuit interconnect stack 50 as being specific to air cavity introduction, with the defined portion 52 being smaller than an area 51 of the interconnect stack 50.
  • the metal lines will be less exposed or submitted to the removal agent HF, as illustrated in FIGs. 3B and 3C1. Consequently, air cavities formation will be more expeditious and gentler than if it had been carried out using conventional standard integration procedures without the presence of the polymer SiLK TM or BCB TM layer 27. Furthermore, it also limits the distribution of the air cavities 22 within the interconnect stack. This contrast can be seen by comparing FIG. 3C1 and FIG. 3C2, where in the latter illustration, no polymer SiLK TM or BCBTM layer 27 has been added. In other words, the air cavities 22 formation process can be advantageously less design dependent in the case of FIG. 3C1.
  • Another optimization that can be performed is to completely remove the remaining SiLK TM or BCB TM layer 27 within the air cavity area 22 of the interconnect stack 10 by using an adapted process if keeping the polymer layers within the air cavities in terms of mechanical stability enhancement is unnecessary or not advantageous.
  • the integration control and reliability enhancement associated with the present invention can also be implemented with multi-layers within the interconnect stack 50 made of a hybrid material such as an USG layer in addition to a permanent porous permeable layer made of SiLK TM material that allows the diffusion of HF through it.
  • IMD intrametal dielectric
  • ILD Intermetal dielectric
  • ILD Interlevel dielectric
  • metal dummies such as lines or via can be implemented by design in the right areas to fasten the HF diffusion to the lower metal levels of the interconnect.
  • the permeable material used in this optimization is typically SiLKTM or BCBTM, which allows the fast diffusion of the removal agent (i.e., HF) from the top through another interconnect stack 55.
  • the total duration for the removal of the USG layer 16 at multi level stacks is significantly shortened. That is, the total duration for the entire removal time is approximately equivalent to the removal time of the sacrificial layer/material 16 at the upper metal level.
  • the interconnect stack 55 is shown with a hard mask 18 deposition (SiC, SiN, etc).
  • the layers of the interconnect 55 include a substrate 12 followed by the hard mask layer 18, a permeable permanent layer of polymer 57, followed by a USG layer 16.
  • a deep trench 26 is formed from a surface 56 of the interconnect stack 55 all the way to a bottom 59, through the complete interconnect stack 55 (FIG. 4B).
  • a deposition step takes place with the dielectric polymer 57 (SiLK TM or BCB TM ) filling the trench 26 (FIG. 4C) all the way down to the bottom 59.
  • a chemical mechanical polishing technique 60 is applied to smooth out the surface 56 of the interconnect stack 55 (FIG. 4D), with the resulting stack with the hard mask 18 removed.
  • a SiC hard mask 61 deposition is performed followed by an etching process of a large area 63 for a subsequent HF diffusion 65 (FIGs. 4E-4F). Since the HF 65 rapidly diffuses through the permeable polymer layers 57, the removal of the USG layers 16 is quasi simultaneously carried out at each of the metal levels, as represented by arrows 67.
  • the final resulting interconnect stack 55 is shown in FIG. 4F with the air cavities 22 formed throughout the stack in between the metal lines.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
EP07112163A 2005-07-12 2006-06-21 Verbindungsstruktur mit Hohlräumen im Dielektrikum Withdrawn EP1837905A3 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP07112163A EP1837905A3 (de) 2005-07-12 2006-06-21 Verbindungsstruktur mit Hohlräumen im Dielektrikum

Applications Claiming Priority (3)

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EP05291505 2005-07-12
EP07112163A EP1837905A3 (de) 2005-07-12 2006-06-21 Verbindungsstruktur mit Hohlräumen im Dielektrikum
EP06291019A EP1744359A1 (de) 2005-07-12 2006-06-21 Verbindungsstruktur mit Aushöhlungen in ihrem dielektrischen Bereich

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EP1837905A2 true EP1837905A2 (de) 2007-09-26
EP1837905A3 EP1837905A3 (de) 2008-12-31

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EP06291019A Withdrawn EP1744359A1 (de) 2005-07-12 2006-06-21 Verbindungsstruktur mit Aushöhlungen in ihrem dielektrischen Bereich
EP07112163A Withdrawn EP1837905A3 (de) 2005-07-12 2006-06-21 Verbindungsstruktur mit Hohlräumen im Dielektrikum

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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7919388B2 (en) 2008-05-30 2011-04-05 Freescale Semiconductor, Inc. Methods for fabricating semiconductor devices having reduced gate-drain capacitance
US7838389B2 (en) 2008-05-30 2010-11-23 Freescale Semiconductor, Inc. Enclosed void cavity for low dielectric constant insulator
DE102010006769A1 (de) * 2010-02-04 2014-10-30 Dominik Mösch Verfahren zur Herstellung von kleinen Hohlräumen oder Maskierungen/Strukturen in der Halbleiterindustrie, Mikroelektronik, Mikrosystemtechnik o.ä. anhand von Substanzen mit einem geringen Schmelz- und Siedepunkt

Citations (4)

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Publication number Priority date Publication date Assignee Title
DE10227663A1 (de) * 2002-06-20 2004-01-15 Infineon Technologies Ag Verfahren zum Versiegeln poröser Materialien bei der Chipherstellung und Verbindungen hierfür
US20050037604A1 (en) * 2000-02-08 2005-02-17 International Business Machines Corporation Multilayer interconnect structure containing air gaps and method for making
US20050067673A1 (en) * 2003-09-30 2005-03-31 International Business Machines Corporation Adjustable self-aligned air gap dielectric for low capacitance wiring
US20050127514A1 (en) * 2003-12-08 2005-06-16 Ibm Line level air gaps

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US7294934B2 (en) * 2002-11-21 2007-11-13 Intel Corporation Low-K dielectric structure and method
US6924222B2 (en) * 2002-11-21 2005-08-02 Intel Corporation Formation of interconnect structures by removing sacrificial material with supercritical carbon dioxide
US6861332B2 (en) * 2002-11-21 2005-03-01 Intel Corporation Air gap interconnect method
US6875685B1 (en) * 2003-10-24 2005-04-05 International Business Machines Corporation Method of forming gas dielectric with support structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050037604A1 (en) * 2000-02-08 2005-02-17 International Business Machines Corporation Multilayer interconnect structure containing air gaps and method for making
DE10227663A1 (de) * 2002-06-20 2004-01-15 Infineon Technologies Ag Verfahren zum Versiegeln poröser Materialien bei der Chipherstellung und Verbindungen hierfür
US20050067673A1 (en) * 2003-09-30 2005-03-31 International Business Machines Corporation Adjustable self-aligned air gap dielectric for low capacitance wiring
US20050127514A1 (en) * 2003-12-08 2005-06-16 Ibm Line level air gaps

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EP1744359A1 (de) 2007-01-17
EP1837905A3 (de) 2008-12-31

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