Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/16—Error detection or correction of the data by redundancy in hardware
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30181—Instruction operation extension or modification
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/16—Error detection or correction of the data by redundancy in hardware
  • G06F11/1629—Error detection by comparing the output of redundant processing systems
  • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/16—Error detection or correction of the data by redundancy in hardware
  • G06F11/1695—Error detection or correction of the data by redundancy in hardware which are operating with time diversity
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F15/00—Digital computers in general; Data processing equipment in general
  • G06F15/76—Architectures of general purpose stored program computers
  • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30181—Instruction operation extension or modification
  • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
  • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/46—Multiprogramming arrangements
  • G06F9/48—Program initiating; Program switching, e.g. by interrupt
  • G06F9/4806—Task transfer initiation or dispatching
  • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
  • G06F2201/845—Systems in which the redundancy can be transformed in increased performance

Definitions

• Dual-core architectures are also used in other applications to increase performance, ie to increase performance. Both cores execute different programs, program segments, and instructions, which can improve performance, so this configuration of a dual-core system can be referred to as a performance mode. This system is also referred to as a symmetric multiprocessor system (SMP).
• SMP symmetric multiprocessor system
• SMP Multiprocessor System
• Such a switch usually requires major interventions both in the hardware and in the hardware-related software. So it's not easy to use standard cores, it's also difficult to use code from previous applications written for a core. It is therefore an object of the invention to provide means that require a minimum change of hardware and hardware-related software when using an existing core in a multi-core system.
• a method or apparatus for switching in a computer system having at least two execution units as described in claim 1 or claim 14, over known approaches has the advantage of being able to use already existing bit combinations and thus provides means that minimal change in hardware and require hardware-aware software when using an existing core in a multi-core system.
• optional instructions may be used as described in claim 2, Operands as described in claim 3 or operations as described in claim 4 are used.
• the use of the methods described in claims 2 to 4 thus advantageously increases the flexibility of the possible applications.
• the use of a method as described in claim 5, claim 9 or claim 11 is advantageous as this facilitates the implementation.
• FIG. 1 shows a multiprocessor system G60 with two execution units GlOa, GlOb of a comparison unit G20, a switching unit G50 and a unit for
• FIG. 2 shows a multiprocessor system G60 with two execution units GlOa, GlOb of a combined comparison and switching unit G70 comprising a comparison unit G20 and a switching unit G50 and a unit for switching request recognition G40.
• FIG. 3 shows a multiprocessor system G60 with two execution units GlOa, GlOb of a combined switchover request recognition, comparison and switchover unit G80 consisting of - A -
• FIG. 5 shows in a flow chart a method which, within a specific pipeline stage G230a, G230b, exchanges a special undefined bit combination with a NOP or other neutral bit combination.
• FIG. 6 shows a multiprocessor system H200 with two execution units H210a, H210b and a switching and comparison unit H260.
• FIG. 7 shows in a flow chart a method which shows how, with the aid of the unit ID, the program flow can be changed from one comparison mode to another
• Performance mode can be separated in a multiprocessor system with 2 execution units.
• FIG. 8 shows a possible method, such as the program flow when changing from a comparison mode to a performance mode in one using the unit ID
• Multiprocessor system can be separated with 3 execution units.
• FIG. 9 shows in a flow chart a method which synchronizes the execution units when switching from the performance mode to the comparison mode.
• FIG. 10 shows a state machine which represents the switching between a performance and a comparison mode.
• FIG. 11 shows a multiprocessor system G400 with two execution units and two interrupt controllers G420a, G420b including interrupt masking registers contained therein
• G430a, G430b and various interrupt sources G440a to G440n are provided.
• FIG. 12 shows a multiprocessor system with two execution units, a switching and comparison unit and an interrupt controller with three register sets.
• FIG. 13 shows the simplest form of a comparator.
• FIG. 16 describes the basic behavior of the preferred component M700 (switching and comparison unit) in the performance mode.
• FIG. 18 shows a further embodiment of the switching and comparison unit.
• FIG. 20 shows a general representation of a switching and comparison unit.
• FIG. 22 shows the question of response communication with an external unit.
• execution unit can in the following both a processor, a core, a CPU, as well as an FPU (Floating Point Unit), a DSP (Digital Signal Processor), a coprocessor or a
• ALU Arimetic logical Unit
• FIG. 1 shows a multiprocessor system G60 with two execution units GlOa, GlOb of a comparison unit G20, a switching unit G50 and a unit for switching request recognition G40.
• the invention relates to a multiprocessor system G60 shown in Figure 1, Figure 2, Figure 3 with at least two execution units GlOa, GlOb, a comparison unit G20, a switching unit G50 and a unit for Umschaltplaceerkennung G40.
• the switching unit G50 has at least two outputs to at least two system interfaces
• This multiprocessor system can be operated in at least two modes of operation, a compare mode (VM) and a performance mode (PM).
• VM compare mode
• PM performance mode
• each execution unit GlOa, GlOb is connected to a system interface G30a, G30b.
• the execution unit GlOa is connected to the system interface G30a and the execution unit GlOb is connected to the system interface G30b.
• FIG. 2 shows a multiprocessor system G60 with two execution units GlOa, GlOb of a combined comparison and switching unit G70 comprising a comparison unit G20 and a switching unit G50 and a unit for switching request recognition G40.
• the switching unit G50 and the comparison unit G20 can be combined to form a common switching and comparison unit (UVE) G70, as shown in FIG.
• This common component G70 then takes over the tasks of the individual components G50, G20.
• FIG. 15 FIG. 16, FIG. 17, FIG. 18 and FIG. 19, variant embodiments of UVE G70 are shown.
• the unit for switching request recognition G40, the comparator G20 and the switching unit G50 can be combined in a common component G80.
• Comparator G20 be summarized in a common component. Also conceivable is a summary Umschaltorerkennung G40 with the switch G50 in a common component.
• Switchover request recognition G40 and a combined switchover and comparison unit G70 are combined switchover and comparison unit G70.
• Execution units go n signals N 140, ..., N14n to the switching and comparison component N100. This can generate up to n output signals N160, ..., N16n from these input signals.
• the "pure performance mode” all signals N14i are directed to the corresponding output signals N16i.
• the "pure comparison mode” all signals N140, ..., N14n are only applied to exactly one of the output signals N16i directed.
• the switching logic Nl 10 first determines how many output signals there are. It also determines which of the input signals contribute to which of the output signals. An input signal can contribute to exactly one output signal. Formulated in a different mathematical form is thus by the
• Switching logic defines a function that assigns to each element of the set ⁇ N140, ..., N14n ⁇ an element of the set ⁇ N160, ..., N16n ⁇ .
• the processing logic N120 determines to each of the outputs N16i how the inputs contribute to that output signal. Again, this component does not have to be your own
• a first possibility is to compare all signals and to detect an error in the presence of at least two different values, which can be optionally signaled.
• a second possibility is to make a k out of m selection (k> m / 2).
• an error signal can be generated if one of the signals is detected as deviating.
• a possibly different error signal can be generated if all three signals are different.
• a third option is to apply these values to an algorithm. This may be, for example, the formation of an average, a median, or the use of a Fault Tolerant Algorithm (FTA). Such an FTA is based on extreme values of the
• Delete input values and make a kind of averaging over the remaining values This averaging can be done over the entire set of remaining values or preferably over a subset that is easy to form in HW. In this case, it is not always necessary to actually compare the values. In the For example, averaging needs only to be added and divided, FTM, FTA, or median require partial sorting. If necessary, an error signal can optionally also be output at sufficiently large extreme values.
• the task of the processing logic is thus to determine the exact shape of the comparison operation for each output signal - and thus also for the associated input signals.
• L 0 processing logic i.e., the determination of the comparison operation per output signal, i.e., per
• Function value is the mode information and this sets the mode. This information is of course multivalued in the general case, i. not just a logical bit. Not all the theoretically conceivable modes are useful in a given implementation, it is preferable to restrict the number of modes allowed. It should be emphasized that in the case of only
• Switching from a performance mode to a comparison mode is characterized in the general case by the fact that execution units, which are displayed in the performance mode on different outputs, mapped in the comparison mode to the same output
• Execution units are in which in the performance mode, all input signals N14i, which are to be considered in the subsystem, are switched directly to corresponding output signals N16i, while they are all mapped to an output in comparison mode.
• a switch can also be realized by pairings
• Performance mode and can speak a comparison mode, although in a given form of the invention can limit the amount of allowed modes so that this is the case. However, one can always speak of switching from a performance mode to a comparison mode (and vice versa). i 0 Between these modes it is possible to switch dynamically during operation, controlled by software. The switching is triggered either by the execution of special switching instructions, special instruction sequences, explicitly marked instructions or by the access to specific addresses by at least one of the execution units of the multiprocessor system.
• Fault circuit logic N130 collects the error signals generated by the comparators, for example, and optionally can passively turn outputs N16i off, for example, via a switch.
• the switching between the modes can be coded by various methods.
• special switching commands are to be used, which are detected by the switching request recognition unit G40.
• Another possible method for coding the switching is defined by the access to a special memory area which again detects the unit for switching request recognition G40.
• the following describes a method that uses unused bit combinations in the existing instruction set of the processor. The particular advantage of this method is that existing development environments (assembler, compiler, linker, debugger) can continue to be used.
• FIG. 4 shows a multiprocessor system G200 with two execution units G210a, G210b and a switching and comparison unit G260.
• undefined bit combinations of the at least two execution units G210a, G210b are used in the assembler.
• Undefined or undefined bit combinations in this sense are to be understood as meaning all bit combinations which are specified as undefined or illegal in the description of the instruction set. These are e.g. Illegal Operand, Illegal Instruction, Illegal Operation.
• the general characteristic of these undefined bit combinations is that a normal execution unit when executing such a bit combination either generates an error signal or exhibits an undefined behavior. So these bit combinations are not needed to represent the semantics of an ordinary program.
• the previous development environment can be used, as it exists for single-processor systems. This can be realized, for example, by using a macro "SWITCH MODE TO PM” and a macro “SWITCH MODE TO VM” defined, which inserts appropriate undefined bit combinations at the appropriate place in the code as defined above.
• SWITCH switch to the other depending on the current mode.
• the switchover request is not defined by a command set
• Encoded bit combination may not be processed in the usual way within an execution unit G210a, G210b.
• an additional pipeline stage (REPLACE stage) G230a, G230b is proposed, which recognizes the corresponding bit combinations and replaces them for further processing by neutral bit combinations.
• this is done using the "NOP" (No Operation) command, which is characterized by the fact that it does not change the internal state of the execution unit, except for the intruction pointer, the REPLACE stage G230a, G230b being after the usually first stage , the FETCH stage G220a G220b and before the remaining pipeline stages G240a, G240b, are inserted in the assembler undefined bit combinations, which are here combined in one unit.
• the implementation shown here of a unit for switching request recognition G40 as a special pipeline stage G230a, G230b in a pipeline unit G215a, G215b generates an additional signal G250a, G250b if a corresponding bit combination for switching was detected, which is a separate one
• Switchover unit and comparison unit G260 signals that a change of the processing mode is to be carried out.
• Execution units G210a, G210b arranged.
• the REP stages G230a, G230b recognize the corresponding bit combinations and, in this case, forward NOP instructions to the remaining stages G240a, G240b.
• the respective signal G250a or G250b is activated.
• the REP stages G230a, G230b are neutral, ie all other commands are passed on unchanged to the remaining stages G240a, G240b.
• FIG. 5 shows in a flow chart a method which, within a specific pipeline stage G230a, G230b, has a special undefined bit combination with a
• step G330 represents the functionality of a REPLACE stage G230a, G230b according to the invention, these also being further
• FIG. 6 shows a multiprocessor system H200 with two execution units H210a, H210b and a switching and comparison unit H260.
• the components H220a, H220b, H240a, H240b have the same meaning as G220a, G220b, G240a, G240b.
• this has, in addition to the signals H250a, H250b, which signal a changeover, further signals. So that the execution units H210a, H210b can be synchronized when switching from the performance mode to the comparison mode, the pipeline units H215a, H215b of the execution units H210a have,
• H210b each have a signal input H280a, H280b, with which the processing can be stopped.
• This signal is set by the switching and comparison unit H260 for the pipeline unit H215a or H215b which first detected a switchover command and thus activated the signal H250a or GH50b. Only when both pipeline units H215a, H215b of the execution units H21 Oa, H21 Ob have recognized the switchover command and by
• each execution unit can determine its individual number or unit ID.
• an ID unit a unit or method by which each execution unit can determine its individual number or unit ID.
• one execution unit can determine the number 0 for itself and the other the number 1.
• the numbers are assigned or determined accordingly.
• This ID does not distinguish between a comparison mode and a performance mode, but uniquely identifies an execution unit.
• the ID unit may be included in the respective execution units, for example implemented as a bit or bit combination in the processor status register or as its own
• Register or as a single bit or as an external unit to the execution units that provides a corresponding ID upon request.
• the comparison unit After the execution units have made the changeover to the performance mode in accordance with a changeover request, the comparison unit is no longer active, but the
• Execution units still execute the same commands. This is because the instruction pointers that mark the location in the program where an execution work is currently working or is currently working in the next step are not affected by the switchover. So that the execution units can subsequently execute different software modules, the program sequence of the execution units must be separated. Therefore, the instruction pointers in performance mode usually have different values, since according to the invention independent instructions, program segments or programs are processed.
• the separation of the program flows is done in the proposal described here by determining the respective execution unit number. Depending on which ID has an execution unit, the execution unit executes a specific software module. Since each execution unit has an individual number or ID, the program flow of the participating execution units can thereby be reliably separated.
• Unit ID the program flow can be separated when switching from a comparison mode to a performance mode in a multiprocessor system with 2 execution units. After executing the switchover from a comparison to a performance mode G500, a query of the units ID or execution unit code takes place. Number G510 by both execution units. According to the invention, the execution unit 0 receives the execution unit number O, the execution unit 1 the execution unit number 1. In G510, the determined execution unit number is compared with the number 0. If these are the same, the execution unit moves in step G520 This comparison was successful with the code for
• Comparator so considered a switching and comparison unit G70.
• This implementation is particularly favorable if they are implemented together with the execution units GlOa, GlOb within a chip.
• a preferred variant of the implementation is therefore to combine these two parts in one component.
• This is a component with at least the input signals (output execution unit 1, output execution unit 2), at least the output signals (Output 1, Output 2), a logic output signal "Output total” (can physically match Output 1 or Output 2) and a comparator
• the component has the ability to switch the mode, pass all signals in the performance mode, and in a comparison mode Mode to compare several signals and pass one if necessary
• further input and output signals are advantageous: An error signal for
• FIG. 16 Component in comparison mode
• the various switch positions in these modes are implemented by M700 through the M760 control.
• the two execution units M730, M731 can first write in the performance mode on the data and address bus M710 when the switches M750 and M751 are closed, as shown in FIG. It is assumed that possible write conflicts will be resolved either via the bus protocol or through other, not drawn components.
• the behavior is different, at least from a logical point of view.
• the switches M750, M751 are then opened and thus the direct access possibilities are interrupted.
• FIG. 16 in FIG. 15 then the switches M752, M753 closed.
• the switch M754 is closed, and then one of the two matching signals is forwarded to the address / data bus M710.
• the M700 switching and comparison unit can influence the M750-M754 switches.
• the respective switch position depends on the mode and the error detection. Variants in which the switch M754 is always closed, and a suitable system response is generated by the error signal, are also covered hereby.
• FIG. 17 shows a variant of the switching and comparison unit. Even for a simple system with only two execution units GlOa, GlOb, there are many variants of the implementation of a switching and comparison unit. Another, which is particularly advantageous when no buffers are to be used in the comparator, is shown in FIG. As in FIG. 15, FIG. 16, there are the signals M840, M841 of the execution units. The latter are not drawn in this figure.
• the mode logic M810 which specifies the mode of the component. In the performance mode it closes the switch M831, in comparison mode it opens it. Next she gives the mode signal to the comparator
• the comparison component M920 interrupts the forwarding of the signal M940 to the bus by opening the switch M930.
• Execution units may arise from the processing of various output signals of the various execution units.
• this mode information may even be available explicitly in a subcomponent.
• this mode information may even be available explicitly in a subcomponent.
• this signal can also be led out of the component and made available to other parts of the system.
• N161, N162, N163, N16n have the same meaning as in Fig. 20.
• the mode signal N150 and the error signal N170 are drawn in this figure.
• the optional error signal is generated by fault circuit logic N130, which collects the error signals, and is either a direct forwarding of the single error signals or a bundling of the error information contained therein.
• the mode signal Nl 50 is optional, but its use outside of this component can be beneficial in many places.
• the combination of the information of the switching logic NI10 i.e., the function described in the description of Figure 20
• the processing logic i.e., the determination of the comparison operation per output, i.e., per function value
• the mode signal then brings the relevant mode information to the outside.
• An HW implementation is preferably shown so that the externally visible mode signal can be configured.
• this mode signal is protected.
• An implementation in the two-system is illustrated in Figure 19, for example, based on the implementation illustrated in Figure 17.
• the signal M850 is led out of the switching and comparison unit.
• this information can be represented logically over one bit.
• a hedge can then preferably be displayed via a dual-rail signal.
• the signal can also be protected by a doubling, which is optionally inverted.
• this signal can optionally also be used in other data sinks of a ⁇ C (or more general arithmetic unit).
• a memory protection unit MPU
• MPU memory protection unit
• An MPU is a unit that can ensure that only permitted accesses are made to the data / address bus, for example by blocking access to certain address spaces for certain program sections.
• An essential further purpose is the evaluation of the mode signal outside of the arithmetic unit.
• a direct application is the evaluation in a decrementing
• Reset the value of the register in good time This can be used to check (within limits) whether the microprocessor is executing the software correctly. If the microprocessor no longer executes the software correctly, it is assumed that in this case the "watchdog" is no longer correctly operated and thus an error signal is generated by the "watchdog". The integrity of the hardware and data structures can be reliably verified in a compare mode, but it must be ensured that the microprocessor regularly returns to this.
• the task of the "watchdog” described here is therefore not only to generate an error signal if it is no longer reset within a defined period of time, but also if the microprocessor no longer switches back to the defined comparison mode within a defined period of time the "watchdog" can only be reset if the signal mode indicates the defined comparison mode of the arithmetic unit. This ensures that the arithmetic unit regularly returns to this mode.
• One possibility is to pass the mode signal to an ASIC or another ⁇ C. This can at least check the following points via timers and simple logic using this signal:
• N300 is a computational unit that can send such a mode signal. This may be, for example, a ⁇ C with multiple execution units and another component that can generate this mode signal. For example, this other component may be realized as in FIG. 19 or FIG. N300 gives this signal N310 to the partner (e.g., other arithmetic unit, other ⁇ C or ASIC) N330. This can be over the signal
• N320 ask questions to N300 who has to answer N300 via N321.
• Such a question may be a computational task whose correct result is to be delivered via N321 from N300 within a defined time interval.
• N330 can check the correctness of this result independently of N300. For example, the results are stored in N330 or N330 can calculate it yourself. If an incorrect value is detected, an error is detected.
• the special feature of the proposed question-answer communication is that a parallel to the response, the mode signal is observed.
• the questions are to be asked so that to answer by N300, they must adopt certain modes. This can be reliably verified that all mode changes are functional, and that provided in the program flow mode changes are also performed. Especially when initializing a system, but also during operation, this can serve as an essential component of a security concept.
• An arithmetic unit N400 which has the invention, sends an actuating command via the connection N420 to an (intelligent) actuator or an actuator control N430. In parallel, it sends the mode signal to this actuator via the N410 connection.
• Actuator N430 uses the mode signal to check whether control is permitted and optionally returns an error status via signal N440. If the drive is faulty, it assumes the non-critical fail-silence state in the system.

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