Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
  • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
  • H01L31/035236—Superlattices; Multiple quantum well structures
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y20/00—Nanooptics, e.g. quantum optics or photonic crystals
• • G—PHYSICS
  • G02—OPTICS
  • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
  • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
  • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
  • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
  • G02B6/12004—Combinations of two or more optical elements
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L31/12—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
  • H01L31/16—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources
  • H01L31/167—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources the light sources and the devices sensitive to radiation all being semiconductor devices characterised by at least one potential or surface barrier
  • H01L31/173—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources the light sources and the devices sensitive to radiation all being semiconductor devices characterised by at least one potential or surface barrier formed in, or on, a common substrate
• • G—PHYSICS
  • G02—OPTICS
  • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
  • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
  • G02B6/24—Coupling light guides
  • G02B6/42—Coupling light guides with opto-electronic elements
  • G02B6/4201—Packages, e.g. shape, construction, internal or external details
  • G02B6/4202—Packages, e.g. shape, construction, internal or external details for coupling an active element with fibres without intermediate optical elements, e.g. fibres with plane ends, fibres with shaped ends, bundles

Definitions

• the present invention relates to the field of semiconductors, and, more particularly, to semiconductors having enhanced properties based upon energy band engineering and associated methods.
• 6,472,685 B2 to Takagi discloses a semiconductor device including a silicon and carbon layer sandwiched between silicon layers so that the conduction band and valence band of the second silicon layer receive a tensile strain. Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer, thus, an n-channel MOSFET is asserted to have a higher mobility.
• U.S. Patent No. 4,937,204 to Ishibashi et al. discloses a superlattice in which a plurality of layers, less than eight monolayers, and containing a fraction or a binary compound semiconductor layers, are alternately and epitaxially grown. The direction of main current flow is perpendicular to the layers of the superlattice.
• U.S. Patent No. 5,357,119 to Wang et al. discloses a Si-Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice.
• U.S. Patent No. 5,683,934 to Candelaria discloses an enhanced mobility MOSFET including a channel layer comprising an alloy of silicon and a second material substitutionally present in the silicon lattice at a percentage that places the channel layer under tensile stress.
• U.S. Patent No. 5,216,262 to Tsu discloses a quantum well structure comprising two barrier regions and a thin epitaxially grown semiconductor layer sandwiched between the barriers.
• Each barrier region consists of alternate layers of SiO 2 /Si with a thickness generally in a range of two to six monolayers. A much thicker section of silicon is sandwiched between the barriers.
• An article entitled "Phenomena in silicon nanostructure devices" also to Tsu and published online September 6, 2000 by Applied Physics and Materials Science & Processing, pp. 391-402 discloses a semiconductor-atomic superlattice (SAS) of silicon and oxygen.
• the Si/O superlattice is disclosed as useful in a silicon quantum and light-emitting devices.
• a green electroluminescence diode structure was constructed and tested. Current flow in the diode structure is vertical, that is, perpendicular to the layers of the SAS.
• the disclosed SAS may include semiconductor layers separated by adsorbed species such as oxygen atoms, and CO molecules. The silicon growth beyond the adsorbed monolayer of oxygen is described as epitaxial with a fairly low defect density.
• One SAS structure included a 1.1 nm thick silicon portion that is about eight atomic layers of silicon, and another structure had twice this thickness of silicon.
• An article to Luo et al. entitled “Chemical Design of Direct-Gap Light-Emitting Silicon” published in Physical Review Letters, Vol. 89, No. 7 (August 12, 2002) further discusses the light emitting SAS structures of Tsu.
• an integrated circuit which may include at least one active optical device including a superlattice.
• the superlattice may include a plurality of stacked groups of layers. More particularly, each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon.
• the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
• the integrated circuit may further include a waveguide coupled to the at least one active optical device.
• the at least one active optical device may be an optical transmitter, and at least one portion of the superlattice may define an optical emission region thereof coupled to the waveguide.
• the optical transmitter may further include at least one facet adjacent the optical emission region.
• the at least one active optical device may also be an optical receiver, for example. More specifically, at least one portion of the superlattice may define an optical detector region of the optical receiver coupled to the waveguide, and the optical receiver may further include a light absorbing region adjacent the optical detector for absorbing scattered light.
• the waveguide may also include the superlattice.
• the waveguide may further include a layer on the superlattice, such as an epitaxial silicon layer, for example. Further, the superlattice of the waveguide may have an increased thickness adjacent the at least one active optical device.
• the superlattice may have a common energy band structure therein, and the superlattice may also have a higher charge carrier mobility than would otherwise be present without the at least one non- semiconductor monolayer.
• each base semiconductor portion may comprise at least one of silicon and germanium, and each energy band-modifying layer may comprise oxygen.
• each energy band-modifying layer may be a single monolayer thick, and each base semiconductor portion may be less than eight monolayers thick, for example.
• the superlattice may also have a substantially direct energy bandgap, and it may further include a "base semiconductor cap layer on an uppermost group of layers.
• Each energy band-modifying layer may include a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon- oxygen, for example.
• Another aspect of the invention is directed to a method for making an integrated circuit including one or more active optical devices with enhanced energy band engineered materials.
• the method is for making an integrated circuit which may include forming at least one active optical device including a superlattice.
• the superlattice may include a plurality of stacked groups of layers. More particularly, each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and an energy band-modifying layer thereon.
• the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
• the method may further include forming a waveguide coupled to the at least one active optical device.
• forming the at least one active optical device may include forming an optical transmitter, which may include forming an optical emission region comprising the superlattice and coupled to the waveguide, and forming at least one facet adjacent the optical emission region.
• forming the at least one active optical device may include forming an optical receiver. More specifically, forming the optical receiver may include forming an optical detector region comprising the superlattice and coupled to the waveguide, and forming a light absorbing region adjacent the optical detector region for absorbing scattered light.
• forming the waveguide may include forming a first layer including the superlattice on the semiconductor substrate, and forming a second layer on the first layer, such as an epitaxial silicon layer. Additionally, forming the first layer may include forming the superlattice to have an increased thickness adjacent at least one of the optical transmitter and the optical receiver.
• FIG. 1 is a top plan view of an integrated circuit in accordance with the present invention including active optical devices and a waveguide having an energy band engineered superlattice.
• FIG. 2A is a schematic cross-sectional view of the integrated circuit of FIG. 1 taken along line 2- 2.
• FIG. 2B is an enlarged schematic cross- sectional view illustrating an alternate embodiment of the waveguide of the integrated circuit of FIG. 2A.
• FIG. 3 is a cross-sectional end view of the integrated circuit of FIG. 1 taken along line 3-3 and illustrating the waveguide thereof.
• FIG. 4 is a top plan view of an electronic device in accordance with the present invention including first and second integrated circuits each having an active optical element with an energy band engineered superlattice.
• FIG. 5 is a schematic cross-sectional view of the electronic device of FIG. 4 taken along line 5-5.
• FIG. 6 is a schematic cross-sectional view illustrating the electronic device of FIG. 4 implemented in a multi-chip module.
• FIG. 7 is a greatly enlarged schematic cross- sectional view of the superlattice material used in the integrated circuits of FIGS. 1 and 4.
• FIG. 8 is a perspective schematic atomic diagram of a portion of the superlattice material used in the integrated circuits of FIGS. 1 and 4.
• FIG. 9 is a greatly enlarged schematic cross- sectional view of another embodiment of a superlattice material that may be used in the integrated circuits of FIGS. 1 and 4.
• FIG. 1OA is a graph of the calculated band structure from the gamma point (G) for both bulk silicon as in the prior art, and for the 4/1 Si/0 superlattice as shown in FIGS. 7 and 8.
• FIG. 1OB is a graph of the calculated band structure from the Z point for both bulk silicon as in the prior art, and for the 4/1 Si/0 superlattice as shown in FIGS. 7 and 8.
• FIG. 1OC is a graph of the calculated band structure from both the gamma and Z points for both bulk silicon as in the prior art, and for the 5/1/3/1 Si/O superlattice as shown in FIG. 9.
• FIGS. 11-13 are schematic cross-sectional views illustrating a method for making the integrated circuit of FIG. 1.
• FIGS. 14-15 are schematic cross-sectional views illustrating a method for making the electronic device of FIG. 4.
• FIGS. 16 and 17 are cross-sectional views illustrating alternate contact configurations for the optical detector region of the integrated circuit of FIG. 1.
• FIGS. 18A is a top-plan view of another alternate contact configuration for the optical detector region of the integrated circuit of FIG. 1.
• FIG. 18B is a cross-sectional view of the optical detector of FIG. 18A taken along line 18B-18B.
• FIGS. 19A-19C are cross-sectional views illustrating alternate embodiments of the waveguide of FIG. 3.
• the present invention relates to controlling the properties of semiconductor materials at the atomic or molecular level to achieve improved performance within semiconductor devices. Further, the invention relates to the identification, creation, and use of improved materials for use in the conduction paths of semiconductor devices as well as in optical devices. [0041] Applicants theorize, without wishing to be bound thereto, that certain superlattices as described herein reduce the effective mass of charge carriers and that this thereby leads to higher charge carrier mobility. Effective mass is described with various definitions in the literature. As a measure of the improvement in effective mass Applicants use a
• f is the Fermi-Dirac distribution
• E F is the Fermi energy
• T is the temperature
• E(k,n) is the energy of an electron in the state corresponding to wave vector k and the n th energy band
• the indices i and j refer to Cartesian coordinates x, y and z
• the integrals are taken over the Brillouin zone (B.Z.)
• the summations are taken over bands with energies above and below the Fermi energy for electrons and holes respectively.
• Applicants' definition of the conductivity reciprocal effective mass tensor is such that a tensorial component of the conductivity of the material is greater for greater values of the corresponding component of the conductivity reciprocal effective mass tensor.
• the superlattices described herein set the values of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the material, such as typically for a preferred direction of charge carrier transport.
• these superlattices also may advantageously be configured to provide direct band gaps and, thus, desired optical transmission characteristics.
• the inverse of the appropriate tensor element is referred to as the conductivity effective mass.
• the conductivity effective mass for electrons/holes as described above and calculated in the direction of intended carrier transport may be used to distinguish improved materials.
• the integrated circuit 20 illustratively includes two active optical devices formed in a semiconductor substrate 21 (e.g., silicon) .
• the first active optical device is an optical transmitter 22, and the second optical device is an optical receiver 23.
• a waveguide 24 is coupled between the optical transmitter 22 and the optical receiver 23.
• each of the optical transmitter 22, optical receiver 23, and waveguide 24 includes the superlattice material 25, which will be described further below.
• the superlattice material 25 is shown with stippling in FIG.
• the superlattice material 25 need not be used in each of the optical transmitter 22, optical receiver 23, and waveguide 24 in all embodiments.
• the superlattice material 25 may be used solely in the optical transmitter 22 and/or receiver 23, or it may be used in the waveguide 24 with or without being used in either of the optical transmitter or receiver.
• a single optical transmitter 22, optical receiver 23, and waveguide 24 are shown for clarity of illustration, it will be appreciated by those skilled in the art that numerous such devices may be included within the integrated circuit 20.
• a single type of active optical device may be included in the semiconductor device 20, and there may be one or more of such devices.
• the superlattice material portion of the optical transmitter 22 defines an optical emission region of the optical transmitter which is coupled to the waveguide 24.
• the optical transmitter 22 also illustratively includes a pair of facets 26a, 26b and conductive contacts 27 (e.g., metal or suicide contacts) adjacent the optical emission region to define a laser light transmitter. It should be noted that, while the contacts 27 are not shown in section in FIG. 1, they are hatched for clarity of illustration. [0047] More particularly, the optical emission region and facets 26a, 26b define an optical cavity that contains photons emitted when a voltage is applied across the contacts 27.
• the first facet 26a is located on the side of the optical emission region opposite the waveguide 24, and it is made to reflect the photons.
• the facet 26b is positioned between the optical emission region and the waveguide 24, and it is made partially reflecting so that some radiation can escape from the cavity into the waveguide, as will be appreciated by those skilled in the art.
• the optical transmitter 22 may be a light emitting diode (LED) .
• the superlattice material 25 defines an optical detector region which is illustratively coupled to the waveguide 24.
• the optical detector region receives the photons emitted from the optical emission region of the optical transmitter 22 via the waveguide 24, which may then be detected as a voltage across top and bottom contacts 31t, 31b (e.g., metal or suicide contacts) coupled to the optical detector region.
• the optical receiver 23 may further include a light absorbing region 28 which is doped in the substrate 21 adjacent the optical detector for absorbing scattered light, as will be appreciated by those skilled in the art.
• the bottom contact 31b may be a metal via which is electrically connected to the bottom portion of the superlattice 25 in the optical detection region through a doped contact region 32.
• a metal via which is electrically connected to the bottom portion of the superlattice 25 in the optical detection region through a doped contact region 32.
• numerous contact arrangements are possible for both the optical transmitter 22 and the optical receiver 23 (e.g., top/bottom, front-back, side contacts) , depending upon the given implementation.
• FIGS. 16-18 More particularly, an optical detection region is illustrated in FIG. 16 in which the superlattice 25 is formed on a substrate 160, and a plurality of back-to- back p-type and n-type regions 161, 162, respectively, are doped through the superlattice into the substrate.
• the superlattice 25 is shown with dashed lines in the areas where doping has occurred for clarity of illustration.
• Contacts 163, 164 e.g., metal or suicide
• the p-n regions 161, 162 are reverse-biased and conduct when photons arrive in the depletion regions therebetween, creating charge carriers in the superlattice 25, as will be appreciated by those skilled in the art.
• Using a plurality of p-n regions advantageously allows more light to be captured, which may be desirable in certain embodiments where a relatively small thickness of the superlattice 25 is used.
• FIG. 17 Another embodiment is illustrated in FIG. 17, in which the superlattice 25 is formed on a substrate 170 having a first conductivity type (e.g., n-type) .
• a top cap layer 52 of the superlattice 25, which is described further below, is implanted with an impurity of a second conductivity type (e.g., p-type) .
• a contact region 172 of the first conductivity type is doped through the superlattice 25 to the substrate 170, which provides a bottom contact to the superlattice.
• a contact 173 is formed on the cap layer 52 to provide a top contact for the superlattice 25, and a contact 174 is also formed on the contact region 172.
• FIGS Yet another embodiment is illustrated in FIGS.
• a p-type contact region 181 and an n-type contact region 182 are formed in a substrate 180 (e.g., n-type) in parallel with the path light travels through the superlattice 25, as shown with a dashed arrow in FIG. 18A.
• contact regions 183 and 184 are respectively formed on the p and n-type contact regions 181, 182.
• the contact regions may advantageously be configured in numerous ways relative to the given orientation of the superlattice 25 and the direction of light propagation depending upon the particular implementation. Generally speaking, it is desirable to minimize the distance that light has to pass through the doped regions to avoid signal loss, as will be appreciated by those skilled in the art. Also, while the foregoing contact configurations were described with reference to optical receivers, it will be appreciated that they may be used for optical transmitters as well.
• the superlattice 25 is shown as being substantially lateral or parallel to the upper surface of the substrate in the above-noted embodiments, the superlattice may also be substantially vertically- oriented (i.e., perpendicular to the upper surface of the substrate) in other embodiments, for example, and the contact regions configured accordingly. Further details regarding vertical implementations of the superlattice 25 in semiconductor devices is provided in co-pending application entitled SEMICONDUCTOR DEVICE COMPRISING A VERTICAL SUPERLATTICE STRUCTURE, attorney docket number 62651.
• the waveguide 24 transports the photons generated by the optical transmitter 22 to the optical receiver 23.
• the waveguide 24 is a rib waveguide including an upper layer 29 on the superlattice material 25 defining a rib 33.
• the layer 29 may be an epitaxial silicon layer (or layers) grown on top of the superlattice 25 (or it could be the cap layer of the superlattice) .
• it may be desirable to increase the thickness of the superlattice material 25 adjacent the optical transmitter 22 and/or optical receiver 23 to facilitate alignment of the various components, as shown in the enlarged view of FIG. 2B.
• FIG. 3 A cross-sectional view of the rib waveguide 24 is illustrated in FIG. 3.
• the light transmission field 34 is shown with dashes and extends within the rib 33, layer 29, and into the superlattice 25.
• the superlattice 25 of the waveguide 24 may be about 500 nm in thickness, while the layer 29 and rib 33 may be about 2 to 4 ⁇ m thick, although other dimensions may also be used.
• FIG. 19A Another similar waveguide 24' is illustrated in FIG. 19A.
• the waveguide 24' is also a rib waveguide, but rather than being formed directly on the substrate 21' it is instead formed on an insulating layer 190' (e.g., silicon dioxide) to provide a silicon-on- insulator (SOI) implementation, as will be appreciated by those skilled in the art.
• SOI silicon-on- insulator
• FIG. 19B Another SOI rib waveguide 24'' is illustrated in FIG. 19B.
• p+ and n+ regions 191' ' , 192' ' are included for biasing the superlattice 25'', which extends therebetween.
• FIG. 19C Yet another exemplary waveguide embodiment is illustrated in FIG. 19C.
• the waveguide 24''' is a ridge waveguide, where the ridge is made up a vertical stack of top and bottom semiconductor (e.g., silicon or germanium) layers 193' ' ' , 194' ' ' with the superlattice 25' ' ' therebetween.
• the ridge may optionally be formed on the insulating layer 190' ' ' , if desired.
• a single optical transmitter 22 could be used to distribute clock and/or data signals optically to numerous other components of the integrated circuit 20.
• the waveguide 24 may be configured in a network, such as an H-tree network, to distribute clock and/or data signals to a plurality of optical receivers 23 distributed throughout the integrated circuit 20, as will be appreciated by those skilled in the art.
• the waveguide 24 including the superlattice 25 may also advantageously be used for providing voltage isolation between components, i.e., as an opto-isolator. This may be particularly important where high voltage components are included in the integrated circuit 20.
• an electronic device 60' illustratively includes a first integrated circuit 20a' having an optical transmitter 22' , and a second integrated circuit 20b' having an optical receiver 23' .
• the optical transmitter 22' includes an optical emission region defined by the superlattice 25a' and contacts 27' coupled thereto.
• the optical emission region is positioned adjacent an edge of the integrated circuit 20a' to provide an edge emitting device as shown.
• the first and second integrated circuits 20a' , 20b' are positioned relative to one another so that the optical transmitter 22' and optical receiver 23' are aligned to establish an optical communications link therebetween.
• the optical communications link is a free space optical (FSO) communications link, as shown.
• FSO free space optical
• a waveguide or other optical elements/devices may also be coupled in the optical path between the optical transmitter 22' and optical receiver 23' in certain embodiments, if desired.
• the optical transmitter 22' may be a vertical surface emitting device.
• Various optical elements/devices may also be used with such a surface emitting configuration, such as a hologram grating and/or mirror, for example, as will be appreciated by those skilled in the art.
• the electronic device 60' may be implemented in a multi-chip module 61' (FIG. 6) , as will be appreciated by those skilled in the art, although other configurations may also be used.
• FIGS. 7 and 8 the superlattice 25 for use in the integrated circuit 20 is now further described.
• the materials/ structures used to form the superlattice 25, whose structure is controlled at the atomic or molecular level, may be formed using known techniques of atomic or molecular layer deposition.
• the superlattice 25 includes a plurality of layer groups 45a-45n arranged in stacked relation, as perhaps best understood with specific reference to the schematic cross-sectional view of FIG. 7.
• Each group of layers 45a-45n of the superlattice 25 illustratively includes a plurality of stacked base semiconductor monolayers 46 defining a respective base semiconductor portion 46a-46n and an energy band-modifying layer 50 thereon.
• the energy band-modifying layers 50 are indicated by stippling in FIG. 7 for clarity of illustration.
• the energy-band modifying layer 50 illustratively includes one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. In other embodiments, more than one such monolayer may be possible.
• non- semiconductor/semiconductor monolayer means that the material used for the monolayer would be a non- semiconductor/semiconductor if formed in bulk. That is, a single monolayer of material, such as a semiconductor, may not necessarily exhibit the same properties that it would if formed in bulk or in a relatively thick layer, as will be appreciated by those skilled in the art.
• the superlattice 25 may have a substantially direct energy bandgap, which is particularly advantageous for opto-electronic devices, as discussed further below.
• transportation of charge carriers through the superlattice is in a parallel direction relative to the layers of the stacked groups 45a-45n.
• the superlattice 25 also illustratively includes a cap layer 52 on an upper layer group 45n.
• the cap layer 52 may comprise a plurality of base semiconductor monolayers 46.
• the cap layer 52 may have between 2 to 100 monolayers of the base semiconductor, and, more preferably between 10 to 50 monolayers.
• Each base semiconductor portion 46a-46n may comprise a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.
• Group IV semiconductors also includes Group IV-IV semiconductors, as will be appreciated by those skilled in the art.
• the base semiconductor material may comprise at least one of silicon and germanium, for example.
• Each energy band-modifying layer 50 may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon- oxygen, for example. The non-semiconductor is also desirably thermally stable through deposition of a next layer to thereby facilitate manufacturing.
• the non-semiconductor may be another inorganic or organic element or compound that is compatible with the given semiconductor processing as will be appreciated by those skilled in the art.
• the term monolayer is meant to include a single atomic layer and also a single molecular layer.
• the energy band-modifying layer 50 provided by a single monolayer is also meant to include a monolayer wherein not all of the possible sites are occupied. For example, with particular reference to the atomic diagram of FIG. 8, a 4/1 repeating structure is illustrated for silicon as the base semiconductor material, and oxygen as the energy band-modifying material. Only half of the possible sites for oxygen are occupied.
• this one half occupation would not necessarily be the case, as will be appreciated by those skilled in the art. Indeed, it can be seen even in this schematic diagram that individual atoms of oxygen in a given monolayer are not precisely aligned along a flat plane, as will also be appreciated by those of skill in the art of atomic deposition.
• a preferred occupation range is from about one-eighth to one-half of the possible oxygen sites being full, although other numbers may be used in certain embodiments.
• the number of silicon monolayers should desirably be seven or less so that the energy band of the superlattice is common or relatively uniform throughout to achieve the desired advantages.
• the 4/1 repeating structure shown in FIGS. 7 and 8 for Si/O has been modeled to indicate an enhanced mobility for electrons and holes in the X direction.
• the calculated conductivity effective mass for electrons is 0.26
• the 4/1 SiO superlattice in the X direction it is 0.12, resulting in a ratio of 0.46.
• the calculation for holes yields values of 0.36 for bulk silicon and 0.16 for the 4/1 Si/0 superlattice, resulting in a ratio of 0.44.
• other devices may benefit from a more uniform increase in mobility in any direction parallel to the groups of layers. It may also be beneficial to have an increased mobility for both electrons or holes, or just one of these types of charge carriers as will be appreciated by those skilled in the art.
• the lower conductivity effective mass for the 4/1 Si/0 embodiment of the superlattice 25 may be less than two-thirds the conductivity effective mass than would otherwise occur, and this applies for both electrons and holes.
• the superlattice 25 may further comprise at least one type of conductivity dopant therein, as will also be appreciated by those skilled in the art.
• FIG. 9 another embodiment of a superlattice 25' in accordance with the invention having different properties is now described.
• a repeating pattern of 3/1/5/1 is illustrated. More particularly, the lowest base semiconductor portion 46a' has three monolayers, and the second lowest base semiconductor portion 46b' has five monolayers. This pattern repeats throughout the superlattice 25' .
• the energy band-modifying layers 50' may each include a single monolayer.
• the enhancement of charge carrier mobility is independent of orientation in the plane of the layers.
• all of the base semiconductor portions of a superlattice may be a same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be a different number of monolayers thick. In still other embodiments, all of the base semiconductor portions may ⁇ be a different number of monolayers thick.
• FIGS. lOA-lOC band structures calculated using Density Functional Theory are presented. It is well known in the art that DFT underestimates the absolute value of the bandgap. Hence all bands above the gap may be shifted by an appropriate "scissors correction.” However the shape of the band is known to be much more reliable. The vertical energy axes should be interpreted in this light.
• DFT Density Functional Theory
• FIG. 1OA shows the calculated band structure from the gamma point (G) for both bulk silicon
• the directions refer to the unit cell of the 4/1 Si/O structure and not to the conventional unit cell of Si, although the (001) direction in the figure does correspond to the (001) direction of the conventional unit cell of Si, and, hence, shows the expected location of the Si conduction band minimum.
• the (100) and (010) directions in the figure correspond to the (110) and (-110) directions of the conventional Si unit cell.
• the bands of Si on the figure are folded to represent them on the appropriate reciprocal lattice directions for the 4/1 Si/O structure.
• the conduction band minimum for the 4/1 Si/O structure is located at the gamma point in contrast to bulk silicon (Si) , whereas the valence band minimum occurs at the edge of the Brillouin zone in the (001) direction which we refer to as the Z point.
• the greater curvature of the conduction band minimum for the 4/1 Si/O structure compared to the curvature of the conduction band minimum for Si owing to the band splitting due to the perturbation introduced by the additional oxygen layer.
• FIG. 1OB shows the calculated band structure from the Z point for both bulk silicon (continuous lines) and for the 4/1 Si/0 superlattice 25 (dotted lines) . This figure illustrates the enhanced curvature of the valence band in the (100) direction.
• FIG. 1OC shows the calculated band structure from the both the gamma and Z point for both bulk silicon (continuous lines) and for the 5/1/3/1 Si/0 structure of the superlattice 25' of FIG. 9 (dotted lines) . Due to the symmetry of the 5/1/3/1 Si/0 structure, the calculated band structures in the (100) and (010) directions are equivalent. Thus the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e. perpendicular to the (001) stacking direction. Note that in the 5/1/3/1 Si/O example the conduction band minimum and the valence band maximum are both at or close to the Z point.
• the appropriate comparison and discrimination may be made via the conductivity reciprocal effective mass tensor calculation. This leads Applicants to further theorize that the 5/1/3/1 superlattice 25' should be substantially direct bandgap.
• the appropriate matrix element for optical transition is another indicator of the distinction between direct and indirect bandgap behavior, and thus may be used to distinguish improved materials.
• FIGS. 11-13 a method for making the integrated circuit 20 is now described. First, the semiconductor substrate 21 is etched to form a superlattice material 25 deposition region and the contact region 32 is doped. The superlattice 25 is then deposited in the etched region as described above. Of course, in some embodiments the superlattice 25 may be deposited on the surface of the substrate 21 without etching, as will be appreciated by those skilled in the art.
• the epitaxial silicon layer 29 and rib 33 may then be formed on the superlattice material 25 and patterned, as shown in FIG. 13. More particularly, the epitaxial silicon layer may be patterned as part of the facet 26a, 26b formation process. The light absorbing region 28 may then be doped in the substrate 21 adjacent the portion of the superlattice 25 that is to define the optical detection region, and the contacts 27, 31t, 31b may be formed to provide the semiconductor 20 illustrated in FIGS. 1 and 2.
• the light absorbing region 28 may in some cases be doped before the superlattice material 25 is deposited or the facets 26a, 26b are formed.
• FIGS. 14-15 A method for making the electronic device 60' illustrated in FIGS. 4 and 5 is now described with reference to FIGS. 14-15. While the substrates 21a', 21b' are shown side-by-side for clarity of illustration in these figures, it will be appreciated that these substrates need not necessarily be processed simultaneously (i.e., the integrated circuits 20a', 20b' may be formed separately) . However, in some embodiments it may be possible to form the device on a single substrate, similar to the steps described above with reference to FIGS. 10-12, and then divide the completed device into the two integrated circuits 20a' , 20b' to form the electronic device 60' .
• the substrates 21a', 21b' are etched to form superlattice deposition regions and the contact region 32' is doped, as discussed above.
• the superlattice deposition regions are formed, the superlattice portions 25a' , 25b' are formed therein, as discussed above.
• the light absorbing region 28' may then be doped, and the contacts 27' , 31t' , 31b' are formed to complete the integrated circuits 20a' , 20b' .
• conventional semiconductor processing techniques may be used for the above-noted steps, and various steps may also be performed in different orders in different embodiments, as will be appreciated by those skilled in the art.

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• 2005
  • 2005-09-08 EP EP05796396A patent/EP1794805A1/de not_active Withdrawn
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