EP1782534A1 - Reduction de la consommation d'energie dans des circuits numeriques haute frequence - Google Patents

Reduction de la consommation d'energie dans des circuits numeriques haute frequence

Info

Publication number
EP1782534A1
EP1782534A1 EP05774786A EP05774786A EP1782534A1 EP 1782534 A1 EP1782534 A1 EP 1782534A1 EP 05774786 A EP05774786 A EP 05774786A EP 05774786 A EP05774786 A EP 05774786A EP 1782534 A1 EP1782534 A1 EP 1782534A1
Authority
EP
European Patent Office
Prior art keywords
frequency
self
bias
digital circuit
resonant frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05774786A
Other languages
German (de)
English (en)
Inventor
Henk Visser
Cicero Vaucher
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of EP1782534A1 publication Critical patent/EP1782534A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0233—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
    • H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
    • H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
    • H03K3/288—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit
    • H03K3/2885—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit the input circuit having a differential configuration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
    • H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
    • H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
    • H03K3/289—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable of the master-slave type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption

Definitions

  • the present invention relates to electronic digital circuitry, and more particularly to circuits and methods for operating high frequency dividers for minimized power consumption.
  • Reduced current demand in electronic devices translates directly into longer battery life and lower power dissipation.
  • Longer battery life is critical in wireless portable applications like cellphones, portable computers, and Wi-Fi wireless networking.
  • Power dissipation goes up as the square of the current demanded, and any wasted heat produced can unnecessarily shorten device life.
  • Semiconductor process variations and wide operating temperature ranges traditionally dictate high DC-biasing currents in order to guarantee reliable operation. Reducing these DC-biasing currents can lead to improved battery life.
  • a frequency divider to produce the in- phase (I) and quadrature-phase (Q) clocks needed by the radio transmitters and receivers.
  • a voltage controlled oscillator (VCO) is typically controlled by a phase locked loop (PLL) to synthesize one or more frequencies to drive the I-Q frequency divider.
  • PLL phase locked loop
  • Such dividers are conventionally constructed as two cross-coupled D-type flip-flops.
  • the typical I-Q frequency divider will free oscillate at some frequency of its own choosing if there is no oscillator input drive.
  • the self-resonant frequency represents the point where loop losses are minimum and positive feedback is maximum. This point represents maximum circuit power efficiency.
  • the free-oscillating frequency is affected by the DC-biasing currents applied. In conventional circuit design, these DC-biasing currents are fixed and set high enough to guarantee an operational margin over the range of process variations and operating temperatures that are expected to occur. In actual fact, such currents are at least double that which are really necessary. Reducing these margins can significantly reduce overall operating currents and contribute substantially to battery life in portable devices.
  • Each flip-flop comprises a gate section and a latch section. Each such section is respectively DC-biased by a gate-current (I gate ) and a latch-current (Ii atCh ) from independent current sources.
  • I gate gate-current
  • Ii atCh latch-current
  • Such self-resonant frequency has been observed to be dependent on the ratio of Igate and li atC h DC-biasing currents applied.
  • atCh DC-biasing currents can be varied over a wide range without any significant affect on the self-resonant frequency if the I gate /Iia tch ratio is maintained. Of course, such total current will directly affect battery consumption, and there is a minimal bias point where the circuit will no longer work.
  • the I-Q frequency divider can function reliably in operation at its minimum total I gate and Ii atch DC-biasing currents if the ratio of these currents is adjusted to result in a self- resonant frequency that approximates the oscillator input frequency.
  • a circuit embodiment of the present invention comprises a frequency divider connected to receive respective Igate and Iiatch DC-biasing currents. Such frequency divider will self-resonate at some frequency that depends in part on these DC-biasing currents.
  • Corresponding current sources provide programmable magnitudes for each of these DC-biasing currents, and can therefore affect the self-resonant frequency and overall power consumption.
  • the frequency divider is allowed to self-oscillate, and the DC-biasing currents are manipulated to cause the self-resonant frequency to approximate some target frequency.
  • the DC-biasing currents can be opportunistically lowered and still maintain reliable operation when the self-resonant frequency of the frequency divider is tuned to the target operational frequency. Such calibration is repeated as needed during the service life of the device.
  • An advantage of the present invention is a circuit is provided that can operate at reduced power.
  • a further advantage of the present invention is a circuit is provided that can extend battery life in portable devices.
  • a still further advantage of the present invention is that a method is provided for sensing an efficient DC-bias combination for a frequency divider.
  • Fig. 1 is a schematic diagram of a frequency divider circuit embodiment of the present invention
  • Fig. 2 is a flowchart diagram of a first method embodiment of the present invention, and is useful in the circuit of Fig. 1 ;
  • Fig. 3 is a flowchart diagram of a second method embodiment of the present invention, and is also useful in the circuit of Fig. 1.
  • Fig. 1 illustrates a frequency divider circuit embodiment of the present invention, and is referred to herein by the general reference numeral 100.
  • the frequency divider circuit 100 comprises a first gate section 102, a first latch section 104, a second gate section 106, and a second latch section 108 that is cross-coupled back to the first gate section 102.
  • a pair of output buffers 1 10 provides a differential output drive.
  • a frequency meter 112 measures the oscillations (if any) at this output.
  • a gate/latch bias generator 1 13 receives a control signal related to the self-resonant output frequency. It can switch off an oscillator input with a switch 1 14 during a calibration mode.
  • a temperature sensor is included in the bias generator 1 15 for this purpose.
  • the calibration mode may be engaged only once to detect and remove worst-case process margins, or every time the circuit is energized, or periodically, or on command.
  • the values to set the I-gate and I-latch bias currents, determined during calibration, can be stored in non-volatile digital memory or analog sample-and-hold devices.
  • a reference frequency input 1 16 is provided to the frequency meter 1 12.
  • a gate- bias output 1 18 from generator 1 13 is applied to an I-gate bias current source 120.
  • a latch- bias output 122 is applied to an I-latch bias current source 124.
  • the frequency divider circuit 100 is such that its self-resonant frequency is dependent on the ratio of the I-gate and I-latch bias currents provided by current sources 120 and 124. Such self-resonant frequency also corresponds with the frequency at which the frequency divider circuit 100 has its best input signal sensitivity. If operated at such a frequency, the required input drive can be reduced and the loading on an oscillator can be minimized. An object of this is to reduce operating power without sacrificing performance or reliability.
  • the sum total of the two I-gate and I-latch bias currents provided by current sources 120 and 124 is controlled by generator 1 12 to be just high enough to produce stable frequency divider circuit operation. Integrated circuit designers can optimize the high frequency performance of frequency divider circuit 100 by critically sizing the area of the gate pair transistors in relation to the latch pair transistors.
  • the optimum ratio to set for the two I-gate and I-latch bias currents is determined during a calibration mode. One, or the other, or both such currents can be manipulated for the desired effects.
  • the reference frequency input 1 16 is fixed to provide a frequency-measurement time-base.
  • the bias generator 1 13 switches off oscillator input switch 114, and manipulates the ratio of gate-bias 118 and latch-bias 122 outputs until the self-resonant output frequency approximates a desired target frequency. These bias values are then stored.
  • the reference frequency input 1 16 is adjusted to clock at the same frequency that the frequency divider circuit 100 should self- resonate.
  • the bias generator 113 switches off oscillator input switch 114 and manipulates the ratio of gate-bias 1 18 and latch-bias 122 outputs until the self-resonant output frequency sample approximates the reference frequency input 1 16. These bias values are then stored. Other methods are also possible that take advantage of circuitry already included for other purposes. After the initial finding of the current ratio that results in the desired self-resonant frequency, both the I-gate and I-latch bias currents are reduced in parallel, while maintaining their ratio, to the point where no divider output is detected. Too little bias current causes the device to turn off.
  • the I-gate and I-latch bias currents are tuned back up just high enough so that reliable frequency divider operation resumes. These bias current setpoints are then fixed, and the calibration mode is completed. Such currents are substantially less that those that would result if only worst-case process and temperature margins had to be fixed in the original integrated circuit design.
  • a circuit operation method embodiment of the present invention comprises measuring a first self-resonant frequency of a digital circuit in a step 202.
  • a first bias current applied to the digital circuit is adjusted to produce a second self-resonant frequency that approximates an operational frequency.
  • the power required by the digital circuit reduces during operation from the first to second self-resonant frequencies.
  • a second bias current applied to the digital circuit is adjusted to tune the circuit to the second self-resonant frequency.
  • the ratio of the first and second bias currents is principally manipulated to effectuate the second self-resonant frequency.
  • a step 212 the total of the first and second bias currents is adjusted to effectuate reduced power consumption by the digital circuit.
  • a minimum total for the first and second bias currents is detected that still allows the digital circuit to continue to operate.
  • a minimum total for the first and second bias currents, determined in the step of detecting, is set so the digital circuit will operate.
  • Fig. 3 represents another method embodiment of the present invention, and is referred to herein by the general reference numeral 300.
  • Method 300 is for reducing the power consumption of an electronic device during its operation. It comprises a step 302 that includes within an electronic device a digital circuit that has maximum signal input sensitivity at a self-resonant frequency, and such self-resonant frequency depends on at least one biasing input current.
  • a step 304 is for measuring the self-resonant frequency.
  • a step 306 is for adjusting at least one bias current applied to the digital circuit, to tune it to another self-resonant frequency that approximates an intended operational frequency.
  • a step 308 operates the digital circuit thereafter at the bias currents determined in the step of measuring.
  • the method 300 may comprise further steps.
  • a step 310 adjusts the ratio of a first bias current and a second bias current to tune to a self-resonant frequency that approximates an intended operational frequency.
  • a step 312 adjusts the total of the first and second bias currents to effectuate reduced power consumption by the digital circuit.
  • a step 314 detects a minimum total for the first and second bias currents that allows the digital circuit to continue to operate.
  • a step 316 fixes the first and second bias currents at respective values determined in detecting step 314.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

L'invention concerne un circuit comprenant un diviseur de fréquence connecté en vue d'une réception de courants de polarisation CC Igate et Ilatch. Ce diviseur de fréquence est auto-résonant à une fréquence donnée qui dépend, en partie, de ces courants de polarisation CC. Des sources de courant correspondantes fournissent des amplitudes programmables pour chacun de ces courants de polarisation CC et peuvent ainsi affecter la fréquence auto-résonante et la consommation d'énergie globale. Pendant un étalonnage, le diviseur de fréquence peut auto-osciller et les courants de polarisation CC sont manipulés en vue d'amener la fréquence auto-résonante à se rapprocher d'une fréquence cible donnée. Les courants de polarisation CC peuvent avantageusement être abaissés tout en assurant un fonctionnement fiable lorsque la fréquence auto-résonante du diviseur de fréquence est réglée sur la fréquence de fonctionnement cible. Cet étalonnage est réitéré autant de fois que nécessaire pendant la durée de vie du dispositif.
EP05774786A 2004-08-17 2005-08-17 Reduction de la consommation d'energie dans des circuits numeriques haute frequence Withdrawn EP1782534A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US60244104P 2004-08-17 2004-08-17
PCT/IB2005/052715 WO2006018818A1 (fr) 2004-08-17 2005-08-17 Reduction de la consommation d'energie dans des circuits numeriques haute frequence

Publications (1)

Publication Number Publication Date
EP1782534A1 true EP1782534A1 (fr) 2007-05-09

Family

ID=35240893

Family Applications (1)

Application Number Title Priority Date Filing Date
EP05774786A Withdrawn EP1782534A1 (fr) 2004-08-17 2005-08-17 Reduction de la consommation d'energie dans des circuits numeriques haute frequence

Country Status (5)

Country Link
EP (1) EP1782534A1 (fr)
JP (1) JP2008510412A (fr)
KR (1) KR20070033470A (fr)
CN (1) CN101006642A (fr)
WO (1) WO2006018818A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100967043B1 (ko) * 2008-09-23 2010-06-29 삼성전기주식회사 래치 구조를 이용한 주파수 분주기
US8456202B2 (en) * 2011-02-15 2013-06-04 Texas Instruments Incorporated Latch divider

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2871560B2 (ja) * 1995-11-21 1999-03-17 日本電気株式会社 π／２移相器

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2006018818A1 *

Also Published As

Publication number Publication date
WO2006018818A1 (fr) 2006-02-23
CN101006642A (zh) 2007-07-25
KR20070033470A (ko) 2007-03-26
JP2008510412A (ja) 2008-04-03

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