Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
  • H03M13/2957—Turbo codes and decoding
  • H03M13/296—Particular turbo code structure
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
  • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
  • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
  • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
  • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
  • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
  • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
  • H03M13/1105—Decoding
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
  • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
  • H03M13/3972—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using sliding window techniques or parallel windows
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L1/00—Arrangements for detecting or preventing errors in the information received
  • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
  • H04L1/0041—Arrangements at the transmitter end
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L1/00—Arrangements for detecting or preventing errors in the information received
  • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
  • H04L1/0056—Systems characterized by the type of code used
  • H04L1/0057—Block codes
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L1/00—Arrangements for detecting or preventing errors in the information received
  • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
  • H04L1/0056—Systems characterized by the type of code used
  • H04L1/0061—Error detection codes
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
  • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
  • H03M13/3905—Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding
  • H03M13/3938—Tail-biting
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L1/00—Arrangements for detecting or preventing errors in the information received
  • H04L1/08—Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system

Definitions

• An error correction encoding method comprising local error-detecting codes, decoding method, transmitting, receiving and storing devices, and corresponding program.
• TECHNICAL FIELD The field of the invention is that of the coding of digital data, in particular with a view to their transmission or storage. More specifically, the invention relates to error correcting codes. The invention can find applications in all areas where it is necessary, or at least desirable, to have an error correcting code. Thus, the invention can notably be applied to: protection against errors due to the noise and interference inherent in the physical transmission channels (conventional error correction coding and space-time codes for multi-antenna systems), example for applications in wireless telecommunications systems DECT, GSM, UMST, local and home automation networks, satellite telecommunications ...
• the turbo-codes encode (that is to say calculate a block of the redundancy bits Y1) a first time a block of information (block of bits X) by a convolutional encoder 11 described by a lattice with a small number of states (8 or 16 in general), then interchange or interleave the information block in another order (12) to encode them again (13) to provide the block of redundancy bits Y2.
• the transmitted encoded block is therefore composed of X, Y1 and Y2, or even other permuted blocks 14-encoded with additional redundancies Yi.
• FIG. 1 Another representation of the LDPC codes is their bipartite Tanner graph which represents the variables by nodes (or vertices) placed on the left in a graph and the control equations (or constraints) by exclusive OR represented by nodes placed on the right in this graph and connected to the binary variables by branches (or edges).
• Figure 2 shows the bipartite Tanner graph corresponding to the matrix above.
• the degrees may vary from one variable to another and the codes may be different.
• the constraints "exclusive OR" are replaced by small codes called “local” the overall code is said to Tanner.
• Figure 3 shows the architecture of Tanner codes more general than that of LDPC codes.
• the codes Ci 31 can be much more complex codes than a simple parity code realized by an exclusive OR as in the LDPC codes. 3.
• Disadvantages of these prior techniques Turbo codes, LDPC codes or their variants offer performance, in terms of error correction, remarkable for large block sizes, of at least a few thousand or tens of thousands of bits information, but for computation complexity at high decoding, which however remains compatible with the constantly increasing computing capabilities of current microprocessors.
• turbo-codes have a minimum distance ⁇ TM at best logarithmic length, and LDPC codes that approach the channel capacity are also at best logarithmic in the length of the code: n ⁇ ⁇ A code family is said to be asymptotically good (AB) if the minimum distance
• an object of the invention is to provide an error correction coding technique that is simpler to implement than known codes, in particular codes of the turbo-code or LDPC type, and more efficient.
• an objective of the invention is to provide such a coding technique, making it possible to reduce the complexity of the codes (and therefore of the corresponding decoding), in particular in order to reduce the silicon surface used on the components, and the consumption of necessary energy.
• the object of the invention is to enable the construction of codes offering a better compromise between complexity and error correction capabilities than the best current correction codes.
• One of the goals pursued is therefore to obtain error-correcting codes that further improve the error correction performance of the best LDPC codes and existing turbo-codes for a smaller complexity, by optimizing their information transmission capabilities for given channels: symmetrical binary channel (BSC), erasing channel (BEC), Gaussian channel, ...
• Another objective of the invention is to provide such a coding technique, which has very good correction qualities. errors, as close as possible to the theoretical limits.
• an object of the invention is to provide effective error correcting codes even for small size blocks.
• an object of the invention is to make it possible to construct very good short error-correcting codes by practically eliminating the phenomenon of "error-floor" by increasing the minimum distances of the error. min .
• error-floor means that the bit error rate (BER) curve decreases less rapidly for high signal-to-noise ratios than for low signal-to-noise ratios, part of the BER curve also known as “water- fall "(" waterfall "). 5.
• BER bit error rate
• said local codes are detectors codes but not error correctors on a predetermined coding alphabet, and in that said local codes are interconnected by their status words, so as to form at least one lattice of coding, each trellis defining a basic code.
• said invention is effective for many types of codes, including short error correcting codes, strongly limiting the so-called "error floor” phenomenon.
• said permutations are applied to said label words, and not to said status words. This results in a simplified system, reducing the number of variables processed.
• said local codes are binary codes, represented by trellises with 2 or 4 states.
• said local codes are defined on a coding alphabet with 2 n elements, and represented by lattices with 2 n , 2 n + 1 or 2 n + 2 states (n integer greater than 2) .
• a 4-element coding it may be represented by 4, 8 or 16-state trellis.
• each of said basic codes delivers codewords of length m symbols, each of which is at least one bit, of a coding alphabet defined in such a way that: the number of weight code words 2 is smaller or equal to m / 2; the number of code words of weight 3 is non-zero, the weight of a code word being the number of non-zero symbols that it contains.
• This structure makes it possible to obtain very good coding results.
• at least one of said basic codes is formed of at least two sections of code. According to the invention, it is also possible to implement punching on at least one of said basic codes. This punching can be applied to variables and / or code branches.
• At least one of the lattices is a cyclic lattice. At least one of the lattices may also be a lattice whose input state and output state are forced to predetermined values.
• at least one of said local codes is a 2-state code (6, 4, 2), associating an output state bit with an input state bit, based on 6 label bits, where: - 6 is the length of said local code, or its number of tag bits; - 4 is the dimension of said local code; - 2 is the minimum distance from said base code.
• said base code is advantageously formed of three sections of said code (6, 4, 2).
• At least one of said local codes is a 2-state code (4, 3, 2), associating an output state bit with an input state bit, according to 4 label bits, where: - 4 is the length of said local code, or its number of tag bits; - 3 is the dimension of said local code; - 2 is the minimum distance from said base code.
• said base code is advantageously formed of two sections of said code (4, 3, 2).
• At least one of said local codes is a 2-state code (6, 5, 2), associating an output state bit with an input state bit, based on 6 label bits, where: - 6 is the length of said local code, or its number of tag bits; - 5 is the dimension of said local code; - 2 is the minimum distance from said base code.
• said base code is advantageously formed of three sections of said code (6, 5, 2).
• At least one of said local codes is a 4-state code (8, 7, 2), associating an output state bit with an input state bit, according to 8 label bits, where: - 8 is the length of said local code, or its number of tag bits; - 7 is the dimension of said local code; - 2 is the minimum distance from said local code.
• at least one of said local codes is a code (8, 7, 2) with 2 states, associating an input state bit with an input state bit, according to 8 label bits, where: - 8 is the length of said local code, or its number of tag bits; - 7 is the dimension of said local code; - 2 is the minimum distance from said local code.
• said base code is advantageously said basic code is formed of eight sections of said code (8, 7, 2).
• the invention also relates to a method of decoding coded data using the coding method described above.
• Such a decoding method implements, in a manner symmetrical to the coding, a plurality of local codes, associating at least one input state word with at least one output status word, as a function of at least one label word, and permutations applied to at least some of said words, said local codes being detector codes but not correcting errors on a predetermined coding alphabet, and said local codes being interconnected by their status words, to form at least one coding trellis, each trellis defining a basic code.
• the invention also relates to the coded data transmission devices implementing the coding method described above, the data receiving devices coded using this coding method, implementing decoding means acting symmetrically to the coding, and the encoded data storage devices, comprises coding and / or decoding means according to the above-mentioned methods.
• the invention also relates to computer programs implementing the coding and / or decoding methods described above. 6. List of Figures Other features and advantages of the invention will appear more clearly on reading the following description of a preferred embodiment of the invention, given as a simple illustrative and non-limiting example, and attached drawings, among which: - Figure 1, discussed in the preamble, schematically illustrates the principle of a turbo-code; FIG.
• FIG. 2 is a representation using a Tanner graph of an LDPC code (4, 2);
• FIG. 4 is a Tanner graph illustrating the principle of an error correcting code according to the invention;
• FIG. 6 is a Tanner graph of another exemplary code according to the invention, with trellis of the basic code split into 2 sub-trellises, one with state ending at 0 and the other loopback (or in tail-biting);
• FIG. 7 shows the decomposition of a first local code (6, 4, 2) usable in a global code according to the invention, into three trellis sections each carrying two tag bits;
• FIGS. 8A, 8B and 8C respectively illustrate the three sections of the local code (6, 4, 2) of FIG. 7;
• Fig. 9 is the basic code information transfer curve constructed with a lattice of two-state trellis code sections (6, 4, 2);
• FIG. 10 shows the decomposition of a second local code (4, 3, 2) usable in a global code according to the invention, into two trellis sections each carrying two tag bits; - Figures HA and HB respectively illustrate the two sections of the local code (4, 3, 2) of Figure 10; Fig. 12 is the basic code information transfer curve constructed with a lattice of two-state trellis code sections (4, 3, 2); FIG. 13 shows the decomposition of a third local code (6, 5, 2) usable in a global code according to the invention, into two trellis sections each carrying three tag bits; FIGS. 14A and 14B respectively illustrate the two sections of the local code (6, 5, 2) of FIG. 13; Fig.
• FIG. 15 is the basic code information transfer curve constructed with a lattice of two-state trellis code sections (6, 5, 2);
• FIG. 16 shows an "exploded" lattice, not sectioned, of a fourth four-state local code (8, 7, 2), usable in a global code according to the invention;
• FIG. 17 shows the decomposition of a fifth local code (8, 7, 2) usable in a global code according to the invention, into two trellis sections each carrying four tag bits;
• FIGS. 18A and 18B respectively illustrate the two sections of the local code (8, 7, 2) of FIG. 17; Fig.
• FIG. 19 is the basic code information transfer curve constructed with a trellis of four-state code sections (8, 7, 2); - Figure 20 shows another decomposition of the local code (8, 7, 2) in 2 sections of lattice each carrying 4 tag bits;
• FIGS. 21A and 21B illustrate the two sections of the trellis of the local code of FIG. 20;
• Fig. 22 is the basic code information transfer curve constructed with a lattice of two-state code sections (8, 7, 2);
• - Figure 23 shows the decomposition of a sixth local code (4, 3, 2) to 4 states on Z4;
• FIGS. 24A and 24B show the two lattice sections of FIG. 23.
• the invention is based on a new approach to error correcting codes. , implementing very simple local codes, only error detectors, combined to provide a final overall code simpler and more efficient than known codes.
• the codes of the invention are distinguished by a reduction of the complexity, by the use of binary lattices with low numbers of states (2 and 4 states).
• states binary lattices with low numbers of states (2 and 4 states).
• the resulting codes offer, despite the low complexity of their trellises, a better compromise between complexity, error correction capability and error-floor of the best turbo-codes and current LDPC codes, since these new codes have at least as well good performance in error rate and "error-floor" as little inconvenient in practice.
• the table below summarizes the performance and complexities of some codes obtained, described in more detail later.
• the parameters of a local code are: (number of label bits, dimension, d min max limit of the base code built with this code).
• the code is constructed as follows: the state bits of the local codes are interconnected; at least the majority of the variable bits (which comprise both the information bits and the redundancy bits) are repeated and connected to the code of base via a permutation that changes the order of these bits of repeated variables (not new).
• An advantageous approach of the invention consists in retaining particular local code sections to meet the following criteria: the number of basic codewords (large lattice) of length m bits of weight 2 is less than or equal to m divided by 2; the number of basic codeword of length m bits of weight 3 is non-zero. This approach has been applied for the 6 local codes described below.
• An essential technical element is therefore the use of a trellis composed of small C local codes J connected as described in Figure 4.
• Q This local code sequence J 41 forms the basic code 42 described by a trellis and it is said that the lattice is cyclic, or tail-biting, if it forms a loop.
• the "tail-biting" lattice can be reduced to a conventional non-cyclic lattice if one or more of the "state" bits between the local codes Ci are "forced” to 0 by construction.
• This 0-state trellis termination technique is a well-known technique for simplifying decoding. As illustrated in FIG. 6, the division of a trellis into several sub-trusses 61 and 62 is possible. This makes it possible to parallelize the decoding calculations on each of the sub-lattices (before synthesizing these calculations performed in parallel) and is done without significant loss of performance by taking a sufficient number of sections in each of the sub-lattices.
• the schematic notation of the trellis section means that the transition from the input state 0 to the output state 0 can occur if the tag bits are 00 or 11. It is said that it is a branch of double label.
• the labels of the same branch are placed in braces on the same line corresponding to the same input state and the successive braces correspond in the same order to the successive arrival states.
• the transition from the input state 0 to the output state 0 can be carried out if the tag bits are equal to 00 or 11, and the transition of the state 0 input to the output state 1 can be achieved if the tag bits are 01 or 10.
• FIG. 12 shows, according to the same principle as explained above, the decomposition of the local code (4,3,2) into 2 sections of trellis each carrying 2 bits of label, and Figures HA and HB the 2 sections of the lattice of the local code (4,3,2) with 2 corresponding states.
• FIG. 15 shows, according to the same principle as explained above, the decomposition of the local code (6, 3, 2) into 2 sections of trellis each carrying 3 bits of tag, and FIGS. 14A and 14B the 2 sections of the trellis of the local code (6,3,2) with 2 corresponding states.
• FIG. 15 shows that the information transfer curve below tangents the straight line with 30% of slope at the origin, which reflects a correction capacity of 30% of global code erasures for a theoretical maximum of 33.33% for a 2/3 performance code.
• Figure 16 describes the "exploded" trellis in 8 sections each having a tag bit.
• the bits ( ⁇ o , ⁇ j , è 2 , è 3 ) and the bits (b 4 , b 5 , b 6 , b 7 ) can be grouped into 2 sections which each have 4 input states and 4 output states as shown in Figures 17, 18A and 18B.
• FIG. 22 8.5 trellis section of the 2-state local code (8.7.2)
• Figure 20 shows, according to the same principle as explained above, the decomposition of the local code (8, 7, 2) into 2 trellis sections carrying each 4 bits of tag, and Figs. 21A and 21B the 2 sections of the trellis of the local code (6,3,2) with 2 corresponding states.
• example code (4, 3, 2) with 4 states on Z4 Z4 is the set of integers ⁇ 0,1,2,3 ⁇ with the addition modulo 4.
• This code example is easily generalizable to other alphabets because it suffices to replace the law "addition on Z4" by the law of addition on the new alphabet considered.
• the labels of a multiple branch are obtained from this code repetitively by adding a word of the same length ("coset leader" or side class representative).
• a multiple branch (or multibranch) 01 will have labels ⁇ 01,12,23,30 ⁇ .
• Bibliography [1] Gallager, “Low Density Parity Check Codes,” Ph.D.Thesis, MIT, July 1963. [2] RMTanner, "A recursive aproach to low complexity codes, "IEEE Transactions on Information Theory, vol IT-27, pp.533-547, Sept. 1981. [3J C.Berrou, A.Glacreme and P.Thitimajshima,” Near Shannon limit error-correcting coding and decoding: Turbo codes, pp.1064-1070, Proceedings of the International Communications Conference (ICC), May 1993, Gene goes.

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