Classifications

• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
  • G05F1/70—Regulating power factor; Regulating reactive current or power

Definitions

• the present invention relates to electrical power control circuitry and, more particularly, to an improved system for monitoring and correcting the power factor of a power installation which employs a power measurement integrated circuit.
• Electrical power is an enormously versatile and convenient source of energy. However, there are costs in generating and distributing electrical energy, which tend to increase when demand for electrical power increases. For this reason, there is always a motivation for increasing the efficiency of electrical power transmission and utilization and, conversely, for reducing losses and wastes in the delivery and use of electrical energy.
• Alternating current electrical power is characterized by a phase relationship between the current and voltage.
• Current phase lagging the voltage phase results from a preponderance of inductive loads, while current phase leading the voltage phase results from capacitive loads.
• An in-phase relationship results from resistive loads or a balance of inductive and capacitive loads.
• In-phase current results in "real" or resistive power, also known as active power, while out-of-phase current results in reactive power from the influence of inductive or capacitive reactance in the power circuit.
• the vector sum of active power and reactive power is called apparent power. In a single phase AC system, the angle between the active power and the apparent power is the same as the phase angle between the voltage and current.
• power factor is equal to the cosine of the phase angle therebetween or between the active power and the apparent power. Power factor maximizes at a value of unity when the relationship is effectively resistive, is positive and less than one when inductive, and is negative and less than one when capacitive.
• Relatively small amounts of energy are also used for communications, computers, entertainment devices, and the like. Although reactive power is not “consumed” as such in useful work, it is delivered to the power system and returned to the generator.
• power or energy measurement circuits There is a type of integrated circuits or chips referred to as power or energy measurement circuits which have been developed principally for use in solid state power meters for measuring power consumption by electrical utility customers.
• Such chips measure a number of parameters associated with the flow of AC electrical energy from a source to a customer's electrical installation, including parameters which indicate levels of reactive power or energy drawn by an installation.
• apparatus or methods using such chips to compensate for reactive power drawn for power factor correction purposes are not known to have been previously developed.
• the present invention provides a system for correcting the power factor of relatively small power installations, such as residences, apartments, small businesses, and also individual appliances, such as refrigerators, air conditioners, heat pumps, dish washers, laundry washers and dryers, and the like.
• the system of the present invention generally includes a plurality of reactance units or capacitors which are selectively coupled to a power line and sensor circuitry to determine if the capacitors connected to the power line have favorably affected the power factor.
• the present invention measures an electrical parameter of the power drawn by a load of a power installation which is capable of indicating a level of reactive power drawn by the load and couples a combination of reactance elements to the power line to substantially compensate for the level of reactive power indicated by the electrical parameter measured.
• the present invention employs power or energy measurement integrated circuits or chips in power sensor circuitry, coupled either to the power line or to a load connectable to the power line, to derive reactive power indicating parameters from voltage and current measurements on the power line.
• the invention is directed to a first embodiment in which the power measurement chip provides a reactive power value having a positive or negative sign to indicate an inductive or capacitive power value, which is derived from periodic measurements of power line voltage and load current.
• a controller or microprocessor periodically acquires the signed reactive power value from the power measurement chip and calculates a combination of capacitance values to compensate for the reactive power level drawn by the load on the power line and controls the switching of the capacitance combination across the power line.
• a power measurement chip periodically derives values of active power and apparent power from voltage and current measurements.
• the controller periodically acquires the values of active power and apparent power and derives a power factor value from the ratio of active power to apparent power.
• the controller then calculates a combination of capacitance values to maximize the power factor value, to compensate for the level of reactive power drawn, and controls the switching of the capacitance combination across the power line.
• current sensing circuitry is placed in a circuit branch which includes the load and which is in parallel with the compensating capacitors.
• load current measured by the current sensing circuitry is not affected by compensating capacitors which might already connected across the power line or which might be excessive because of a change in operation of the load.
• the controller in the second embodiment simply calculates the most appropriate capacitance combination to compensate for the currently derived value of power factor, regardless of the previously calculated capacitance combination.
• the present invention may average a number of measurements over time and takes no compensation action unless a change of a selected difference is measured in less than a selected interval of time. This approach, thus, reduces switching transients by making the system relatively immune to small variations in the power drawn.
• the present invention bases compensating capacitance increments on multiples of a base capacitance which would result in a compensating reactance that would draw about one ampere of current at the nominal power line frequency and voltage.
• the base capacitance is 22 microfarads for a power installation with a line frequency of 60 hertz and a nominal voltage of 110 volts.
• the set of capacitors includes capacitors with capacitance values: 1 , 2, 4, 8...128 times the base capacitance.
• a typical installation of the present invention includes a set of eight compensating capacitors with values ranging in powers of two from 1 to 128 times the base capacitance of 22 microfarads.
• the compensating capacitors are connected through latching switches across the power line.
• the latching switches are interfaced to an eight-bit output port of a controller, such as a microprocessor or microcontroller.
• the controller can connect any one of 256 combinations of the capacitors across the power line or disconnect any or all of the capacitors from the power line by writing an appropriate binary word to the output port in which the bit content of the binary word corresponds to the combination of capacitors to be connected or disconnected.
• Fig. 1 is a block diagram illustrating the principal components of an automatic power factor correction system using a power measurement chip which embodies the present invention.
• FIG. 2 is a more detailed block diagram illustrating further details of the automatic power factor correction system.
• Fig. 3 is a block diagram illustrating a capacitor bank and switching circuitry of the automatic power factor correction system.
• Fig. 4 is a flow diagram illustrating the principal process steps of the present invention for correcting power factor based on acquisition of a signed reactive power value obtained from a power measurement chip.
• Fig. 5 is a flow diagram illustrating the principal process steps of a second embodiment of the present invention in which a power factor value is derived from values of active power and apparent power obtained from a second type of power measurement chip.
• Fig. 6 is a block diagram illustrating a preferred configuration of the principal components of an automatic power factor correction system of the second embodiment of the present invention.
• the reference numeral 1 generally designates a power factor correction apparatus for automatically correcting the power factor of a power installation including one or more power loads drawing a variable level of reactive power at random times from an AC power source 3, such as a generator of an electrical utility company, by way of a power line 4.
• the present invention measures a one or more electrical parameters of the power drawn by the load 2 which are capable of indicating a level of reactive power drawn by the load and controls the coupling of an appropriate combination of reactance elements 6, such as capacitors, to the power line 4 to substantially compensate for the level of reactive power indicated by the electrical parameter measured.
• the electrical parameters of the drawn power are measured by way of a power measurement integrated circuit (IC) or chip 8.
• IC power measurement integrated circuit
• the power factor correction apparatus 1 includes current sensing circuitry
• the apparatus 1 includes a controller 14, such as a microprocessor, which is programmed to periodically query the chip 8 for selected ones of the parameter values to employ in calculations to determine the appropriate combination of capacitors 6 to couple to the power line 4 to compensate for reactive power drawn by the load 2.
• the controller 14 controls capacitor switching circuitry 16 to connect the selected capacitor combination across the power line 4 to improve the power factor of the load 2, as it would be sensed or "seen" by the power source 3.
• the current sensing circuitry 10 preferably includes a transformer or coil (not shown) which is connected or inductively coupled to one conductor of the power line 4.
• the current sensing circuitry 10 could alternatively be formed by a resistor or other type of element, such as a Hall effect based sensor.
• the signal from the current sensing circuitry 10 is coupled to the power measurement chip 8 by way of signal conditioning circuitry 20 which includes scaling elements, such as a resistor network (not shown) and low pass filtering elements, such as a capacitor network (not shown).
• the voltage sensing circuitry 12 includes signal conditioning circuitry 22 including scaling components, such as a resistor network (not shown) and low pass filtering components, such as a capacitor network (not shown).
• conditioning circuitry 20 and 22 depends on the range of signal levels required by the particular chip 8 employed.
• the illustrated controller 14 includes ROM (read-only memory) 26 which stores programs and fixed data and RAM (read/write memory) 28 which stores temporary data.
• ROM read-only memory
• RAM read/write memory
• the ROM 26 may be an EPROM or other type of field programmable
• the RAM 28 may include flash RAM or other non-volatile type of memory circuitry.
• the controller 14 may be implemented by any of a number of known types of embedded microprocessors, microcontrollers, and the like.
• the controller 14 may, for example, be one of the PIC16F87X series of microcontrollers manufactured by Microchip Technology, Inc. (documentation for which can be found at www.microchip.com).
• the controller 14 includes a parallel port 32 (Fig. 3) which is interfaced through a set of drivers 36 and solid state relays or latching switches 16 to a plurality of capacitors 38 of the capacitor bank 6.
• Fig. 3 illustrates details of the capacitor bank 6 and the manner of interfacing the capacitors 38 of the bank 6 to the port 32 of the controller 14.
• the 32 is illustrated as having eight terminals 42 labeled P0 through P7. Each terminal 42 is connected through a latching switch 16 to a specific capacitor 38.
• the capacitors 38 are shown as having values (1 X C) through (128 X C), varying in powers of two or doubling.
• the value "C” is selected as the value of capacitance which will form a capacitive reactance which will draw approximately one ampere of current at the nominal line frequency and line voltage of the power line 4.
• the value of "C” is 22 microfarads for a line frequency of 60 hertz and a nominal AC line voltage of 110 volts.
• the value of "C" could be determined to draw some other value of current, such as one-half ampere, a quarter of an ampere, or the like, depending on the degree of correction resolution desired. In such a case, it would still be desirable to vary the values of capacitors 38 in the capacitor bank 6 by multiples of 2 for convenient binary switching control of the capacitors 38.
• additional ports 32 could be employed and a larger number of capacitors 38 used to provide for flexibility in the range and/or resolution of power factor correction in the present invention.
• the compensation resolution of the apparatus 1 is one ampere of correction.
• the set of capacitors 38 in the illustrated capacitor bank 6, and activated in the matter illustrated in Fig. 3, can provide any capacitance value from zero to 255 times "C", in increments of "C".
• the controller 14 simply writes a binary word to the port 32 in which the binary content of the word corresponds to the capacitors 38 it has been determined require coupling to the power line 4.
• the drivers 36 provide isolation and driving current to operate the solid state relays 16, such as triacs, SCR's, or the like. The relays or switches 16, or the drivers
• the apparatus 1 may be set up to use either a positive logic, in which a logic one activates the switches 16, or a negative logic, in which a logic zero activates the switches 16.
• Each set of a capacitor 38 and its latching switch 16 is connected across the power line 4.
• the sets of capacitors 38 with latching switches 16 can be connected in parallel and simply plugged into a convenient outlet connected to the power line 4.
• Fig. 3 shows load appliances 2 which are connected by respective appliance switches 44 to the power line 4. It is also foreseen that the apparatus 1 could be incorporated within an appliance 2 for providing power factor correction solely for that particular appliance rather than a plurality of appliances or a whole household.
• the power measurement integrated circuit 8 is one of a type of integrated circuits which are also referred to as power measurement circuits, energy measurement circuits, power/energy metering circuits, or the like. They are provided by their manufactures principally for incorporation into power meters, such as those employed by electrical utility companies for metering electrical power usage and energy consumption by utility customers. Power measurement circuits with varying capabilities and specifications are manufactured by Analog Devices, Inc. (www.analog.com) and
• Cirrus Logic, Inc. www.cirrus.com
• comparable types of chips may be available from other manufacturers. Such chips incorporate sampling control circuitry, scaling circuitry, analog to digital conversion circuitry (ADC), storage registers, mathematical processing software, and data interfaces. Published specifications and application notes detail the manner of coupling such devices to power lines for measuring power line parameters and for interfacing to host systems for obtaining values of the parameters measured. In the present invention, the use of such types of chips reduces the complexity of the apparatus 1 and increases the flexibility of design and use of the apparatus 1.
• the chip 8 is a model ADE7753 manufactured by Analog Devices, Inc. Documentation for this chip is available on the website identified above.
• the ADE7753 periodically derives a signed reactive power value, among other parameters, from the voltage and current values measured through the current and voltage sensing circuitry 10 and 12 and stores this value in a particular register within the chip 8 which can be queried by the controller 14, over a serial interface between the chip 8 and the controller 14. From the signed reactive power value, the controller 8 can calculate the value of capacitance required to compensate for the reactive component of power drawn by the load 2, using known formulas. From the known voltage of the power line 4, or a measured voltage value stored in an appropriate register, and the measured reactive power, the reactive current drawn by the load 2 can be calculated, along with the reactive impedance or reactance of the load 2.
• the compensating reactance is numerically the same as the load reactance with the opposite sign, from which the required compensating capacitor combination can be calculated. It is foreseen that there are other ways to determine the compensating capacitance value from the signed reactive power value, either in combination with known factors or with other parameters derived by the particular chip
• Fig. 4 illustrates the principal steps of a first embodiment of a method of power factor correction 47 according to the present invention.
• the controller At step 48, the controller
• step 49 the controller 14 calculates the reactance required to compensate for the reactive power value obtained.
• step 50 the calculated reactance is connected across the load 2 or power line 4.
• the process 47 obtains a signed reactive power value, it has the capability of detecting overcorrection of the power factor of the load 2, such as when the reactive power drawn by the load 2 decreases. It is not desirable for the process 47 to track variations in the reactive power drawn by the load 2 too closely. Thus, some averaging and comparing of current and past values of measured reactive power may be desirable. Additionally, it is not desirable to attempt to correct the power factor of the load 2 to precisely unity, because of undesirable resonance effects which can occur. It has been found that maximizing the power factor to about 0.95 is an optimum correction in the process 47.
• Figs. 5 and 6 illustrate a power factor correction process 54 (Fig. 5) and apparatus 56 (Fig. 6) which form a second embodiment of the present invention.
• the process 54 and apparatus 56 are particularly adapted for use with a power measurement integrated circuit 58 which does not provide a signed reactive power value but which does provide values of active power and apparent power, from which a power factor value for a load 60 may be obtained.
• a power measurement integrated circuit 58 which does not provide a signed reactive power value but which does provide values of active power and apparent power, from which a power factor value for a load 60 may be obtained.
• Such a chip 58 could be implemented by a model CS5460 manufactured by Cirrus Logic, Inc. Documentation for the CS5460 can be obtained from the website listed above.
• the apparatus 56 provides power factor correction for the load 60 which receives electrical power from an AC power source 62 by way of a power line 64.
• the apparatus 56 includes current sensing circuitry 66 and voltage sensing circuitry 68 which may be similar to the circuitry 10 and 12 of the apparatus 1.
• the circuitry 66 and 68 are coupled to the chip 58 by means of respective scaling and filtering circuitry (not shown).
• the chip 58 communicates with a controller 70, which may be similar to the controller 14.
• a set of capacitor switching elements 72 is coupled between the controller 70 and a bank of capacitors 74 which are connected on one side to one conductor of the power line 64.
• the switches 72 are connected to the other conductor of the power line 64 and complete circuits between selected ones of the capacitors 74 and the power line 64 when corresponding ones of the switches 72 are activated by the controller 70.
• the switches 72 and capacitors may be substantially similar to the switches 16 and capacitors 6.
• the power measurement chip 58 periodically derives values of active power and apparent power, among other parameters, from current and voltage measurements made through the current and voltage sensing circuitry 66 and 68 and stores these values in particular registers within the chip 58.
• the controller 70 is programmed to acquire the active power value from the chip 58 in step 76 of the process 54 and the apparent power value in step 78.
• the controller 70 calculates a power factor value from the ratio of the active power value to the apparent power value.
• the controller 70 calculates the combination of capacitors 74 required to substantially maximize the power factor value, to thereby compensate for the level of reactive power drawn by the load 60.
• the objective of the process 54 is to achieve a power factor value of about 0.95.
• the controller 70 controls the connection of the required capacitors 74 across the power line 64, by way of the capacitor switches 72, in step 84.
• the apparatus 56 could be interconnected to the load 60 in such a manner that the process 54 is only activated with the load 60 is electrically activated.
• the particular power measurement chip 58 used in the apparatus 56 does not directly provide a signed value of reactive power drawn by the load 60.
• the chip 58 is not adapted to directly sense overcorrection of the power factor, such as when the level of reactive power decreases, as would occur if mechanical loading of an electrical motor were reduced.
• the chip 58 is capable of deriving parameters from which a signed level of reactive power could be determined or by comparing current parameters with previous parameters, the apparatus 56 is particularly configured so that such an indirect manner of determining a signed level of reactive power is not necessary.
• the current sensing circuitry 66 is connected in series with the load 60 in a circuit branch 86 which is connected in parallel with the power source 62 and any capacitors74 connected across the power line 64. Because the current sensing circuitry 66 is on the load side of the capacitors 74, rather than on the source side, the current sensed by the circuitry 66 is only affected by the characteristics of the load 60 and not by the capacitors 74. Thus, the chip 58, in calculating a compensating reactance, simply calculates the combination of capacitors

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• 2005
  • 2005-02-25 JP JP2007500976A patent/JP2007525938A/ja active Pending
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  • 2005-02-25 CA CA002556779A patent/CA2556779A1/en not_active Abandoned
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