EP1640966B1 - Procédé et circuit pour le rafraîchissement de trame - Google Patents

Procédé et circuit pour le rafraîchissement de trame Download PDF

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Publication number
EP1640966B1
EP1640966B1 EP20040022686 EP04022686A EP1640966B1 EP 1640966 B1 EP1640966 B1 EP 1640966B1 EP 20040022686 EP20040022686 EP 20040022686 EP 04022686 A EP04022686 A EP 04022686A EP 1640966 B1 EP1640966 B1 EP 1640966B1
Authority
EP
European Patent Office
Prior art keywords
physical address
state
pixel data
video
frame buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Not-in-force
Application number
EP20040022686
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German (de)
English (en)
Other versions
EP1640966A1 (fr
Inventor
Ping-Yeh Chen
Yung-Che Pao
Szu-Han Wu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HTC Corp
Original Assignee
HTC Corp
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Filing date
Publication date
Application filed by HTC Corp filed Critical HTC Corp
Priority to EP20040022686 priority Critical patent/EP1640966B1/fr
Publication of EP1640966A1 publication Critical patent/EP1640966A1/fr
Application granted granted Critical
Publication of EP1640966B1 publication Critical patent/EP1640966B1/fr
Not-in-force legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to a frame refresh method and circuit, and more particularly to a frame refresh method for use in a handheld electronic device.
  • System pixel data is saved to a random access memory (RAM) providing pixel data updates when the power of the video chip is turned off. Pixel data is copied by the central processing unit (CPU) and sent to a video frame buffer for refreshing pixel data.
  • RAM random access memory
  • FIG 1 is a flowchart of a traditional frame refresh method for a handheld electronic device.
  • FIG 2 shows the internal circuit of the handheld electronic device 1, which comprises an operating system 10(OS), a central processing unit (CPU) 11, a RAM 12 and a video frame buffer 13.
  • the frame refresh method comprises, first, in step S1, the operating system (OS) writes pixel data to the CPU.
  • step S2 the CPU 11 writes the pixel data to the RAM 12.
  • operating system 10 sends a memory copy command to the CPU 11.
  • step S4 according to the received copy command, the CPU 11 copies the pixel data stored in the RAM 12.
  • step S5 the copied pixel data is stored in the video frame buffer 13 .
  • the disadvantage of conventional refreshing method is the frequent updating of pixel data of the display by the operating system.
  • the CPU must write the pixel data into RAM and copy the pixel data out of RAM to the video frame buffer for every refresh.
  • the copy procedure consumes excessive CPU resources and power and degrades deteriorate system performance.
  • the EP 1 262 939 Al describes a method for updating a frame buffer with reduced power consumption.
  • the display module includes a display and a display frame buffer.
  • the display module is coupled to a specific integrated circuit having a local frame buffer and a frame buffer update hardware.
  • the specific integrated circuit is provided for performing a software, in particular, for providing a display server and a application software.
  • the display server writes data to a local frame buffer which provides the data to update hardware component.
  • the update hardware component provides the data to the display.
  • FIG 3 is a circuit block diagram of an embodiment of the invention.
  • a handheld electronic device such as a mobile phone, a personal digital assistance or a portable computer, comprises an operating system 10, a central process unit (CPU) 11, an address lookup table 20, a RAM 12, and a video frame buffer 13.
  • CPU central process unit
  • RAM random access memory
  • video frame buffer 13 a circuit block buffer
  • the CPU 11 is instructed by the operating system 10 to write a pixel data and a virtual address.
  • the address lookup table 20 installed in a memory 2 stores the virtual address and a corresponding physical address, and can be read by the CPU 11 according to a power state of a video chip for searching out the corresponding physical address.
  • the physical address may be a first physical address or a second physical address.
  • the first physical address is inside a RAM 12.
  • the second physical address is inside a video frame buffer 13.
  • the RAM 12 is coupled to the CPU 11 for receiving the pixel data during an off state and receiving pixel data copied from the video frame buffer 13 when the power state of the video chip is turned from an on state to the off state.
  • the video frame buffer 13 is coupled to the CPU 11 and the RAM 12 for receiving the pixel data during an on state and receiving pixel data copied from the RAM 12 when the power state of the video chip is turned from the off state to the on state.
  • FIG 4 illustrates a frame refresh method.
  • step S1 a pixel data and a virtual address are written into the CPU by the operating system.
  • step S2 the power state of the video chip is determined by the CPU. If the power state is in an off state, the address lookup table is searched by the CPU for transforming the virtual address to a corresponding first physical address in step S3, wherein the first physical address is inside the RAM.
  • step S4 the pixel data is written to the first physical address of the RAM by the CPU.
  • step S5 If the power state of the video chip is in an on state, the address lookup table is searched by the CPU for transforming the virtual address to a corresponding second physical address in step S5.
  • the second physical address is inside the video frame buffer.
  • step S6 the pixel data is written to the second physical address of the video frame buffer by the CPU.
  • FIG 5 is a flowchart when the power of the video chip is turned from an off state to an on state.
  • step 4.1 when the CPU detects that the power state of the video chip is turned from an off state to an on state.
  • the video chip is turned on and the interrupt functions are then turned off for avoiding other interruptions.
  • step 4.3 the content of the address lookup table is changed by the CPU in step 4.3.
  • the first physical address which corresponds to the virtual address is changed to the second physical address.
  • the pixel data stored in the RAM are copied by the CPU and written to the video frame buffer.
  • step 4.5 the interrupt functions are recovered by the CPU.
  • FIG 6 is a flowchart showing when the power state of the video chip turned from an on state to an off state.
  • step 6.1 when CPU detects that the power of the video chip is turned from an on state to an off state.
  • step 6.2 the interrupt functions are turned off by the CPU to prevent other interruptions.
  • step 6.3 the pixel data stored in the video frame buffer is copied and written to the RAM.
  • step 6.4 the content of the address lookup table is changed by the CPU. The second physical address corresponding to the virtual address is changed to the first physical address.
  • step 4.5 the video chip is turned off and the interrupt functions are recovered by the CPU.
  • the frame refresh method and circuit of an embodiment of the invention eliminates the need to copying pixel data each time. Additionally, the video chip is turned off when the power of the video chip is in an off state, thus saving more power. Further, the content of the address lookup table can be changed according to the power state. When the power state is in an off state, the pixel data is written to the RAM directly. When the power state is in an on state, the pixel data is written to the video frame buffer directly, thus increasing the frame refresh performance.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Claims (13)

  1. Procédé d'actualisation de trame, apte à être mis en oeuvre dans un dispositif électronique portatif (1), le dispositif électronique portatif (1) comprenant une unité centrale (11), une mémoire vive (12) et une puce vidéo comprenant une mémoire tampon de trame vidéo (13), le fonctionnement dudit dispositif électronique portatif (1) étant commandé par un système d'exploitation (10), le procédé comprenant les étapes de :
    l'unité centrale (11) reçoit du système d'exploitation (10) un signal concernant l'écriture [a] de données de pixels à afficher (S1),
    le procédé étant caractérisé en ce que :
    l'unité centrale (11) détermine un état de puissance de la puce vidéo (S2) ; et
    l'unité centrale (11) écrit les données de pixels dans la mémoire vive (12) ou dans la mémoire tampon de trame vidéo (13) dans la puce vidéo en fonction de l'état de puissance de la puce vidéo (S4 ou S6).
  2. Procédé d'actualisation de trame selon la revendication 1, caractérisé en ce que le signal comprend en outre une adresse virtuelle correspondant aux données de pixels, l'adresse virtuelle correspondant à une première adresse physique ou à une deuxième adresse physique, la première adresse physique étant à l'intérieur de la mémoire vive (12) et la deuxième adresse physique étant à l'intérieur de la mémoire tampon de trame vidéo (13).
  3. Procédé d'actualisation de trame selon la revendication 2, caractérisé en ce que, lorsque l'état de puissance est dans un état hors tension, l'adresse virtuelle correspond à la première adresse physique, et les données de pixels sont écrites dans la mémoire vive (12).
  4. Procédé d'actualisation de trame selon la revendication 2, caractérisé en ce que, lorsque l'état de puissance est dans un état sous tension, l'adresse virtuelle correspond à la deuxième adresse physique, et les données de pixels sont écrites dans la mémoire tampon de trame vidéo (13).
  5. Procédé d'actualisation de trame selon la revendication 3, caractérisé en ce qu'il comprend en outre, lorsque l'état de puissance de la puce vidéo est passé d'un état hors tension à un état sous tension, les étapes suivantes :
    le changement de la première adresse physique correspondant à l'adresse virtuelle à la deuxième adresse physique ; et
    la copie des données de pixels de la mémoire vive (12) dans la mémoire tampon de trame vidéo (13).
  6. Procédé d'actualisation de trame selon la revendication 4, caractérisé en ce qu'il comprend en outre, lorsque l'état de puissance de la puce vidéo est passé d'un état sous tension à un état hors tension, les étapes suivantes :
    la copie des données de pixels de la mémoire tampon de trame vidéo (13) dans la mémoire vive (12) ; et
    le changement de la deuxième adresse physique correspondant à l'adresse virtuelle à une première adresse physique.
  7. Dispositif électronique portatif (1), comprenant :
    une unité centrale (11), dans lequel le fonctionnement dudit dispositif électronique portatif (1) est commandé par un système d'exploitation (10) ;
    au moins une table de recherche d'adresse (20) dans laquelle l'unité centrale (11) peut effectuer des recherches ;
    une mémoire vive (12) couplée à l'unité centrale (11) ; et
    une mémoire tampon de trame vidéo (13), installée dans une puce vidéo et couplée à l'unité centrale (11) et à la mémoire vive (12), caractérisé en ce que l'unité centrale (11) est apte à recevoir du système d'exploitation (10) un signal concernant l'écriture [a] de données de pixels pour afficher des données de pixels, à la réception du signal l'unité centrale (11) est apte à contrôler un état de puissance de la puce vidéo et à écrire les données de pixels dans la mémoire vive (12) ou dans la mémoire tampon de trame vidéo (13) en fonction de l'état de puissance de la puce vidéo.
  8. Dispositif portatif selon la revendication 7, caractérisé en ce que le signal comprend en outre une adresse virtuelle correspondant aux données de pixels, l'adresse virtuelle correspondant à une première adresse physique ou à une deuxième adresse physique, la première adresse physique étant à l'intérieur de la mémoire vive (12) et la deuxième adresse physique étant à l'intérieur de la mémoire tampon de trame vidéo (13).
  9. Dispositif portatif selon la revendication 7, caractérisé en ce que, lorsque l'état de puissance de la puce vidéo est dans un état hors tension, le contenu dans la table de recherche d'adresse (20) est l'adresse virtuelle correspondant à la première adresse physique.
  10. Dispositif portatif selon la revendication 8, caractérisé en ce que, lorsque l'état de puissance de la puce vidéo est dans un état sous tension, le contenu dans la table de recherche d'adresse (20) est l'adresse virtuelle correspondant à la deuxième adresse physique.
  11. Dispositif portatif selon la revendication 8, caractérisé en ce que, lorsque l'état de puissance de la puce vidéo est passé d'un état hors tension à un état sous tension, le contenu dans la table de recherche d'adresse (20) est changé de la première adresse physique à une deuxième adresse physique, puis des données de pixels de la mémoire vive (12) sont copiées dans la mémoire tampon de trame vidéo (13).
  12. Dispositif portatif selon la revendication 8, caractérisé en ce que, lorsque l'état de puissance de la puce vidéo est passé d'un état sous tension à un état hors tension, les données de pixels de la mémoire tampon de trame vidéo (13) sont copiées dans la mémoire vive (12) ; et la deuxième adresse physique est changée à la première adresse physique.
  13. Dispositif portatif selon la revendication 7, dans lequel le dispositif portatif (1) est un téléphone cellulaire, un assistant numérique personnel ou un ordinateur portable.
EP20040022686 2004-09-23 2004-09-23 Procédé et circuit pour le rafraîchissement de trame Not-in-force EP1640966B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP20040022686 EP1640966B1 (fr) 2004-09-23 2004-09-23 Procédé et circuit pour le rafraîchissement de trame

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Application Number Priority Date Filing Date Title
EP20040022686 EP1640966B1 (fr) 2004-09-23 2004-09-23 Procédé et circuit pour le rafraîchissement de trame

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EP1640966A1 EP1640966A1 (fr) 2006-03-29
EP1640966B1 true EP1640966B1 (fr) 2012-09-19

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US9196216B2 (en) 2011-12-07 2015-11-24 Parade Technologies, Ltd. Frame buffer management and self-refresh control in a self-refresh display system

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DE69228929T2 (de) * 1992-02-25 1999-12-02 Citizen Watch Co Ltd Flüssigkristallanzeige
US5961617A (en) * 1997-08-18 1999-10-05 Vadem System and technique for reducing power consumed by a data transfer operations during periods of update inactivity
EP1157370B1 (fr) * 1999-11-24 2014-09-03 DSP Group Switzerland AG Unite de traitement de donnees pouvant acceder a la memoire d'une autre unite de traitement de donnees pendant une periode d'attente
EP1262939B1 (fr) * 2001-05-31 2012-02-01 Nokia Corporation Méthode et appareil pour la mise à jour d'un tampon de trame avec consommation d'énergie réduite

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