EP1636846A1

EP1636846A1 - Integrated circuit arrangement with npn and pnp bipolar transistors and corresponding production method

Info

Publication number: EP1636846A1
Application number: EP04735578A
Authority: EP
Inventors: Thomas BÖTTNER; Stefan Drexl; Thomas Huttner; Martin Seck
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2003-06-21
Filing date: 2004-06-01
Publication date: 2006-03-22
Also published as: WO2004114408A1; US20060131694A1; US7968416B2; US20090305477A1; CN100550384C; CN1809926A; DE10327709A1; US7592648B2

Abstract

An integrated circuit arrangement (100) is disclosed amongst other things, containing an NPN transistor (102) and a PNP transistor (104). Transistors with excellent electrical properties are produced when the PNP transistor comprises a recess (142), which defines the width of the emitter connection region (120) of the PNP transistor and the electrically conducting material of the connector region (120) laterally overlaps the recess (142).

Description

description

Integrated circuit arrangement with npn and pnp bipolar transistors and manufacturing process

The invention relates to an integrated circuit arrangement which contains at least one npn bipolar transistor and a pnp bipolar transistor. The npn bipolar transistor contains one another in the following order: an n-doped collector region, which is also referred to below as an edge region,

- A p-doped base region, and an n-doped emitter region, which is also known as

Edge area is called.

The pnp bipolar transistor contains one another in the following order:

a p-doped collector region, which is also referred to below as an edge region, an n-doped base region, and a p-doped emitter region, which is also referred to as an edge region.

The emitter regions are usually doped higher than the collector regions. The dopant concentration of the base region is usually between the dopant concentration of the emitter region and the dopant concentration of the collector region. The integrated circuit arrangement also contains an electrically insulating insulating layer which contains a cutout in the region of the pnp bipolar transistor. The base region of the pnp bipolar transistor is arranged under the cutout in the region of the pnp transistor. Electrically conductive material is arranged in the recess, which is electrically conductively connected to the emitter region of the pnp transistor or which even adjoins the one emitter region. In the electrically insulating layer there is also in the area of the npn transistor a further recess at which the basa area of the npn transistor is arranged.

The edge regions and the base region of a transistor are arranged on emkrastallanem semiconductor material. In the case of the npn transistor, a single-crystal layer was produced in the further cutout, in order, for example, to improve the electrical properties of the transistor, for example the so-called transit frequency, by using two adjoining ecrystalline layers with different basic material. An integrated circuit arrangement with pnp and npn

Transistors are known, for example, from German patent DE 199 58 062 C2, an additional silicidation being carried out there, but this can also be omitted.

It is an object of the invention to provide an easily produced integrated circuit arrangement with npn and pnp bipolar transistors, which in particular have good electrical properties. A manufacturing process is also to be specified

The invention is based on the consideration that, in the method used hitherto, the entire production is carried out optimally neither with regard to the npn bipolar transistor nor with regard to the pnp transistor. The electrical properties of the npn bipolar transistor and the pnp bipolar transistor are reduced. For example, when structuring a polyknstalline silicon layer arranged on the insulating layer in the area of the npn transistor, it cannot be overstated in order to achieve steep flanks, which can be of great importance for the reproducibility of the transistor properties. A strong Uberat tongue is, for example, an overstatement by more than 50 percent or by more than 100 percent. When etching a 200 nm-thick low-poly layer, a 100% overdraft means a doubling of the etching time, which is necessary for etching the 200 nm. During the translation, however, the base connection region of the pnp transistor arranged next to the emitter is partially removed in the region of the pnp transistor, as is the case with the method according to patent specification DE 199 58 062 C2. The invention is also based on the consideration that the simultaneous use of layers for the construction of the pnp transistor and the npn transistor should also be retained in the integrated circuit arrangement according to the invention. In the circuit arrangement according to the invention, the insulating layer is therefore used further on the emitter region or on the emitter connection region of the pnp transistor than previously, so that the cutout adjoins the connection region of the emitter of the pnp transistor and thus the width of the electrical contact between the emitter and emitter connection region and indirectly also specifies the width of the emitter region. In addition, the electrically conductive material is structured in such a way that, after the structuring, electrically conductive material of the connection region also adjoins the insulating layer outside the cutout. As a result of this measure, the insulating layer serves as an etch stop layer and not the sensitive partial area of the base connection area, which is located next to the emitter area. Due to the undimmed base connection area, the base connection resistance remains small. As a result, the maximum oscillation frequency becomes large. The minimum noise figure and delay times decrease. In addition, the reproducibility of the aforementioned parameters is improved. Further circuitry effects are evident from the further explanations. In configurations, the cutout in the area of the pnp transistor also borders on the emitter area. This is achieved in that after the introduction of the electrically conductive material, dopers made of this material diffuse into the material lying under the recess and form the emitter region there.

In another embodiment, the electrically conductive material completely fills the recess, so that no other material and no empty spaces are present in the recess. In a next embodiment, the electrically insulating layer is a flat layer which is arranged on a flat substrate. The flat substrate contains, for example, a main substrate area and an epitaxial layer of uniform thickness arranged thereon.

In a further development of the circuit arrangement, a low-crystal layer is arranged in the further cutout, ie in the cutout of the npn transistor, which contains a different base material than the edge region of the npn transistor which is not arranged in the cutout. The low-crystal layer preferably contains silicon germanium or silicon germanium carbon as the base material. The eαnkrαstalle material not arranged in the recess of the npn transistor preferably contains silicon as the base material. By using the materials mentioned, transit frequencies of 100 GHz or even 200 GHz can be achieved. Despite these high transit frequencies of the npn transistor, the pnp transistor is not excessively impaired due to the structure of the integrated circuit arrangement

In another development, the electrically conductive material is strongly p-doped semiconductor material, in particular polycrystalline semiconductor material, for example polycrystalline silicon. This material offers the possibility of diffusing me crystal-clear material the emitter area of the to generate pnp bipolar transistor. At the same time, in the further development, outdiffusion provides connection areas for connecting the base area of the npn transistor with a higher doping. Thus, in turn, processes are used both for producing the pnp transistor and for producing the npn transistor. Furthermore, the electrically conductive material can be used to connect the collector region of the pnp transistor. This further simplifies production.

In a next development, spacer elements are located on the side faces of the electrically conductive material and adjacent to the insulating layer. The foot region of the spacers is on the pnp transistor on the insulating layer. The spacers are preferably produced from electrically insulating material, for example from silicon dioxide or silicon nitride. In addition, the spacers can taper with increasing distance from the insulating material. The spacer elements are, for example, so-called single spacer elements or double spacer elements, for the production of which only one layer has been isotropically etched or for the production of which two layers have been used, of which one has been isotropically etched. The spacer elements have an insulation function between the connection areas for the emitter and for the base only in the area of the npn transistor. In the area of the pnp transistor, however, the spacing elements are not disruptive, so that without additional method steps, they are also formed in the area of the pnp transistor and are left there.

In another development, the base region of the pnp transistor is connected via an e crystalline layer, which extends under the isolating layer to at least one base connection recess m in the isolating layer. The low-crystal layer is doped higher in the area of the base connection area than in the base area in order to to reduce the level. In one configuration, the base connection region extends to below a spacer element on the emitter connection region of the pnp transistor or even to below the emitter connection region of the npn transistor. The base connection recess also contains electrically conductive material, in particular highly doped polyconducting silicon or metallic material. In a further development, both the base region of the pnp transistor, the collector region of the npn transistor and the emitter region of the npn transistor are connected via an n-doped semiconductor material layer. This layer is therefore used again several times and connections in transistors of both types of transistor are produced by a single structuring.

In a next development, the edge region of the pnp transistor which is further away from the recess is formed with the aid of a doping region which has the same outline shape as the recess. In other words, the cutout has been used as an implantation mask. The cutout therefore has another function. Such methods are also known as SIC methods (selectively implanted collector). The SIC process enables a small collector area to be created without an additional mask. Due to the small collector area, the parasitic base

Collector capacity significantly reduced compared to a wider collector. The electrical properties of the pnp transistor continue to improve. This increases the incentive to use circuits that contain both npn and pnp transistors. For example, current sources at positive potential can be realized more easily with pnp transistors than with npn transistors. Up to now, an SIC process was only possible in the area of the npn transistor when npn and pnp transistors were manufactured at the same time.

In a next development of the circuit arrangement according to the invention, the pnp transistor is designed as a multi-emitter Transistor formed, which contains at least two recesses, on which outside the respective recess electrically conductive material of the connection area of an emitter adjoins. In the circuit arrangement according to the invention, the width of the emitter can be reduced in comparison with previous pnp transistors m circuits with npn transistors. A small emitter width results in good high-frequency properties of the transistor, but reduces the maximum permissible switching current. In order to nevertheless be able to switch larger currents, the arrangement of a plurality of emitter regions next to one another also becomes attractive, the total chip area required being small owing to the reduced emitter width. It is therefore possible to produce multαemαtter pnp transistors with good high-frequency properties and high switchable current intensities on a small chip area.

In another development, the doping contained on the circuit arrangement according to the invention is of the opposite type to the types specified above. Accordingly, the base region of the pnp transistor would, for example, be arranged in a recess which is located in the insulating layer.

In another aspect, the invention relates to a method for producing an integrated circuit arrangement, in particular the circuit arrangement according to the invention or one of its developments. The above-mentioned technical effects thus also apply to the method according to the invention. The following steps are carried out in the method according to the invention:

- Applying an insulating layer on em crystal semiconductor material, for example on crystal silicon, structuring the insulating layer with the creation of a recess in the area of the pnp transistor or the pnp transistor still to be produced. The base region of the pnp transistor is located below the cutout or the base region is still being formed. Applying a connection layer made of electrically conductive material or material convertible to such a material onto the structured insulating layer, ie in particular m-situ doping or subsequent doping of semiconductor material,

- Structuring the connection layer to produce a connection area for the emitter region of the pnp transistor in the recess and on the insulating layer outside the recess, - Generating the base region of the npn transistor of the insulating layer after structuring the connection layer.

In a further development, connections made of metal are used to connect the base region of the pnp transistor, which penetrate the insulating layer. In an alternative development, n-doped connection areas are used which overlap the connection area for the emitter of the pnp transistor. No additional chip area is required for the overlap, since the emitter already overlaps the insulating layer by a predetermined distance.

The following are exemplary embodiments of the invention

Hand explained with the accompanying drawings. Darm shows: FIG. 1 the preparation of a base connection area of a pnp transistor with simultaneous overetching in the area of an npn transistor,

2 shows an integrated circuit arrangement with a pnp transistor and an npn transistor, FIGS. 3 and 4

Manufacturing stages in the manufacture of the circuit arrangement shown in Figure 2, and

5 shows an integrated circuit arrangement with a multi-iter pnp transistor and with an npn transistor.

Figure 1 shows the manufacture of an integrated circuit arrangement 8 according to the German patent DE 19958062 C2. The integrated circuit arrangement 8 contains a p-doped substrate made of silicon, not shown. There is an n-epitaxial layer 10 on the substrate, which has been n-doped on its surface in the region of the pnp transistor, see doping region 12 which later forms the base connection region of the pnp transistor. The dopant concentration in the doping region 12 is, for example, 10 ^{μs of} dopant atoms per cubic centimeter, so that the doping region 12 is suitable for forming a base region of the pnp transistor. Below the doping region 12 there is a doping region 14, to which an eme p doping of, for example, 10 ¹⁷ doping atoms per cubic centimeter has been generated.

In the area of the npn transistor, on the surface of the n-epitaxial layer 10 there is a doping region 16, which is n-doped and has, for example, the basic doping of the n-epitaxy of 10 ¹⁶ doping atoms per cubic centimeter in this production stage. The doping region 16 is later doped even higher than the collector region of the npn transistor.

On the n-epitaxial layer 10 there is an insulating layer 18, which for example has a thickness of 100 nm and consists of silicon dioxide. In the area of the pnp transistor, the insulating layer 18 is recessed over a large area, so that it is not shown in FIG. 1. In contrast, in the area of the npn transistor, in particular above the doping area 16, the insulating layer 18 is present and is still unstructured. After the application of the insulating layer 18, a heavily p-doped polyconductive silicon layer 20 was deposited over the entire area, which is referred to below as the polysilicon layer 20. For example, in the polysilicon layer 20, the number of doping atoms is 10 ²⁰ doping atoms per cubic centimeter. The is in the area of the pnp transistor

Polysilicon layer 20 due to the lack of insulating layer 18 on the doping region 12. In the area of the npn In contrast, the transistor, the polysilicon layer 20 lies on the insulating layer 18.

An insulating cover layer 22 was applied over the entire surface above the polysilicon layer 20. Thereafter, photoresist 24 was applied to the cover layer 22, exposed and developed, so that the regions of the photoresist 24 shown in FIG. 1 are left standing, i.e. above an emitter connection area of the pnp transistor and above a base connection area of the npn transistor.

An etching is then carried out for structuring the cover layer 22 and for structuring the underlying polysilicon layer 20, for example with the aid of reactive ion etching, see arrows 26 and 28. The reactive

Ion etching is carried out selectively to the insulating layer 18 when the polysilicon layer 20 is etched. In order to completely remove oblique flanks 30 of the polysilicon layer 20 in the area of the npn transistor, a strong over-etching would be necessary. Due to the strong overetching during the etching of the polysilicon layer 20, the doping region 12 was severed in the region of the pnp transistor. For this reason, it is only possible to make a slight overstatement, the doping region 12 being etched on and thus reducing its original thickness D1 by a thickness D2. In addition, the selectivity in the region of the pnp transistor when the polysilicon layer 20 is etched is considerably less than the selectivity in the region of the npn transistor, where the insulating layer 18 made of silicon dioxide lies under the polysilicon layer 20, due to the silicon lying under the polysilicon layer 20.

FIG. 2 shows an integrated circuit arrangement 100, in the manufacture of which the problems explained with reference to FIG. 1 no longer occur. The integrated circuit arrangement contains a pnp transistor 102 shown in the left part of FIG. 2 and an npn transistor 104 shown in the right teal of FIG. 2. Beαde transαstors 102 and 104 are vertical transistors in which the active emitter region, the base region and the active collector region are arranged vertically when the substrate surface carrying the transistor lies horizontally, ie the active regions are lined up in the normal direction of a main surface of the substrate, with a main surface including a surface a considerably larger surface area than, for example, an edge surface of the substrate. A vertical line 106 between the transistors 102 and 104 illustrates that the two transistors 102 and 104 can be arranged both next to one another and in circuit parts of the integrated circuit arrangement 100 that are spaced apart from one another. For example, several other components are located between the two transistors 102 and 104.

Starting from a substrate 108 with increasing distance from the substrate 108, the transistor 102 contains one another in the order specified: an n-doped well 110, a p-doped buried one

Collector supply layer 112,

an einkπstallinen p-doped collector region 114,

an emcrystalline n-doped base region 116, an emcrystalline p-doped emitter region 118

- A low-poly emitter connection region 120 made of silicon, and

a metallic emitter connection 124, for example made of tungsten.

On the emitter connection area there is an insulating cover layer 122, for example made of silicon dioxide, with a recess for the emitter connection.

An epitaxial layer 126 applied to the substrate 102 contains two isolation trenches 128, 130 that laterally isolate the transistor 102, and one isolation grille between them. ben 128 and 130 arranged isolation trench 132, which serves to isolate an n-doping region 134 for receiving the base region 116 and for connecting the base region 116 from a p-doping region 136 for connecting the buried p-collector lead 112. In this embodiment, the isolation trenches 128 to 132 extend into the collector lead 180. The epitaxial layer 126 has a thickness of 300 nm, for example. In another exemplary embodiment, the collector lead 112 of the pnp transistor 102 is arranged deeper in the substrate 108 than the collector lead 180 of the npn Transistor 104.

There is an insulating layer 140 on the insulating trenches 128 to 132, which has a thickness of 100 nm, for example, and consists of silicon oxide. The insulating layer 140 contains a recess 142 for receiving the polycrystalline emitter connection region 120 and a recess 144 for receiving a heavily p-doped polycrystalline collector connection region 146, which is also covered by the insulating cover layer 122. A metallic collector connection 148 leads to the collector connection region 146.

The insulating layer 140 also contains cutouts on both sides of the cutout 142 for metallic base connections 150, 152, which are connected to the n-doped doping region 134 via heavily n-doped connection regions 154 and 156.

In addition, spacers 160 to 164 are arranged on the side of the emitter connection region 120 and the collector connection region 146. The spacers 160 to 164, the base connections 150, 152, the emitter connection 124 and the collector connection 128 lie in an interlayer insulating layer 170, which consists for example of silicon dioxide. Further metallization layers for connecting transistor 102 are not shown in FIG. 2. There is still a heavily p-doped doping region 172 between the p-doping region 136 and the collector connection region 146. The doping region 172 is formed by diffusion of dopants from the collector connection region 146 into the epitaxial layer 126.

Starting from the same substrate 108, the npn transistor 104 contains an increasing distance from the substrate 108 in the order given: - an n-doped buried collector lead 180,

an low-crystal n-doped collector region 182,

an low-crystal p-doped base region 184,

an low-crystal, n-doped emitter region 186,

an n-doped, low-poly emitter connection region 188, and

a metallic emitter connection 190.

The transistor 104 contains two isolation trenches 192 and 194 which extend as far as the collector lead 180. Between the isolation trenches 192 and 194 there is an isolation trench 196 which isolates the collector region 182 from an n-doped doping region 198. The doping region 198 serves to connect the buried collector feed line 180.

The insulating layer 140 is also arranged on the insulating trench 192 to 196. The insulating layer 140 has a recess 200 in the region of the npn transistor 104, in which a layer is grown which is grown by selective epitaxy and which usually consists partly of silicon germanium and partly of silicon. For example. first the silicon germanium layer and then the silicon layer is produced. The recess 200 and thus the epitaxial layer contains the base region 184 and the emitter region 186.

In the insulating layer 140 there is also a recess 202 in the area of the npn transistor 104, the heavily doped polykπstallmer collector connection area 204 is arranged. The collector connection region 204 consists of n-doped polycrystalline silicon, the dopants of which have been partially diffused into the epitaxial layer 126 and form a doping region 206 there, which adjoins the doping region 198. The collector connection area 204 is connected via a metallic collector contact 208.

Overlapping the edge of the recess 200, two p-doped polycrystalline regions 210 and 212 made of polycrystalline silicon are also arranged on the insulating layer 140 in the region of the npn transistor 104. The low-poly regions 210 and 212 are covered by remaining regions of the cover layer 122. The polycrystalline region 212 is connected via a metallic base connection 230.

Spacers 220 to 226 are arranged on the side surfaces of the polycrystalline areas 210, 212 and the areas of the cover layer 122 on these polycrystalline areas. On the two mutually facing side surfaces, the spacers 222 and 224 adjoin the low-poly emitter connection region 188.

From the doped polycrystalline regions 210 and 212, dopants have penetrated into the silicon-germamum region arranged within the cutout 200 and form doping regions 232 and 234 there or continue forward.

FIG. 3 shows a manufacturing stage of the integrated circuit arrangement 100. Starting from the p-doped substrate 108, the n-doped buried collector lead 180 is first produced in the area of the npn transistor 104 by, for example, arsenic implantation and subsequent emdαffusαon. In the area of the pnp transistor, the well 110 was implanted, which serves to isolate transistor 102 from substrate 108.

The epitaxial layer 126 is then applied by full-surface epitaxy. Alternatively, the epitaxy can also be dispensed with if the regions 110 and 180 are implanted with higher energy. The isolation trenches 128 to 132 and 192 to 196 are then formed in the epitaxial layer 126 with the aid of a photolithographic process, for example with the aid of reactive ion etching. The isolation trenches 128 to 132 and 192 to 196 are then filled with silicon dioxide, which is then planarized. Alternatively, LOCOS technology (LOCal Oxidization of Silicon) can be used instead of the isolation trenches 128 to 132 or 192 to 196. When the isolation trenches 194 and 196 are created, the collector area 182 is defined.

In a subsequent implantation step using a photomask, not shown, the doping region 198 is doped. For example with the help of an implantation and a subsequent diffusion. This implantation is also referred to as npn collector deep implantation.

The buried collector lead 112, the n-doping region 134 and the connection regions 154 and 156 are then implanted with the aid of further additional masks. In addition, with the aid of an additional mask, the p-doping region 136 is generated, which is used to connect the collector region 114 of the pnp transistor.

After these implantation steps have been carried out, the insulating layer 140 is applied. A photoresist layer 250 is applied to the insulating layer 140. The photoresist layer 250 is selectively exposed and developed to determine the location of the cutouts 142, 146 and 202. The recesses 142, 146 and 202 are then inserted into the insulating Manhole 140 etched, beαspαelsweαse with the help of a reactive ion etching process or wet-chemical.

The collector region 114 can then be implanted without the use of an additional mask

Recess 142 is arranged. Alternatively, however, an additional mask can also be used for the implantation of the collector area 114, or the implantation of the collector area can take place earlier in the process, e.g. the photo technique can be used to implant the area 134.

As shown in FIG. 4, the residues of the photoresist layer 250 are subsequently removed. A p-doped polycrystalline silicon layer 260 is deposited or produced by undoped deposition and subsequent doping. The cover layer 122 is applied to the silicon layer 260, for example with the aid of a deposition process. A photoresist layer 270 is then applied and selectively exposed. The exposed photoresist layer 270 is developed in order to define the boundaries of the polycrystalline emitter connection region 120, the polycrystalline collector connection region 146, the polycrystalline region 210 and the polycrystalline region 212. The cover layer 122 and the polycrystalline silicon layer 260 are then patterned with the aid of the structured photoresist layer 270, the emitter connection region 120, the collector connection region 146, the polycrystalline region 210 and the polycrystalline region 212 being produced from the polycrystalline layer 260. For example, reactive ion etching is used. For all four areas mentioned, the insulating layer 140 serves as an etch stop layer. For this reason, a long overdraft does not attack the n-dotalber 134. In the npn transistor 104, the etching of the n-doping region 198 is not critical. As can be seen again from FIG. 2, the npn transistor 104 is then completed, but no further permanent layers are applied in the region of the vertical pnp transistor 102. The following sequence in particular is generated in the region of the npn transistor 104:

the recess 200 by wet-chemical etching of the insulating layer 140, the epitaxial layer 184, the spacers 220 to 226, the spacers 160 to 166 also being formed,

- The collector connection area 204 and the emitter connection area 188 made of an n-doped polyconductive silicon layer with the aid of a photolithographic method.

This is followed by an annealing to diffuse the dopants on the polykstallin silicon. The emitter region 118, the doping region 172, the doping region 206, the doping regions 232, 234 and the emitter region 186 are generated at the latest.

Subsequently, the intermediate layer insulating layer 170 is applied, planarized and structured with the aid of a further photolithographic method. The metallic contacts are inserted into the contact holes that are created. Subsequently, further metallization layers are created.

FIG. 5 shows an integrated circuit arrangement 1100, in the production of which the same method steps were carried out as in the production of the circuit arrangement 100. However, the pnp transistor 1102 corresponding to the pnp transistor 102 was implemented with two emitter regions 1118 and 1118b which are separated from one another. The transistor 1102 also contains two collector connection regions 1144 and 1144b. In FIG. 5, elements which have already been explained above are identified by the same reference numerals, which, however, are preceded by a "1". These elements will not be explained again. Elements in duplicate with the same structure as the elements already explained with reference to FIGS. 2 to 4 have the same reference numerals in FIG. 5, but with the prefix "1" and the lower case letter "b", for example the second emitter connection area 1120b additionally to the emitter connection 1120. The central base connection 1150 shown at Fagur 5 is optional. In addition, the variant explained above with reference to FIGS. 2 to 4 can also be implemented with a collector connection on both sides. In another exemplary embodiment, field-effect transistors are also integrated in the integrated circuit arrangement 100 to 1100 in addition to the two bipolar transistor types, so that, for example, a BiCMOS circuit arrangement (bipolar complementary metal oxide semiconductor) is produced.

In contrast to the methods used hitherto, no n-doped polycrystalline silicon, which in some cases runs above the p-polycrystalline silicon, is necessary in the methods according to the exemplary embodiments explained for the basic connection. Even if polycrystalline silicon is used for the base connection, there is an overlap of the polycrystalline silicon with the emitter connection region over a chip area which is already occupied by the overlap of the emitter connection region 120 over the insulating layer 140. However, the overlap of the emitter region over the insulating layer does not adversely affect the effective width of the emitter region 118, so that the emitter can be selected to be significantly narrower than before. This allows the electrical properties of the pnp transistor to be improved considerably. Also the multi-emitter configuration according to FIG. 5, which, for example, for a high current carrying capacity can be used per chip area, this makes it more attractive.

In summary, the integration of a vertical pnp transistor is a technology with npn transistors, in particular npn transistors with selective base epitaxy, in which the emitter of the vertical pnp transistor is given by eme - albeit with different opening dimensions. sung - opening required anyway, namely the recess 142, m is defined in an insulating layer 140 required anyway. The process steps for the production of the opening of the insulating layer 140 are also to be carried out in any case for the production of openings for contacting the substrate. It is also possible to produce a vertical pnp transistor with additional insertion of the isolating layer 140 and an additional etching for the cutout 142 if pnp transistors are to be produced without the simultaneous generation of npn transistors.

Claims

claims

1. Integrated circuit arrangement (100), with at least one npn transistor (104), which adjoins one another in the following sequence an n-doped emitter region (186), a p-doped base region (184) and an n-doped collector region ( 182), and with at least one pnp transistor (102), which contains a p-doped emitter region (118), an n-doped base region (116) and a p-doped collector region (114), and with the following sequence an electrically insulating insulating layer (140) which contains at least one recess (142) in the area of the pnp transistor (102), under which the base area (116) of the pnp transistor (102) is arranged and in which the electrically conductive material of an emitter connection area (120) is arranged, which is electrically conductively connected to the emitter region (118), and which contains a further recess (200) in the region of the npn transistor (104), that the base region (184) of the npn transistor (104), wherein the recess (142) limits the width of the electrical contact of the emitter connection region (120) to the emitter region (118) of the pnp transistor (102) and / or adjoins the emitter connection region (120), and wherein electrically conductive material of the emitter connection region (120) also overlaps the insulating layer (140) outside the recess (142) and / or adjoins the insulating layer.

2. Circuit arrangement (100) according to claim 1, characterized in that the recess (142) adjoins the emitter region (118) of the pnp transistor (102), and / or that the electrically conductive material of the emitter connection region (120) Fills recess (142) completely, and / or that the Isolαerschαcht (140) is a flat shaft, and / or that the emitter region (118) of the pnp transistor (102) is also arranged below the recess (142), and / or that the emitter region of the npn transistor (104) is also arranged in the further recess (200).

3. Circuit arrangement (100) according to claim 1 or 2, characterized in that in the further recess (200) a low-crystal layer is arranged which contains a different base material than the collector region (182) not arranged in the recess (200). of the npn transistor (104), the low-crystal layer preferably containing silicon germanium or silicon germanium carbon as the base material, and the collector region (182) of the npn transistor (104) preferably not arranged in the recess (200) preferably silicon included as base material.

4. Circuit arrangement (100) according to one of the preceding claims, characterized in that the electrically conductive material of the emitter connection region (120) is p-doped semiconductor material, preferably polycrystalline semiconductor material, in particular polycrystalline silicon, and that the base region (184 ) of the npn transistor (102) with p-doped semiconductor material, and / or that the collector region (114) of the pnp transistor (102) is connected with p-doped semiconductor material.

5. Circuit arrangement (100) according to one of the preceding claims, characterized geke nnz eichnet that spacer elements (160, 162) are arranged on the electrically conductive material of the emitter connection region (120) and adjacent to the insulating layer (140), which preferably with increasing Distance from the insulating layer (140) taper and which preferably contain electrically insulating material or consist of electrically insulating material.

6. Circuit arrangement (100) according to one of the preceding claims, characterized in that the base region (116) of the pnp transistor (102) is connected via an em-crystalline layer (134) which is located under the insulating layer (140 ) extends to at least one base connection recess in the insulating layer (140), and that the low-maintenance layer (134) in the region (154, 156) of the base connection recess is doped higher than in the base region (116), and that the base connection recess is electrically conductive material (150, 152) included.

7. Circuit arrangement (100) according to claim 6, characterized in that the base connection recess e contains metal (150, 152) or a metal connection.

8. The circuit arrangement (100) according to claim 6, characterized in that the base connection recess contains an n-doped semiconductor material, preferably a polycrystalline semiconductor material, in particular polycrystalline silicon, and that the collector region (182) or the emitter region (186 ) of the npn transistor (104) or both the collector region (182) and the emitter region (186) of the npn transistor (104) are also connected with an n-doped semiconductor material.

9. Circuit arrangement (100) according to any one of the preceding claims, characterized in that the

Collector region (114) of the pnp transistor (102) and / or the emitter region (118)) of the pnp transistor (102) has the same outline shape as the recess (142), and / or that the collector region (182) of the The npn transistor (104) and / or the emitter region (186) of the npn transistor (104) has the same outline shape as the further recess (200).

10. Circuit arrangement (1100) according to one of the preceding claims, characterized in that the pnp transistor (1102) is designed as a multi-emitter transistor which contains at least two cutouts (1142, 1142b) which are outside the respective cutout (1142, 1142b) of electrically conductive material of an emitter connection region (1120, 1120b) are overlapped, and / or that the pnp transistor (102) and / or the npn transistor (104) is a vertical transistor.

11. Circuit arrangement (100) according to one of the preceding claims, characterized in that the dopings are of the opposite doping type to the doping types mentioned above, and / or that the emitter region and collector region of a transistor are interchanged.

12. A method for producing an integrated circuit arrangement (100), in particular an integrated circuit arrangement (100) according to one of the preceding claims, which contains at least one npn transistor (104) which adjoins an n-doped emitter region in the following order 186), contains a p-doped base region (184) and an n-doped collector region (182), and which contains at least one pnp transistor (102), which adjoins one another in the following sequence a p-doped emitter region (118) contains n-doped base region (116) and a p-doped collector region (114), with the method steps carried out without restrictions by the predetermined sequence:

Applying an insulating layer (140) to a semicrystalline material (126), structures of the isolating layer (140) producing at least one recess (142) under which the base area (116) the pnp transistor (102) is arranged or is arranged,

Applying a connection layer (260) made of electrically conductive material or material which can be converted into such a material onto the structured insulating layer (140),

Structuring of the connection layer (260) with the creation of an emαtterschlußgebietα (120) for the emitter region (118) of the pnp transistor (102) m the recess (142) and overlapping to the insulating layer (140) outside the recess (142),

Generating the base region (184) of the npn transistor (104) in a recess in the insulating layer (140) after structuring the connection layer (260).

13. The method according to claim 12, g e k e n n z e i c hn e t d u r c h the steps:

Structuring of the connection layer (260) while simultaneously producing a preferably polyconductive base connection area (210, 212) for connecting the base area (184) of the npn transistor (104).

14. The method according to claim 12 or 13, characterized by the following steps: applying a further connection layer made of electrically conductive material or material convertible from such a material after the generation of the base region (184) of the npn transistor (104), structuring of the further ones Connection layer producing an emitter connection region (188) for the emitter region (186) of the npn transistor (104) or a collector connection region (204) for the collector (182) of the npn transistor (104) or producing both an emitter connection region (188 ) for the emitter region (186) of the npn transistor (104) and a collector connection region (204) for the collector (182) of the npn transistor (104), wherein at least one connection area for the base area (116) of the pnp transistor (102) is also generated or wherein the further connection layer areas of the pnp transistor (102) are completely removed.

15. The method according to any one of claims 12 to 14, characterized by the steps: generating connections (150, 152) from metal or metal-containing connections, at least one connection for connecting the base region (116) of the PNP Transistor (102) penetrates the insulating layer (140).