EP1614091A1

EP1614091A1 - Control system and control method for checking the function of liquid crystal displays

Info

Publication number: EP1614091A1
Application number: EP04723901A
Authority: EP
Inventors: Uwe Ruppender; Karl Miltner; Wolfgang Obermeier; Edgar Baumann; Hartmut Henkel
Original assignee: F Hoffmann La Roche AG; Roche Diagnostics GmbH
Current assignee: F Hoffmann La Roche AG; Roche Diagnostics GmbH
Priority date: 2003-04-12
Filing date: 2004-03-27
Publication date: 2006-01-11
Also published as: US20060279321A1; DE10316901A1; WO2004090852A1; CA2521737A1; JP2006526164A

Abstract

The invention relates to a method and a measuring system for checking the function of liquid crystal displays comprising individual display segments, on the basis of the difference in the electrical capacitance Cseg of defective and intact display segments. The invention is based on the fact that the capacitance of the display segments is directly determined by measuring the stored electrical charge using a capacitance measuring method. According to the preferred measuring method, a charge transfer is carried out by a reference capacitor Cref, and the segment capacitance Cseg is determined as a result of a charge balance, preferably by means of a DeltaSigma conversion.

Description

Control system and control method for checking the function of LCD displays

The invention relates to a method and a corresponding electronic measuring system for checking the function of LCD displays comprising individual display segments on the basis of the difference in the electrical capacity of defective and intact display segments, in particular in the case of medical measuring or diagnostic devices.

The correct functioning of the display is of great importance in many applications. In medical devices, e.g. Blood glucose meters, defects in the measured value display can lead to incorrect readings, which can lead to life-threatening misinformation by the user, for example due to a resulting incorrect dosage of a medication, and to life-threatening situations.

A first example of such a malfunction is the failure of the decimal point in a mmol / 1 display, for example due to a line fault or a defect in the display. A second example is the failure of two segments, through which a leading 4, for example when a glucose reading of 415 mg is displayed, becomes a leading 1 and the result is falsified to 115 mg. In particular in the case of battery-operated devices, liquid crystal displays (LCDs) have largely prevailed over other displays since they have a low power requirement, can be operated with low operating voltages, the electronic control is easy to implement, they have a high contrast and have a high level of sharpness, the shape of the display segments can be designed in almost any manner using simple lithographic processes, large-area segments or displays also being feasible, having a low overall depth and being easy to assemble. Such LCD displays comprise a plurality of individually activatable segments, one segment representing a character or symbol or part of a character or symbol.

In the case of LCDs, the alpha-numeric characters and symbols to be displayed are applied to a cover glass as transparent front electrodes and, together with back electrodes applied to a carrier glass and the liquid crystal layer defined by spacers as a dielectric, each form capacitive storage for electrical charges.

However, it is known that at. LCDs, segments or entire characters may fail, which results in the above risks. For this reason, when a device with an LCD display is switched on, the display is usually completely shown for a short period of typically 2 to 4 seconds, with all segments being activated. During this time, the user of the device can visually check whether all segments or signs and symbols are displayed. A first disadvantage, however, is that in practice, users often do not perform such a visual inspection. A second disadvantage is that with this method, the display can only be monitored at the time of switching on and the failure of one or more segments during operation remains unnoticed by the user.

To overcome these disadvantages, methods have been proposed in which the electrical capacity of the LCD segments serves as an auxiliary variable for checking the functionality. The check is based on the deviation of the capacity in the event of a malfunction, because the capacity of intact and non-intact display segments differs. The capacity is used to conclude that it is functioning correctly or that an error has occurred. Different measuring methods have been proposed which are based on the measurement of an electrical measured variable dependent on the capacity of the display segments, for example on the measurement of the time profile of the electrical voltage on the display segment or on the measurement of the level of the operating current.

In document WO 95/14238, the checking of the functionality of the LCD segments is based on their intrinsic capacity, which is measured. In the event of a deviation, an error is concluded. The LCDs are operated with AC voltage and the operating current is measured. A special feature of the function test is that the current is measured at different operating frequencies and it is checked whether predetermined range limits for the current are maintained within a certain frequency range. From this, different conclusions can be drawn about different error states and causes of errors. A disadvantage of this previously known method, however, is that no harmful parasitic coupling capacitances which distort the check are taken into account and that the method is only described for LCD displays, 5 which has separate segment and feedback electrodes for each LCD display segment.

A method is known from document EP 0 015 914 B1 in which the LCD display segments thereby

10 be monitored that the LCDs are driven with clocked voltage or AC voltage and the correct functioning of the segments is inferred from the temporal course of the voltage. The measuring method is based on the fact that there is a short circuit or a defective one

15th segment changes capacitance, resulting in a deviation in the rate of rise or fall of the voltage. However, the described method is only specified for LCD displays with a common back electrode and only for the detection of line interruptions.

20 gen and short circuits between segment and back electrode.

A method and a device for testing the LCDs of an LCD array are provided in document EP 0436777 A2

25 known the final assembly of the array. A charge is applied to an LCD capacitance and the remaining charge is measured after a certain period of time. The functionality is determined from the comparison of the applied and the remaining charge.

30 locks. A disadvantage of this prior art

The technology is that neither the function of the fully assembled LCD array nor its function can be checked during operation. Document US 5,539,326 describes a method for testing the connections of an LCD display before the final assembly. For this purpose, the LCDs are charged in several steps, once with and once without charging, the LCD cell capacity itself, and the difference in the charges, which are determined in the form of a current integrated over time, is used to determine whether the supply lines to the LCDs are fine. The LCDs themselves are not checked, and it is not possible to check them during operation.

Document US 5,428,300 describes a method and a device for testing TFT-LCDs, in which various charging and discharging processes take place and the function of the TFT-LCDs and their connection is determined on the basis of the waveform of the discharge currents.

All previously known methods have in common that they are based on an absolute measurement, with a test being carried out for compliance with certain limits of an absolute value of a capacitance. For this reason, the previously known methods have the disadvantage that they have a high sensitivity to temperature drifts and other drift processes and component scatter. This is particularly disadvantageous because the segments of LCD displays have only a very small capacity.

Furthermore, the previously known methods, in particular those which are based on the determination of charging time constants, often do not operate without DC voltage, require a variation in the measuring frequency and become increasingly non-linear with regard to capacity determination in the case of low capacitances. Taking this prior art into account, the invention is based on the object of providing a method and a corresponding electronic measuring system for checking the function of LCD displays, with which a reliable, user-independent, fully automatic check of the function is possible, the method with little Effort, for example using CMOS technology in an ASIC, should be realizable.

This object is achieved according to the invention by a method or a device with the features of the attached independent claims. Preferred refinements and developments of the invention result from the dependent patent claims and the following description with associated drawings.

A method according to the invention for checking the function of LCD displays comprising individual display segments on the basis of the difference in the electrical capacity of defective and intact display segments therefore has the special feature that instead of measuring an electrical measurement variable dependent on the capacity of the display segments and comparing the measured variable with a comparison value, the capacity of the display segments is determined directly by means of a capacity measurement method by measuring the electrical charge stored in the display segment.

Within the scope of the invention, it has surprisingly been found that the charge stored in LCD display segments can be measured, so that the capacity of the display segments can be determined directly with high resolution and accuracy. The direct determination of the capacity of LCD display segments according to the invention can take place in a variety of ways. According to a first advantageous feature, it is proposed that the capacitance of the display segments be determined by means of capacitively coupled charges, an electrical measuring current being capacitively coupled into an evaluation circuit via the capacitance of the display segment to be measured and the latter measuring the coupled charge. According to an additional advantageous feature, it can be provided that the measuring current is an alternating current and the charge coupled over per alternating voltage period is measured, which results in the capacitance of the display segment at a known frequency.

According to another preferred feature, it is proposed that the measurement of the capacitance of the display segments be carried out using a capacitance measurement method in which a charge transport controlled by a sequence control is carried out both by the capacitance to be measured in a display segment and by a reference capacitor and the capacitance of the display segment is determined on the basis of a charge balance between the display segment to be checked and the reference capacitor.

Such a relative measurement, which is based on the determination of a capacitance ratio, has the advantage of being insensitive to temperature and long-term drifts, for example the reference voltage sources, or the advantage of compensating for these drifts. In a preferred embodiment, to minimize measurement errors, it is provided that the reference capacitor is integrated in the LCD display, for example in the form of an LCD segment or a capacitor component. This has the advantage part of a further improved compensation for temperature drifts.

A preferred embodiment of a method according to the invention is that the capacity of the display segments is determined by means of a capacity measurement method that uses a ΔΣ conversion. Such a method is particularly suitable for measuring small capacities. In the case of LCD display segments, the capacitance is approximately 1 pF to 300 pF, so that the charges to be measured are in the range of pC and the measuring currents are in the range of pA and are therefore difficult to measure in terms of measurement technology.

A capacitance measurement method using a ΔΣ conversion can be set up with little expenditure on analog electronics with high measurement accuracy and insensitivity to parasitic stray capacitances, for example in the form of a first order ΔΣ converter, i.e. using an integrator.

The basic principles of ΔΣ-A / D converters and their implementation questions in connection with CMOS technology are known. The basic principle of such a converter is that charge packets are charged with a fixed frequency from the capacitor to be measured, in the present case an LCD segment, to an integrator. Since the capacitor to be measured is thereby always transferred from a known voltage to another known voltage, since the voltage difference which arises during the transfer at the capacitor to be measured is constant and known, the charge supplied to the integrator with each transfer is proportional to the capacitance. The output voltage of the integrator is proportional to the charge stored in the integration capacitor of the evaluation circuit and is constantly monitored in time with the charge packets supplied. If a given voltage value at the integrator output is exceeded, the integrator is charged in an opposite direction by known reference charge packets. This results in a closed control loop in which the charge in the integrator, ie on its integration capacitor, is kept constant in a long-term equilibrium. Therefore, it is often spoken of a "charge balancing" principle, synonymous with the term ΔΣ method.

The result of such a conversion is a 1-bit data stream, the mean single density of which is proportional to the capacity to be measured. This data stream is processed in a suitable manner in order to obtain a multi-bit result. For this purpose, digital filters, so-called decimation filters, are typically used. The theory of the ΔΣ converters states that a decimation filter of at least one order higher is generally required to evaluate the data stream of a "charge balancing" converter of the given order. In the preferred embodiment of a first-order ΔΣ converter, a second-order or higher-order decimation filter is thus used.

A control circuit for regulating the constant charge balance of the ΔΣ converter can be constructed from a few flip-flops and easily integrated into an ASIC. The structure of a second order decimation filter is also very regular and can easily be integrated into an ASIC. In other embodiments, the filter is also implemented in a microcontroller possible, for example in the microcontroller of the sequence control.

According to a further advantageous feature, it is proposed to use an automatic measuring point switch, with which display segments are individually controlled for the function test. The particular advantage of the measuring point switch, which selects individual segments, is that it can greatly reduce or almost eliminate the influence of parasitic capacitances and coupling capacitances, which usually falsify the measurement result.

In an advantageous embodiment it can be provided that a measuring voltage is applied by means of the measuring point switch to a first electrode of a display segment to be checked, the electrodes of other display segments corresponding to the first electrode are connected to ground in terms of AC voltage, and the coupled charge is applied to the second electrode of the display segment to be checked is measured, this point being AC in terms of virtual ground, and the electrodes of other display segments corresponding to the second electrode are AC in terms of ground.

It is particularly preferred if the first electrode is the front electrode and the second electrode is the rear electrode of the display segment to be tested.

The method according to the invention can advantageously also be used if the display segments are controlled in a matrix structure both for the ongoing operation of the LCD display and for the functional test in the multiplex method. According to a further advantageous feature, it is proposed that the control levels and the clock phases for the control of the display segments, in particular in a multiplex process, be selected such that the voltage level of the inactive display segments below the response threshold and the voltage level of the active display segments above the response threshold of Display segments lies, the capacitance measurement process is carried out with these voltage levels and the switching phases of the capacitance measurement process are synchronized with the clock phases of the LCD control.

For the operation of the LCD display segments, it is advantageous if, by means of a regular polarity reversal of the voltage level, the display segments are driven on average without DC voltage. In direct voltage operation or in the case of a direct voltage component there is a risk that electrolysis effects may occur due to leakage currents, through which the liquid crystals can be decomposed. It is also advantageous if the capacitance measurement method is carried out in such a way that the same effective value of the voltage of the display segment results as without capacitance measurement.

Furthermore, it is advantageously provided that the capacity of a display segment is measured during a clock phase of the control of the display segment, with several switching operations of the capacity measuring method being carried out in this clock phase.

According to a further advantageous feature, it is proposed that the LCD display for ongoing operation and / or for capacitance measurement with a low impedance is controlled to reduce the influence of coupling capacities.

A particular advantage of the method according to the invention can be that the capacitance of the display segments is determined as a digital measurement result by means of the capacitance measurement method and that the functionality of a display segment is checked using the digital measurement result.

Another advantageous feature of the method according to the invention is that it is possible to check the functionality of a display segment while the LCD display is in operation. In an advantageous embodiment of the method according to the invention it is provided that only activated display segments are functional be checked, since inactive display segments do not lead to a false display in the event of a malfunction. This makes it possible to accelerate the function test of the LCD display segments or to repeat them at a higher frequency.

According to an additional advantageous feature, it is provided that the sequence control for the capacitance measurement or the measuring point switch for the control of a display segment is modulated or synchronized with the driver circuit of the LCD display.

Another advantageous feature can be that one or more components of the LCD test device, including the sequence control for the capacitance measurement, the measuring point switch for the control of a display segment, the measuring circuit (analog switch, integration amplifier and comparator and possibly the Integration capacitor), the LCD driver / decoder circuit and the evaluation circuit (microcontroller) are housed in a single integrated component, such as an ASIC or a mixed signal FPGA. In a special embodiment, it can be provided that an LCD control circuit usually used for driving and decoding is equipped with the LCD test device according to the invention. A preferred embodiment provides that the ASIC is integrated in an LCD driver circuit.

The method according to the invention is suitable for any devices containing LCD displays, in particular for medical measuring or diagnostic devices.

The invention and its special configurations have a number of advantages. A digital measurement result is delivered so that a high accuracy and thus a reliable check is achieved. As a result, the criteria used in the functional test for proper functioning or for the presence of a malfunction can be selected in a very differentiated manner and evaluated in software. In the case of relative measurement, insensitivity to temperature and long-term drifts is achieved. Furthermore, series resistances, for example in the contacting, have no influence on the measurement result, provided the switching times are sufficiently long. The method according to the invention is suitable for any LCDs, ie not only for those with a common back electrode or with separate segment and back electrodes, but also for LCDs with segment electrodes in a matrix structure.

The method according to the invention can be calibrated in a simple manner, namely by software, automatic table and without circuit change or circuit adaptation. Calibration parameters can, for example, be determined automatically within an ASIC and saved in an EEPROM or Flash ROM. According to the prior art, however, the external wiring and test frequency must be matched to the type of LCD display.

Automatic calibration by means of a reference LCD of a reference LCD segment or a reference capacitor component or calibration capacitor is possible. A calibration capacitor is used to calibrate the entire measurement or measuring circuit. The charge balance compensation for the ΔΣ conversion is carried out via the reference capacitor. No calibration capacitor is required in the final version of the test device in one device.

Malfunctions of LCD display segments can be automatically recognized with the invention without the user having to check the display by eye. This enables a user-independent, fully automatic check of the LCD display and a high level of safety for the user.

The method according to the invention can be carried out very quickly. A typical LCD display can be fully checked in about 0.5 to 1 second, including multiple scans to increase confidence. It can work with a constant measuring frequency and the segment test can be carried out without DC voltage. Another advantage is that the circuit according to the invention can be implemented very inexpensively, in particular if it is integrated in the ASIC for controlling the LCD display. The invention makes it possible not only to test the quality and functionality of LCD displays in the course of production, for which technically complex methods are used according to the prior art, but also to carry out the functional test in an uncomplicated manner during the service life in the terminal.

The check of the LCD display cannot be visually recognized by the user of the device. The LCD display can be monitored at any time, e.g. constantly, when starting a measurement or when displaying a measurement result, and not only when the device is switched on.

When a display segment malfunctions, numerous device reactions are possible, for example generating a warning signal or preventing the device from functioning.

The invention is explained in more detail below on the basis of the exemplary embodiments illustrated in the figures. The special features described therein can be used individually or in combination with one another in order to create preferred embodiments of the invention. 1 shows a functional sketch of a first LCD display.

Test arrangement according to the state of the art,

2 is a functional sketch of a second LCD

Test arrangement according to the state of the art,

3 shows a schematic diagram of a ΔΣ conversion, FIG. 4 shows a schematic diagram of a preferred LCD capacitance measuring arrangement according to the invention with ΔΣ conversion,

5 shows the capacities of a matrix arrangement of LCD display segments in a 4x9 matrix, 6 shows the capacities of a matrix arrangement of LCD display segments in a 2x2 matrix,

7 shows the 2 × 2 LCD matrix from FIG. 6 in a two-pole representation, FIG. 8 shows the matrix from FIG. 7 with the elimination of the influence of parasitic capacitances during the functional test,

9 shows the display segments of the LCD matrix of FIG. 6,

10 LCD drive pulses for Fig. 9, Fig. 11 shows an LCD driver circuit for the multiplex operation of Fig. 6,

12 shows the LCD driver circuit from FIG. 11 with a ΔΣ conversion according to the invention for testing display segments, FIG. 13 shows a modified capacitance measuring circuit in the idle state,

14 shows the capacitance measuring circuit of FIG. 13 in the charging phase and comparison phase,

FIG. 15 shows the capacitance measuring circuit of FIG. 13 in the comparison phase without reference integration and

FIG. 16 shows the capacitance measuring circuit from FIG. 13 in the integration phase with reference integration.

1 shows a functional sketch of an electronic measuring system according to document WO 95/14238 for testing LCD displays. The circuit works with common driver ICs of the LCD control and comprises two switches SI and S2, an inverter 1 and a voltage source U. During a special test mode, the current flow through the LCD segment to be tested is illustrated by the capacitance Cseg is conducted via a shunt resistor RS. The chip Voltage drop across this shunt resistor RS is amplified by means of the amplifier V and temporarily stored in a sample-and-hold element (sample-and-hold stage S&H). A comparator Δ compares the output voltage of the sample-and-hold element with a reference voltage Uref and delivers the comparison result to the microprocessor μP, which switches the switches SI, S2 periodically. The microprocessor μP changes the keying frequency until there are pronounced signal changes (jitter) in the comparator signal. From the frequency at which this occurs, the capacitance Cseg of the tested display segment is then concluded.

This circuit has the disadvantages described above. Furthermore, the structure of the LCD driver IC is unknown and there is no information about the impedances at the individual LCD segments.

2 shows an LCD test circuit according to document EP 0 015 914 B1 for testing segment capacitances Cseg. In this case, series resistors Rv are switched into the leads of the LCD segments and an RC low-pass filter is formed in this way, to which a voltage is applied by means of an oscillator Os. If the LCD display functions correctly, the rise time of this low-pass filter must be greater than a reference value valid for the respective display type. The rise time is evaluated with the aid of the gate circuit Ts, the comparator Δ and the reference voltage source Uref. The output signal of the comparator Δ indicates whether the voltage across the segment capacitance has exceeded the value Uref. The gate circuit Ts measures the time required for this.

A disadvantage of this known circuit is that both the gate circuit Ts and the series resistor Rv would have to be matched to the segment capacities Cseg of the display type to be checked.

Fig. 3 shows a schematic diagram of a modern ΔΣ converter that works with multiple oversampling and a resolution of one bit. It consists of two blocks, namely an analog modulator and a digital filter. The modulator is in principle an analog comparator Δ, which is preceded by a low-pass filter as an integrator Σ. At the same time, the output signal Uin subtracts the output signal converted back by a 1-bit digital-to-analog converter DAW through the differential amplifier DV, so that the comparator Δ is reset each time. This creates a 1-bit data stream. If the amplitude of the analog signal increases, the "1" predominates at the output of the comparator Δ. If it falls, "0" predominates. If the amplitude is constant, "0" and "1" keep the balance.

The analog signal could now be recovered directly through integration or through a simple low pass. To achieve a better signal-to-noise ratio, noise shaping can be used, in which a noise spectrum is generated, for example by a noise source connected upstream of the integrator Σ. This is then downsampled by a steep-flanked digital filter FIR that forms an average.

4 shows a basic diagram of a preferred measuring arrangement according to the invention for determining the capacitance

Cseg of an LCD display segment based on a ΔΣ capacitance measurement method that is also referred to as ΔΣ conversion or ΔΣ conversion. In principle, this is a "charge pump". The segment capacity Cseg to be determined is together with a reference capacitor Cref with known capacitance integrated in a switch / capacitor structure according to FIG. 4. The measuring arrangement comprises switches Sa, Sb, Sc, Sd and a downstream integrator Σ with integration capacitor C5 and a downstream comparator Δ. The integration capacitor C5 should be chosen so large that the integrator Σ does not come within the limits given the maximum expected segment capacitance Cseg and the given charge-reversal voltage swing ± Uref.

The switches Sa to Sd are controlled by a sequence control, not shown here. With each switching operation, a quantity of charge corresponding to the capacity is transported and integrated by the downstream integrator Σ. The switches Sa-Sd are used by the

Sequence control is controlled so that a charge transport through the reference capacitor Cref causes a decrease, a charge transport through the segment capacitance Cseg to be determined causes an increase in the integrator voltage.

The charge balance of the integrator Σ is monitored with the aid of the downstream comparator Δ and can be kept constant by the sequential control system in that charge is either transported by both capacities or only by one of the two. From the ratio of the number of switching operations (or the added switching times) for the reference capacitor Cref and the segment capacitance Cseg, which results for a balanced charge balance, the ratio results directly as a digital result. The number of switching operations required for a given measurement accuracy is minimized by a digitally implemented decimation filter. Practical embodiments of LCD displays are usually controlled in a multiplex process in a matrix structure. FIG. 5 illustrates an electrical equivalent circuit diagram of an LCD with 9 segment electrodes and 4 back electrodes, that is to say with 36 segments in a 4x9 matrix structure, which are driven with four row signals COM1, COM2, COM3 and COM4 and nine column signals SEG1 to SEG9. Segment capacities and parasitic coupling capacities are shown.

However, not all possible coupling capacities can be shown in the drawing. The electrical equivalent circuit diagram of the LCD is based on a simplified model, which is based on the following assumptions:

1. The front and back electrodes are low-resistance in the frequency range under consideration. Their impedance is therefore neglected compared to the coupling effects of the LCD segments.

2. The electrical conductivity of the liquid crystals is negligible.

3. Only coupling capacitances between adjacent segment or back electrodes are taken into account. This assumption is a good approximation.

The capacities of the individual segments between the front and back electrodes are C11 ... C49. The coupling capacitances between the segment electrodes are CS12 ... CS89, and the coupling capacitances between the back electrodes are CC12 ... CC34. For the testing of a single segment, it should be possible to use the measuring method to measure the segment capacitances C11 ... C49 individually and without mutual influence or influence by the capacities CS12 ... CS89 or CC12 ... CC34.

By using a measuring point switch, it is possible to select individual segments for the functional test and to completely rule out the influence of parasitic coupling capacitances between the segments. As a result, the test method is suitable for practically all types of LCD displays, that is to say also for those whose segment electrodes are arranged in a matrix structure. The function of the measuring point switch is explained below using an LCD display with a 2x2 matrix.

FIG. 6 illustrates such a 2x2 matrix structure using the example of an LCD display with four display segments, the capacities of which are represented by C1, C12, C21 and C22. The segments are controlled by two row signals COM1, COM2 and two column signals SEG1, SEG2. The matrix also includes parasitic coupling capacitances Cc and Cs; So all (essential) coupling capacities are illustrated.

FIG. 7 shows a two-pole position of the 2 × 2 LCD matrix corresponding to FIG. 6. As an example, the capacitance of the segment C1 should be measured, ie the ΔΣ converter is connected between the lines SEG1 and C0M1. The current Iv designates the current flowing into the integrator, ie into the virtual ground. It can be seen from the two-pole representation of FIG. 7 that not only the capacitance C1 to be measured makes a contribution to the current Iv, but also the bridge circuit formed by the other capacitances shown in the circuit. This would falsify the measurement result. The problem can be solved by using a measuring point switch which, as shown in FIG. 8, connects the other lines of the matrix, in this example the lines SEG2 and COM2, to ground. As a result, the parasitic current flows to ground and makes no contribution to the current Iv or to the measurement result. A corresponding procedure is also possible with larger matrices, for example with the matrix shown in FIG. 5.

The LCD shown in FIG. 5 consists of a matrix of many capacitors coupled together. For example, if you want to measure the capacitance of the segment C35 at the electrodes COM3 and SEG5, you measure not only the capacitance C35 alone, but also the other LCD capacitances due to the connections. This falsifies the measurement. By means of a measuring point switch, however, it is possible to use the matrix to determine a certain capacitance, e.g. C35, to be measured in isolation by the measuring point switch ensuring that currents flowing through a capacitor other than the one to be measured do not contribute to the capacitance measurement.

An isolated measurement of a segment, in particular by means of the capacitive coupling of charges, at the crossing point of a certain front and back electrode can be achieved in particular if the following conditions are met by means of the measuring point switch:

1. An AC voltage is applied to the front electrode leading to the segment to be measured. 2. The other front electrodes are connected to ground in terms of AC voltage.

3. The overcoupled charge is measured on the back electrode, which leads from the segment to be measured, this point being at virtual ground in terms of AC voltage.

4. All other back electrodes are connected to ground in terms of AC voltage.

The front and back electrodes can also be interchanged. However, it is electrically more advantageous to arrange as few circuit components as possible on the side on which the charge is removed.

For example, if the segment capacitance C35 is to be measured in FIG. 5, the AC voltage is applied at SEG5. The connections SEG1 to SEG4 and SEG6 to SEG9 are grounded. As a result, the influences of all parasitic capacitances between adjacent segment electrodes CS12 ... CS89 as well as between non-directly adjacent segment electrodes are eliminated. These capacities have the effect that the applied AC voltage is loaded somewhat more; however, the fault current flows to ground. The current flow into the virtual ground is measured at the electrode COM3 and the capacitance C35 is determined from this. The electrodes C0M1, COM2 and COM4 are grounded so that no cross currents can flow in the coupling capacitances between the back electrodes CC12 ... CC34. Therefore CC12 ... CC34 have no influence on the measurement. All other segment capacitances C11 ... C49, with the exception of C35, do not influence the measurement, because the described circuitry with the measuring point switch means that all segment capacitances, with the exception of C15, C25, C35 and C45, lie on both sides on ground or on virtual ground, so that no electricity flows. The currents flowing through C15, C25 and C45 flow to ground and are therefore not included in the capacitance measurement. Overall, the described wiring of the LCD with a measuring point switch thus enables the measurement of individual LCD segments in the matrix.

Such a measuring point switch advantageously consists of digitally controlled analog multiplexers in mixed CMOS Schottky diode switch technology. If a short distance to the measured LCD is maintained, they have only a negligible own parasitic capacitance. In the case of FIG. 6, a measuring point switch has, for example, nine positions for the coupling of the stimulus and five positions for the charge measurement, four of them for the connections COM1 to COM4, and one position for the connection of the calibration or reference capacitor, which is always on its other connection is fed by the stimulus.

The influence of coupling capacitances in the case of LCDs controlled in the multiplex method can also be counteracted in that the control takes place with a low output impedance.

In order not to have to switch off the LCD display during the function test, it is possible to integrate the function of the measuring point switch into the LCD driver circuit, which is preferably implemented by an ASIC, in such a way that the function test of the LCD display segments takes place while the display is running. This is fundamentally based on the fact that there are certain degrees of freedom in the sequence of the switch operations of the ΔΣ conversion and the measuring point switch as well as in the selection of the charge voltage values, which make it possible to synchronize the switching processes with the LCD driver clock. This makes it possible to carry out the functional test of the LCD display segments during the current display operation without the display being disturbed, impaired or interrupted. This is explained in more detail below.

LCD displays, whose segment and back electrodes are arranged in matrix form, are activated in time-division multiplex operation, since a simultaneous selection of all segments is not possible. The matrix structure means that inactive segments cannot be driven completely free of voltage. This is illustrated in Figures 9 and 10.

FIG. 9 shows four LCD display segments 2, 3, 4 and 5, which are designed, for example, as a square arrangement of square display segments in each case. Segment 2 is activated (black), ie it shows a black square, and segments 3, 4 and 5 are not activated (white). The display segments 2, 3, 4, 5 are controlled electrically in a matrix form corresponding to FIG. 6.

It can be seen from FIGS. 6 and 7 that even with a variation in the voltage level at COM2 or SEG2 there is always a current flow through one of the capacitors C12, C21 or C22. In practice, this problem is solved by correspondingly controlling the drive voltage levels and clock phases, so that the voltage level on inactive segments below the response threshold and Voltage level on active segments is above the point of contact of the liquid crystals. Such a common multiplex control by means of a conventional LCD driver IC is shown in FIG. 10 for the LCD display in FIG. 9.

As shown in FIG. 10, there are ternary signals at the COM electrodes, each of which can have the voltage values 0, 0, 5Ur or Ur. Binary signals are present at the SEG electrodes, which are the two voltage values XUr or

(lX) Can take Ur. The coefficient X, with 0 <X _< 0.5, is chosen so that the voltage level required for the activation of an LCD segment is only at the maximum resulting voltage swing, ie with the two level combinations Ur, (1 - X) Ur or 0, XUr. By regular polarity reversal, shown in Fig. 10 by the vertical dashed line, an average DC-free control is achieved. An LCD driver circuit that meets these requirements is shown schematically in FIG.

A used for the functional test of the LCD display segments ΔΣ converter can be designed so that it works with the voltage levels required for the multiplex operation and its switching phases with the clock phases of the

LCD control are synchronized. An average DC voltage-free control of the LCD segments can also be implemented here.

The control frequency of an LCD display is usually between 30 and 100 Hz. The measurement frequency of a capacitance measurement method according to the invention, for example a ΔΣ converter, is preferably greater than 2 kHz, preferably greater than 5 kHz and particularly preferably greater than 10 kHz. As a result, the switching operations accommodate the ΔΣ converter in sufficient numbers in the LCD control clock phases of the LCD control so that a capacitance measurement and consequently a functional test can be carried out while the display is running. The functional test should advantageously be carried out in such a way that the same RMS values of the LCD segment voltages are set as without a functional test, so that the display with the ongoing functional test does not differ from the display without a functional test.

A corresponding LCD driver circuit with an integrated ΔΣ converter is shown in FIG. The voltages at the COM connections are constantly scanned with the measuring clock of the ΔΣ converter. The voltage U0 is then to be selected so that an effective value of the segment voltage corresponding to Ur is established. According to the example from FIGS. 9 and 10, the voltage Ur, like the coefficient X introduced there, is dependent on the LCD response threshold. The additional modulation of the LCD drive voltage with the measuring cycle leads to a reduction in the effective value of the drive level which is decisive for the LCD activation. Therefore, depending on the pulse / pause ratio of the measuring cycle, the voltage U0 must always be selected to be greater than the voltage Ur. In the circuit shown in FIG. 12, a capacitance measurement is only carried out when UCOM = U0 in order to avoid the circuit complexity.

A complete switch cycle in the circuit according to FIG. 12 consists of three successive main phases, namely a charging phase, a comparison phase and an integration phase. There is also a rest phase in which all MOS switches are open. For each complete switch cycle there is an intermediate result single bit. A complete capacitance measurement on an LCD display segment requires a large number of such switch cycles. The capacity is calculated from the sequence of individual bits (the intermediate results) per switch cycle. The states of the switches S1-S11 in FIG. 12 that apply to the various operating phases are given in the table below.

In the table means:

0 = switch open

1 = switch closed

Phase 1 = segment active, polarity +, charging phase Phase 2 = segment active, polarity +, integration without reference integration

Phase 3 = segment active, polarity +, integration with

Reference integration phase 4 = segment active, polarity -, no measurement phase 5 = segment inactive, polarity +, no measurement phase 6 = segment inactive, polarity -, no measurement

The order of the switch phases can also be modified. However, it should be noted that all phases are long enough to charge the capacitors Cseg and Cref, and that the integrator Σ has enough time to settle. The duration of the individual switching phases should also take into account the respective series resistance in the transfer circuits. Although these series resistors have no direct influence on the measurement result, they can falsify the result if the switching phases are too short for sufficient charge equalization. The MOS switches should be controlled in a suitable manner in order to exclude cross currents through switches that are still closed or already closed. For this purpose, the "break-before-make" concept is available, for example, or additional phases of shifted control signals can be used.

At the beginning of the integration phase, starting from the state "all switches open", the integrator Σ should first be connected to the non-driven connections of Cseg and Cref and only then should the transhipment take place, i.e. switches S shown to the right of Cseg and Cref should close before the switches shown to the left. If this is not adhered to, there is a risk of partial discharge via parasitic diodes in the MOS structure, which leads to measurement errors and, in the case of large pulse currents, to a latch-up, which can result in a functional failure or destruction of the ASIC.

The measurement accuracy can be improved if MOS switches and operational amplifiers are used which have no input protection diodes. If the integrator settles too slowly, part of the charge could otherwise be diverted through these diodes in the first moment of the integration phase, which results in a measurement error. The reference capacitor Cref should generally be larger than the largest expected segment capacitance Cseg, since otherwise the "charge balancing" will not proceed correctly. By modifying the switch cycles, a smaller reference capacitor Cref can also be used.

The digital ΔΣ converter result is used for the functional test of the LCD display segment. Numerous function test criteria can be implemented, e.g. the ratio of segment capacities to one another or compliance with absolute limits of capacity values.

FIG. 13 shows a block diagram of a capacitance measuring circuit in principle corresponding to FIGS. 4 and 12, but somewhat modified in detail in the idle state, i.e. for control signals switch S with logic 0. The measuring point switch is not shown, and it is assumed in the circuit situation that a certain LCD display segment 2 is controlled by the measuring point switch to measure its segment capacity Cseg. This segment capacitance Cseg is shown between the signal lines CCOM and CSEG.

FIG. 12 shows an LCD driver circuit which, on the one hand, supplies the voltage level required for correct LCD display operation, and on the other hand allows a capacitance measurement for active LCD segments in accordance with the ΔΣ method described, voltage level and clock signals being controlled in such a way that display and capacitance measurement are carried out simultaneously can be carried out. Figure 13 relates to a capacitance measuring circuit used therein. The capacitance measurement takes place according to FIG. 13 by a ΔΣ conversion with the reference capacitor Cref. The capacitors Cseg and Cref are each interconnected with a full bridge of four MOS switches S each, the switches being controlled by the sequence controller 6 using logic signals LOADR, LOADX, INTR and INTX. This makes it possible to charge the capacitances Cseg and Cref separately, or to charge them in a controlled manner via the inverting integrator Δ, comprising a MOS operational amplifier and the integration capacitor C5.

The output voltage of the integrator Σ is compared with the voltage XUr by means of the comparator Δ, the comparator Δ providing the logic signal COMP. This is logic 1 if the integration voltage supplied by the integrator Σ is greater than XUr. The downstream sequence controller 6, which is integrated, for example, in an ASIC or is implemented in software by means of a microcontroller, controls the switches S via the logic signals LOADR, LOADX, INTR and INTX. The resulting 1-bit data stream 7 and the decimation filter are also shown 8th.

FIG. 14 shows the capacitance measuring circuit of FIG. 13 in the charging phase, in which the capacitors Cseg and Cref are charged, and in the subsequent short comparison phase, in which the output COMP of the comparator Δ is sampled and checked whether the integrator voltage is greater or has become smaller. If COMP is logic 0, this is followed by an integration phase without reference integration, if COMP is logic 1, this is followed by an integration phase with reference integration.

The integration phase without reference integration is shown in FIG. 15 and the integration phase with reference limit integration in Fig. 16. The segment capacity Cseg sought can be determined from the charge balance.

LIST OF REFERENCE NUMBERS

1 inverter

2 display segments

3 display segment

4 display segment 5 display segment

6 sequence control

7 1-bit data stream

8 decimation filter Cc coupling capacity Cmn display segment

C11 ... C49 segment capacities

COM line signal

COMP logic signal

Cref reference capacitor C5 integration capacitor

Cs coupling capacity

Cseg segment capacity

DAW digital to analog converter

DV differential amplifier FIR digital filter

Iv integrator current

LOADR logic signal

LOADX logic signal

INTR logic signal INTX logic signal

Os oscillator μP microprocessor

RS shunt resistor

Rv series resistor S&H sample / hold element SEG column signal

S switch

Ts gate circuit

U voltage source U0 voltage level for combined LCD multiplex and measurement operation

Ur voltage level for LCD multiplex operation

Uin input voltage

Uref reference voltage V amplifier

Δ comparator

Σ Integrator (low pass)

X factor

Claims

claims

1. A method for checking the function of individual display segments (2, 3) comprising LCD displays based on the difference in the electrical capacity of defective and intact display segments, characterized in that instead of measuring an electrical measurement variable dependent on the capacity of the display segments and a comparison the measured measured variable with a comparison value, the capacity (Cseg) of the display segments is determined directly using a capacitance measurement method by measuring the electrical charge stored in the display segment (2, 3).

2. The method according to claim 1, characterized in that the capacitance of the display segments (2, 3) is determined by means of capacitively coupled charges, an electrical measuring current being capacitively coupled via the capacitance (Cseg) of the display segment to be measured into an evaluation circuit and this coupled charge measures.

3. The method according to claim 2, characterized in that the measuring current is an alternating current and the charge coupled over per alternating voltage period is measured, which results in the capacitance of the display segment (2, 3) at a known frequency.

4. The method according to claim 1 or 2, characterized in that the measurement of the capacity of the display segments is carried out with a capacity measurement method, in which a charge transport controlled by means of a sequence control (6) takes place both through the capacitance to be measured of a display segment (2, 3) and through a reference capacitor (Cref) and the capacitance of the display segment (2, 3) on the basis of a

Charge balance between the display segment to be checked (2, 3) and the reference capacitor (Cref) is determined.

5. The method according to claim 4, characterized in that the reference capacitor (Cref) is integrated in the LCD display.

6. The method according to any one of the preceding claims, in particular according to claim 4, characterized in that the capacity of the display segments (2, 3) is determined by means of a capacitance measurement method that uses a ΔΣ conversion.

7. The method according to any one of the preceding claims, characterized in that an automatic measuring point switch is used with the display segments (2, 3) are individually controlled for the functional test.

8. The method according to claim 7, characterized in that a measuring voltage is applied by means of the measuring point switch to a first electrode of a display segment to be checked (2), the electrodes corresponding to the first electrode of other display segments (3) are connected to ground in terms of AC voltage the overcoupled charge is measured in the second electrode of the display segment (2) to be checked, this point lying on virtual ground in terms of AC voltage, and that of the second electrode trode corresponding electrodes of other display segments (3) are connected to ground in terms of AC voltage.

9. The method according to claim 8, characterized in that the first electrode is the front electrode and the second electrode is the rear electrode of the display segment to be tested (2).

10. The method according to any one of the preceding claims, characterized in that the display segments (2, 3) are controlled in a matrix structure both for the ongoing operation of the LCD display and for the functional test in the multiplex method.

11. The method according to any one of the preceding claims, in particular according to claim 10, characterized in that the control level and the clock phases for the control of the display segments, in particular in a multiplex method, are selected so that the voltage level of the inactive display segments (3) below the response threshold and the voltage level of the active display segments (2) are above the response threshold of the display segments (2, 3), the capacitance measurement process is carried out with these voltage levels and the switching phases of the capacitance measurement process are synchronized with the clock phases of the LCD control.

12. The method according to claim 10 or 11, characterized in that by means of a regular polarity reversal of the voltage level an average DC-free control of the display segments (2, 3) success.

13. The method according to any one of the preceding claims, characterized in that the capacitance measuring method is carried out so that the same effective value of the voltage of the display segment (2, 3) results as without capacitance measurement.

14. The method according to any one of claims 10 to 13, characterized in that the capacity of a display segment (2, 3) is measured during a clock phase of the control of the display segment (2, 3), with several switching operations of the capacitance measuring method being carried out in this clock phase.

15. The method according to any one of the preceding claims, in particular according to claim 10, characterized in that the LCD display is driven for ongoing operation and / or for capacitance measurement with a low impedance in order to reduce the influence of coupling capacitances.

16. The method according to any one of the preceding claims, characterized in that the capacity of the display segments (2, 3) is determined as a digital measurement result by means of the capacitance measurement method and the functionality of a display segment (2, 3) is checked by means of the digital measurement result.

17. The method according to any one of the preceding claims, characterized in that the checking of the functionality of a display segment (2, 3) takes place during the ongoing operation of the LCD display.

18. The method according to any one of the preceding claims, characterized in that only activated display segments (2) are checked for functionality.

19. The method according to any one of claims 4 to 18, in particular according to claim 17, characterized in that the sequence control (6) for the capacitance measurement or the measuring point switch for the control of a display segment (2, 3) modulates with the driver circuit of the LCD display or synchronized.

20. The method according to any one of claims 4 to 19, characterized in that one or more of the following components in a single integrated component, e.g. an ASIC or a mixed signal FPGA, the sequence control (6) for the

Capacity measurement, the measuring point switch for the control of a display segment (2, 3), the measuring circuit, the LCD driver / decoder circuit and the evaluation circuit.

21. The method according to claim 20, characterized in that an LCD control circuit usually used for driving and decoding is equipped with an LCD test device according to the invention.

22. The method according to any one of the preceding claims, characterized in that it is carried out on an LCD display installed in a device, in particular a medical measuring or diagnostic device.

23. Electronic measuring system for checking the function of individual display segments (2, 3) comprising LCD displays based on the difference in the electrical capacitance of defective and intact display segments, comprising a capacitance measuring device by means of which Instead of measuring an electrical measured variable dependent on the capacitance of the display segments and comparing the measured measured variable with a comparison value, the capacitance (Cseg) of the display segments can be determined directly using a capacitance measurement method by measuring the electrical charge stored in the display segment (2, 3) is.

24. Measuring system according to claim 23, characterized in that it comprises an electronic circuit for determining the capacitance of the display segments (2, 3) by means of capacitively coupled charges, an electrical measuring current capacitively via the capacitance (Cseg) of the display segment to be measured in an evaluation circuit is coupled and this measures the coupled charge.

25. Measuring system according to claim 24, characterized in that the measuring current is an alternating current and the charge coupled over per alternating voltage period is measured, which results in the capacitance of the display segment (2, 3) at a known frequency.

26. Measuring system according to claim 23 or 24, characterized in that it is an electronic circuit for

Measuring the capacitance of the display segments with a capacitance measuring method, in which a charge transport controlled by a sequence control (6) takes place both through the capacitance to be measured of a display segment (2, 3) and through a reference capacitor (Cref) and the capacitance of the display segment (2 , 3) is determined on the basis of a charge balance between the display segment to be checked and the reference capacitor (Cref).

27. Measuring system according to claim 26, characterized in that the reference capacitor (Cref) is integrated in the LCD display.

28. Measuring system according to one of claims 23 to 27, characterized in that it comprises an electronic circuit for determining the capacity of the display segments (2, 3) by means of a ΔΣ conversion.

29. Measuring system according to one of the preceding claims, characterized in that it comprises an automatic measuring point switch with which the display segments (2, 3) can be controlled individually for the functional test.

30. Measuring system according to claim 29, characterized in that the measuring point switch is designed so that a measuring voltage is applied to a first electrode of a display segment to be checked (2), the electrodes of other display segments (3) corresponding to the first electrode are connected to ground in terms of AC voltage , the overcoupled charge is measured on the second electrode of the display segment (2) to be checked, this point being on virtual ground in terms of AC voltage, and the electrodes of other display segments (3) corresponding to the second electrode are connected to ground in terms of AC voltage.

31. Measuring system according to claim 30, characterized in that the first electrode is the front electrode and the second electrode is the rear electrode of the display segment to be tested (2).

32. Measuring system according to one of the preceding claims, characterized in that the display segments (2, 3) are controlled in a matrix structure both for the ongoing operation of the LCD display and for the functional test in the multiplex method.

33. Measuring system according to one of the preceding claims, in particular according to claim 32, characterized in that the control levels and the clock phases for the control of the display segments, in particular in a multiplex method, are selected such that the voltage level of the inactive display segments (3) below the response threshold and the voltage level of the active display segments (2) is above the response threshold of the display segments (2, 3), the capacitance measurement process is carried out with these voltage levels and the switching phases of the capacitance measurement process are synchronized with the clock phases of the LCD control.

34. Measuring system according to claim 32 or 33, characterized in that by means of a regular polarity reversal of the voltage level, the display segments (2, 3) are driven on average without DC voltage.

35. Measuring system according to one of the preceding claims, characterized in that the capacitance measuring method is carried out in such a way that the same effective value of the voltage of the display segment (2, 3) results as without capacitance measurement.

36. Measuring system according to one of claims 32 to 35, characterized in that the capacitance measuring method during a clock phase of the control of the display segment elements (2, 3) is carried out, with several switching operations of the capacitance measuring method being carried out in this clock phase.

37. Measuring system according to one of the preceding claims, in particular according to claim 32, characterized in that the LCD display is driven for ongoing operation and / or for capacitance measurement with a low impedance in order to reduce the influence of coupling capacitances.

38. Measuring system according to one of the preceding claims, characterized in that the capacity of the display segments (2, 3) is determined as a digital measurement result by means of the capacitance measurement method and the functionality of a display segment (2, 3) is checked by means of the digital measurement result.

39. Measuring system according to one of the preceding claims, characterized in that the functionality of a display segment is checked during the ongoing operation of the LCD display.

40. Measuring system according to one of the preceding claims, characterized in that only activated display segments (2, 3) are checked for their functionality.

41. Measuring system according to one of claims 26 to 40, in particular according to claim 39, characterized in that the sequence control for the capacitance measurement or the measuring point switch for the control of a display segment (2) modulates or synchronizes with the driver circuit of the LCD display is.

42. Measuring system according to one of claims 26 to 41, characterized in that one or more of the following components in a single integrated component, e.g. an ASIC or a mixed signal FPGA, are housed: the sequence control (6) for the capacitance measurement, the measuring point switch for the control of a display segment (2, 3), the measuring circuit, the LCD driver / decoder circuit and the evaluation circuit.

43. Measuring system according to claim 42, characterized in that it comprises an LCD drive circuit usually used for driving and decoding, which is equipped with an LCD test device according to the invention.

44. Measuring system according to one of the preceding claims, characterized in that it is integrated in a device with a built-in LCD display, in particular in a medical measuring or diagnostic device.

45. Medical measuring or diagnostic device, comprising a measuring system according to one of the preceding claims.