EP1605431A1 - Aktivmatrix-Anzeigevorrichtung mit verringerter Anzahl von Electroden - Google Patents

Aktivmatrix-Anzeigevorrichtung mit verringerter Anzahl von Electroden Download PDF

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Publication number
EP1605431A1
EP1605431A1 EP04300319A EP04300319A EP1605431A1 EP 1605431 A1 EP1605431 A1 EP 1605431A1 EP 04300319 A EP04300319 A EP 04300319A EP 04300319 A EP04300319 A EP 04300319A EP 1605431 A1 EP1605431 A1 EP 1605431A1
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EP
European Patent Office
Prior art keywords
scan
lines
data
active
slk
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EP04300319A
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English (en)
French (fr)
Inventor
Yoshiharu Chikazawa
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Thomson Licensing SAS
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Thomson Licensing SAS
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Priority to EP04300319A priority Critical patent/EP1605431A1/de
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0857—Static memory circuit, e.g. flip-flop
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant

Definitions

  • the present invention generally relates to display devices, and particularly relates to an active matrix display device.
  • LED displays are widely used in many electrical devices.
  • LED (light emitting diode) displays are considered to be the technology that replaces the LCD technology as a next generation of the flat panel display.
  • LED displays are brighter and thinner, and offer faster response time, lighter weight, and more power efficiency.
  • OLED organic LED display
  • inorganic LED display There are two types of LED displays, i.e., an organic LED display (OLED) and an inorganic LED display.
  • the inorganic LED display uses an inorganic metal such as gallium arsenide, gallium nitride, etc., as a light emitting material, whereas the OLED display is based on an organic (i.e., carbon-based) material.
  • an organic (i.e., carbon-based) material i.e., carbon-based
  • An OLED is comprised of an organic light emitting material sandwiched between a metallic electrode and a transparent electrode. When a voltage is applied between the electrodes, positive holes and electrons are injected from the electrodes, and are recombined in the organic material to create electro luminescent light.
  • the OLED may be implemented as a passive matrix or an active matrix.
  • picture elements pixels
  • an electrical signal is applied to a particular column while rows are scanned line by line, thereby illuminating a particular pixel at the intersection of the selected column and the selected row.
  • each pixel is provided with a TFT (thin film transistor), which works as a switch and stores information as to an on/off state of each pixel (or how bright each pixel should shine).
  • TFT thin film transistor
  • the information is conveyed through column lines while rows are scanned line by line, resulting in each pixel storing the information in the TFT.
  • the OLED of each pixel shines all the time while a driving voltage is applied, thereby eliminating a need for an instantaneous, large electric current flow ing through an OLED as opposed to the necessity of such current in the passive matrix. This contributes to the increased durability of OLED materials.
  • each pixel needs to have four electrodes, i.e., two power-supply electrodes (i.e., for providing a power-supply potential and a ground potential) that sandwich an organic light emitting material, a scan electrode for scanning each row, and a data electrode serving as a column line to provide data to be stored in each pixel.
  • These electrodes extend in the row direction or the column direction throughout the active-matrix OLED panel.
  • these electrodes may need to be implemented by use of transparent electrodes such as ITO (Indium Tin Oxide).
  • transparent electrodes such as ITO (Indium Tin Oxide).
  • ITO Indium Tin Oxide
  • Such transparent electrodes have a drawback, however, in that conductivity is not as high as conventional metal electrodes.
  • These transparent electrodes thus need to be wider and thicker, which may undermine the optical characteristics of OLED displays.
  • the transparent electrodes can be widened without compromising the optical characteristics of the display.
  • metal electrodes made of Al, Cu, Ag, or the like may become usable without obstructing emitted light.
  • the invention provides an active-matrix display device in which a plurality of pixel circuits (P11-Pnm) are arranged in a matrix and positioned at intersections of data lines (DL1-DLm) and scan lines (SL1-SLn) extending in respective directions perpendicular to each other, and at least one (Pkl) of said pixel circuits is selected by one (SLk+1) of the scan lines to store data provided by one of the data lines, and is powered by two lines that provide a power-supply potential and a ground potential, respectively, characterized in that one of said two lines is another one (SLk) of the scan lines.
  • any one (Pkl) of the pixel circuits may be selected by one (SLk+1) of the scan lines to store data provided by one of the data lines, and is powered by two lines that provide a power-supply potential and a ground potential, respectively, one of said two lines being another one (SLk) of the scan lines.
  • each of the scan lines has dual functions so as to serve both as a power-supply or ground electrode and as a scan electrode.
  • This provision makes it possible to provide each pixel circuit with a power-supply potential, a ground potential, a scan electrode, and a data electrode, with only three types (or three networks) of lines laid out through the active-matrix structure.
  • Fig. 1 is a block diagram showing an example of the construction of an active-matrix display device according to the invention.
  • An active-matrix display device 10 of Fig. 1 includes an image data extractor 11, a synchronizing signal converter 12, a synchronizing signal generator 13, a pixel circuit driving power unit 14, an image data memory 15, a data driver 16, a scan driver 17, a display panel 18, and switches SW1 and SW2.
  • the display panel 18 includes pixel circuits P11 through Pnm, scan-power lines SL1 through SLn, and data lines DL1 through DLm.
  • n and m are integers, and represent the total number of scan lines (i.e., the number of rows) and the total number of data lines (i.e., the number of columns), respectively.
  • P11, P12, and P21 are shown for the pixel circuits, only SL1 and SL2 for the scan-power lines, and only DL1 and DL2 for the data lines.
  • the image data extractor 11 and the synchronizing signal converter 12 receive image signals.
  • the image data extractor 11 extracts image data from the received image signals.
  • the synchronizing signal converter 12 extracts synchronizing signals such as a vertical synchronizing signal and a horizontal synchronizing signal from the received image signals.
  • the switch SW1 couples the image data extractor 11 to the data driver 16
  • the image data extracted by the image data extractor 11 is supplied to the data driver 16.
  • the switch SW2 couples the synchronizing signals generated by the synchronizing signal converter 12 to the data driver 16 and to the scan driver 17.
  • the data driver 16 operates in synchronization with the supplied synchronizing signals to provide pulses to the data lines DL1 through DLm in accordance with the image data supplied from the image data extractor 11.
  • the scan driver 17 operates in synchronization with the supplied synchronizing signals to scan and drive the scan-power lines SL1 through SLn.
  • the drive power is supplied from the pixel circuit driving power unit 14.
  • the image data extracted by the image data extractor 11 is also supplied to the image data memory 15 for storage therein.
  • the image data memory 15 may store a single image or a plurality of images.
  • the switch SW1 is switched to couple the image data memory 15 to the data driver 16
  • the switch SW2 is set such as to couple the synchronizing signal generator 13 to the image data memory 15, the data driver 16, and the scan driver 17.
  • the image data stored in the image data memory 15 is read in synchronization with the synchronizing signals generated by the synchronizing signal generator 13 for provision to the data driver 16.
  • the data driver 16 and the scan driver 17 operate based on the synchronizing signals generated by the synchronizing signal generator 13. This makes it possible to present an image or images stored in the image data memory 15 on the screen of the display panel 18. With this provision, an image shown on the screen may be paused, or a video segment may be repeated as a replay function.
  • Fig. 2 is an expanded view of the display panel 18.
  • Fig. 2 illustrates a portion of the display panel 18 in which the pixel circuits Pk1, Pk(1+1), and P(k+1)1 are shown.
  • Each pixel circuit includes a pixel control circuit 20 and an OLED (organic light emitting diode) 21.
  • OLED organic light emitting diode
  • an active-matrix OLED display is shown as a non-limiting example in Fig. 2, and that the present invention is equally applicable to an inorganic LED display or even to a non-emission type display as long as an active matrix configuration is employed.
  • each pixel circuit is connected to four lines, i.e., a corresponding scan-power line, a next scan-power line, a corresponding data line, and a ground line.
  • each pixel circuit still has four electrodes, i.e., two power-supply electrodes for providing a power-supply potential and a ground potential, a scan electrode, and a data electrode.
  • four types of lines are provided (instead of three in the invention) in the display panel, i.e., the scan-power lines, the data lines to provide data to be stored in each pixel, the power-supply lines and the ground line.
  • each pixel circuit is connected to the different lines of the panel using four electrodes as in the prior art, but only three types of lines (instead of four in the prior art) that extend through the active-matrix panel.
  • This is made possible by connecting each pixel circuit to a corresponding scan-power line and also to a next scan-power line. That is, the pixel circuit Pkl, for example, is connected to the corresponding scan-power line SLk and also connected to the next scan-power line SLk+1.
  • the scan-power line SLk serves as a power-supply line for providing a power-supply potential to this circuit Pkl, whereas the next scan-power line SLk+1 serves as a scan line for scanning the corresponding row to which this circuit Pkl belongs. Further, this scan-power line SLk+1 serving as a scan line for the pixel circuit Pkl serves as a power-supply line for the pixel circuit P(k+1)1 provided on the next row. This pixel circuit P(k+1)1 uses the scan-power line SLk+2 as a scan line.
  • each of the scan-power lines has dual functions so as to serve both as a power-supply electrode and as a scan electrode.
  • This provision makes it possible to provide each pixel circuit with a power-supply potential, a ground potential, a scan signal, and a data signal, with only three types of lines laid out through the active-matrix structure.
  • Fig. 3 is a signal waveform diagram for explaining the operation of the pixel circuit of Fig. 2.
  • a signal of each scan-power line is comprised of a scan-pulse period and a power period.
  • the scan-pulse period corresponds to a low signal level
  • the power period corresponds to a high signal level.
  • the scan-pulse periods appear one after another in successive scan-power lines for the purpose of scanning successive rows.
  • the pixel circuit Pkl is driven during the power period of the scan-power line SLk. While the pixel circuit Pkl is driven, the next scan-power line SLk+1 enters into a scan-pulse period. In response to this scan-pulse period of the scan-power line SLk+1, the pixel circuit Pkl reads data on the data line DL1 for storage therein. In the example of Fig. 3, the data line DL1 has a data pulse that is LOW at the timing corresponding to the scan-pulse period of the scan-power line SLk+1. As a result, the pixel control circuit 20 outputs a HIGH-level signal for a duration corresponding to the power period of the scan-power line SLk, resulting in the OLED 21 emitting light during this time period.
  • Fig. 4 is a circuit diagram showing an example of the logic construction of the pixel circuit.
  • Fig. 4 illustrates a circuit that is implemented by use of logic gates. While such a circuit provides a simple logic that is easy to understand, the circuit size may be prohibitively large for practical use.
  • the pixel circuit of Fig. 4 includes an AND gate 31, NOR gates 32 through 34, an NMOS transistor 35, and the OLED 21.
  • the NOR gates 33 and 34 have their outputs coupled to each other's input, thereby forming a latch.
  • One input of the AND gate 31 is a negative logic input, and is connected to the scan -power line SLk+1. As the scan-power line SLk+1 changes to LOW during the scan-pulse period, data on the data line DL1 is input into the latch. If the data is LOW as shown in Fig. 3, the latch is set, so that the gate node of the NMOS transistor 35 becomes HIGH, resulting in an electric current running through the OLED 21.
  • the OLED 21 thus emits light during the power period of the scan-power line SLk as shown in Fig. 3. If the data on the data line DL1 is HIGH, on the other hand, the latch is reset, so that the gate node of the NMOS transistor 35 becomes LOW, resulting in no electric current running through the OLED 21. The OLED 21 thus does not produce light during the power period of the scan-power line SLk.
  • Fig. 5 is a circuit diagram showing another example of a pixel circuit according to the invention.
  • the circuit construction of Fig. 5 is simple and suitable for actual implementation.
  • the pixel circuit of Fig. 5 includes NMOS transistors 41 through 43, a capacitor 44, a resistor 45, and the OLED 21.
  • the circuit construction of Fig. 5 achieves the same logic as that of Fig. 4, except that the data line DL1 is driven according to a positive logic in Fig. 5.
  • the HIGH-level period of the scan-power line SLk defines a power period during which the pixel circuit of Fig. 5 is driven.
  • the NMOS transistor 43 becomes nonconductive, thereby a positive voltage being applied to the gate of the NMOS transistor 41.
  • the NMOS transistor 41 becomes conductive to pass data on the data line DL1 to the capacitor 44.
  • the capacitor 44 serves as an information storage, and is charged according to the voltage level of the data line DL1. If the data is HIGH, the gate node of the NMOS transistor 42 becomes HIGH, resulting in an electric current running through the OLED 21.
  • the OLED 21 thus emits light during the power period of the scan-power line SLk. If the data on the data line DL1 is LOW, on the other hand, the gate node of the NMOS transistor 42 becomes LOW, resulting in no electric current running through the OLED 21. The OLED 21 thus does not produce light during the power period of the scan-power line SLk.
  • the simple circuit construction shown in Fig. 5 achieves the same logic as that of Fig. 4, except for the difference between a positive logic and a negative logic in respect of data values (the use of a negative logic may require a more complex circuit than that shown in Fig.5).
  • the circuit of Fig. 5 is substantially simple, and is suitable as an actual circuit construction for practical use.
  • Fig. 6 is a signal waveform diagram for explaining the brightness control of light emission in the pixel circuit of Fig. 5.
  • the HIGH-level period of the scan-power line SLk is a power period during which the pixel circuit of Fig. 5 is driven.
  • the scan-power line SLk+1 becomes LOW a first time data D1 on the data line DL1 is read and stored in the capacitor 44, resulting in the OLED 21 shining with brightness responsive to D1. This level of brightness continues for the duration of the power period, and the OLED 21 is turned off at the end of the power period.
  • the scan-power line SLk+1 becomes LOW a second time with the start of the next power period data D2 on the data line DL1 is read and stored in the capacitor 44, resulting in the OLED 21 shining with brightness responsive to D2. This level of brightness continues for the duration of the power period.
  • the circuit of Fig. 5 can control the brightness of the OLED 21 according to data on the data line DL1.
  • the brightness of the OLED 21 may be limited to binary levels (i.e., on/off), and gray-scale representation is achieved by use of a sub-field method which is typically used in plasma displays.
  • the sub-field method one second is divided into a plurality of fields (e.g., 60 fields per second), and each field is further divided into a plurality of sub-fields (typically 8 sub-fields). These sub-fields are configured to have respective durations, ratios of which are typically 1:2:4:8:16:32:64:128 in the case of 8 sub-fields.
  • An on/off state of a given pixel is controlled separately for each sub-field, so that this pixel may shine during one or more sub-fields for which it is directed to shine.
  • a total time length of light emission of this pixel in one field period can be controlled, and can be set to 255 different time lengths in the case of 8 sub-fields.
  • Such different time lengths are perceived as different brightness levels by human vision, thereby achieving gray-scale representation by using only an on/off binary state of the OLED 21.
  • Fig. 7 is a signal waveform diagram showing a variation of signals on the scan-power lines.
  • signals on the scan-power lines SLk through SLk+2 become LOW indicative of a scan-pulse period one after another in successive scan -power lines, with a gap G between adjacent scan-pulse periods.
  • Fig. 8 is a circuit diagram showing an example of the construction of a pixel circuit that is specifically designed for the scan-power line signals of Fig. 7.
  • the same elements as those of Fig. 4 are referred to by the same numerals, and a description thereof will be omitted.
  • the pixel circuit of Fig. 8 differs from the pixel circuit of Fig. 4 in that a circuit block 50 is additionally provided.
  • the circuit block 50 includes registers 51 and 52, a capacitor 53, and an NMOS transistor 54.
  • the NMOS transistor 54 turns on, thereby changing the output of the circuit block 50 from HIGH to LOW, which allows the latch comprised of the NOR gates 33 and 34 to perform its latch operation.
  • the circuit block 50 With proper selection of resistance and capacitance, the circuit block 50 provides a proper delay that is equivalent to the length of the gap period G.
  • Fig. 9 is a signal waveform diagram showing another variation of signals on the scan-power lines.
  • signals on the scan-power lines SLk through SLk+2 become LOW indicative of a scan-pulse period one after another in successive scan-power lines, with an overlap "O" between adjacent scan-pulse periods.
  • the scan-pulse periods of the scan-power lines should be accompanied by respective data signals on a given data line.
  • the scan-pulse periods of adjacent scan-power lines are overlapping in Fig. 9, data signals cannot overlap on a given data line. As shown in Fig. 9. therefore, data pulses on the data line DL1 may only be valid during an early period within the respective scan-pulse periods. Because of this, the circuits of Fig. 4 and Fig. 5 may not properly work in the case of scan-power line signals as shown in Fig. 9.
  • Fig. 10 is a circuit diagram showing an example of the construction of a pixel circuit that is specifically designed for the scan -power line signals of Fig. 9.
  • Fig. 10 the same elements as those of Fig. 4 are referred to by the same numerals, and a description thereof will be omitted.
  • the pixel circuit of Fig. 10 differs from the pixel circuit of Fig. 4 in that a circuit block 60 is additionally provided.
  • the circuit block 60 is a one-shot circuit, and includes a NAND gate 61, a capacitor 62, a resistor 63, and an inverter 64.
  • a potential at node A i.e., input into the inverter 64
  • An electric current then flows through the register 63 to charge the capacitor 62.
  • electric charge in the capacitor 62 builds up, a potential drops at the node A.
  • the circuit block 60 outputs a shortened data pulse, thereby ensuring a proper operation of the pixel circuit even when the scan-power signals have overlaps as shown in Fig. 9.
  • Fig. 11 is a circuit diagram showing another example of the construction of a pixel circuit that is specifically designed for the scan-power line signals of Fig. 9.
  • Fig. 11 the same elements as those of Fig. 5 are referred to by the same numerals, and a description thereof will be omitted.
  • the pixel circuit of Fig. 11 differs from the pixel circuit of Fig. 5 in that a circuit block 60A is additionally provided.
  • the circuit block 60A is a one-shot circuit, and includes inverters 65 and 66, a capacitor 67, and a resistor 68.
  • a potential at node B i.e., input into the inverter 66
  • An electric current then flows through the register 68 to charge the capacitor 67.
  • electric charge in the capacitor 67 builds up, a potential drops at the node B.
  • the output of the inverter 66 changes from LOW to HIGH.
  • the inverter 66 outputs a shortened data pulse, thereby ensuring a proper operation of the pixel circuit even when the scan-power signals have overlaps as shown in Fig. 9.
  • Fig. 10 and Fig. 11 may also be used even when an end of each scan-pulse period is aligned with a start of a next scan-pulse period.
  • Fig. 12 is a signal waveform diagram showing a case in which an end of each scan-pulse period is aligned with a start of a next scan-pulse period but data pulses on a given data line are shorter than corresponding scan-pulse periods.
  • the one-shot circuit as described above may effectively be used to limit the time period during which the pixel circuit reads data on the data line.
  • circuit block used in Fig. 8 and the one-shot circuit used in Fig. 10 and Fig. 11 may be combined as such a need arises.
  • a data pulse (data signal) on a given data line may be shorter than a corresponding scan-pulse period, and successive scan-pulse periods in adjacent scan-power lines may be spaced apart with a gap as shown in Fig. 7.
  • the circuit block as used in Fig. 8 may additionally be provided to cope with the spaced-apart scan-pulse periods
  • the one-shot circuit used in Fig. 10 and Fig. 11 may also be provided to cope with the shorter data pulse.
  • Fig. 13 is a signal waveform diagram showing a variation of the signal of a scan-power line and the signal of a data line.
  • the signal of the scan-power line SLk in this case includes a scan-pulse period defined as a zero-potential period and a power period defined as a negative-potential period.
  • the signal of the data line is a positive logic in which "1" is represented by a higher potential (zero potential) and "0" is represented by a lower potential (negative potential).
  • Fig. 14 is a circuit diagram showing an example of the construction of a pixel circuit that is used with the signal arrangement of Fig. 13.
  • the pixel circuit of Fig. 14 includes AND gates 71 and 72, NOR gates 73 and 74, an NMOS transistor 75, and the OLED 21.
  • the NOR gates 73 and 74 have their outputs coupled to each other's input, thereby forming a latch.
  • Logic on which the operation of this circuit is based is substantially the same as that of Fig.4, and a description thereof will be omitted.
  • Fig. 15 is an illustrative drawing showing a variation of the pixel circuit according to the invention.
  • a circuit block 80 is inserted into the output of the pixel control circuit 20, such that the output of the circuit block 80 is supplied to the OLED 21.
  • the circuit block 80 includes a switch 81 and a capacitor 82.
  • the switch 81 is closed while power is supplied to the pixel control circuit 20. If the pixel control circuit 20 has data stored therein indicative of the emission of light, thus, an electric current is supplied to the OLED 21 to turn it on.
  • the switch 81 is opened when power is not supplied to the pixel control circuit 20. If the OLED 21 was on before the opening of the switch 81, the OLED 21 continues to be on for a while as an electric current is supplied from the capacitor 82 that is discharging.
  • Fig. 16 is a signal waveform diagram showing the operation of the pixel circuit of Fig. 15. As shown in Fig. 16, the OLED 21 continues emitting light even after power is turned off at timing T1. This is because the capacitor 82 illustrated in Fig. 15 supplies power to the OLED 21 while no power is supplied to the pixel control circuit 20 from the scan-power line SLk. With this provision, sudden turning off of the OLED 21 is avoided, and the emission of the OLED 21 slowly diminishes. This may contribute to better appearance of images to human eyes.
  • Fig. 17 is a circuit diagram showing an example of an actual implementation of the circuit of Fig. 15.
  • the NOR gates 33 and 34 and the NMOS transistor 35 are the same as those shown in Fig. 4.
  • the switch 81 is implemented by use of an NMOS transistor in this example.
  • the NMOS transistor 81 becomes conductive to couple the OLED 21 to the power-supply voltage (assuming that the NMOS transistor 35 is conductive).
  • the scan-power line SLk is changed to LOW, the NMOS transistor 81 becomes nonconductive, resulting in the capacitor 82 providing power to the OLED 21.
  • the scan-power lines are given dual functions, serving both as a scan line and as a power-supply line.
  • a ground line may be given dual functions, serving both as a scan line and a ground line.
  • Fig. 18 is an illustrative drawing showing the construction of a pixel circuit and relevant electrodes according to a variation of the invention.
  • Each pixel circuit includes a pixel control circuit 120 and an OLED (organic light emitting diode) 121.
  • OLED organic light emitting diode
  • a scan-ground line two of which are shown as SGk and SGk+1
  • a data line one of which is shown as DL1
  • a power-supply line illustrated as a power-supply node V DD
  • Each pixel circuit is connected to four lines, i.e., the corresponding scan-ground line SGk, the next scan-ground line SGk+1, the corresponding data line DL1, and the power-supply line V DD .
  • each pixel circuit needs to have four electrodes, i.e., two power-supply electrodes for providing a power-supply potential and a ground potential, a scan electrode for scanning each row, and a data electrode serving as a column line to provide data to be stored in each pixel.
  • These four electrodes extend in the row direction or the column direction throughout the active-matrix panel.
  • each pixel circuit is connected to four electrodes, but only three types of lines extend through the active-matrix panel. This is made possible by connecting each pixel circuit to a corresponding scan-ground line and also to a next scan-ground line. That is, the pixel circuit of Fig. 18 is connected to the corresponding scan-ground line SGk and also connected to the next scan-ground line SGk+1.
  • the scan-ground line SGk serves as a ground electrode for providing a ground potential
  • the next scan-ground line SGk+1 serves as a scan electrode for scanning the corresponding row.
  • this scan-ground line SGk+1 serving as a scan electrode for the pixel circuit of Fig. 18 serves as a ground electrode for a pixel circuit provided on the next row.
  • This pixel circuit on the next row uses a next scan-ground line SGk+2 as a scan electrode.
  • each of the scan-ground lines has dual functions so as to serve both as a ground electrode and as a scan electrode.
  • This provision makes it possible to provide each pixel circuit with a power-supply potential, a ground potential, a scan signal, and a data signal, with only three networks of lines laid out through the active-matrix structure.
  • Fig. 19 is a signal waveform diagram for explaining the operation of the pixel circuit of Fig. 18.
  • the pixel circuit of Fig. 18 is driven during the ground-level period of the scan-ground line SGk. While the pixel circuit is driven, the next scan-ground line SGk+1 enters into a scan-pulse period that is defined by a HIGH signal level.
  • the pixel circuit reads data on the data line DL1 for storage therein.
  • the data line DL1 has a data pulse that is HIGH at the timing corresponding to the scan-pulse period of the scan-ground line SGk+1.
  • the pixel control circuit 120 outputs a HIGH-level signal for a duration corresponding to the ground-level period of the scan-ground line SGk, resulting in the OLED 121 emitting light during this time period.
  • Fig. 20 is a circuit diagram showing an example of the pixel circuit according to the variation of the invention.
  • the circuit construction of Fig. 20 is simple and suitable for actual implementation.
  • the pixel circuit of Fig. 20 includes NMOS transistors 131 and 132, a capacitor 133, and the OLED 21.
  • This pixel circuit is driven during a period in which the scan-ground line SGk is set to a ground level.
  • the scan-ground line SGk+1 changes to HIGH during the scan-pulse period
  • the NMOS transistor 131 becomes conductive, thereby passing data on the data line DL1 to the capacitor 133.
  • the capacitor 133 serves as an information storage, and is charged according to the voltage level of the data line DL1. If the data is HIGH, the gate node of the NMOS transistor 132 becomes HIGH, resulting in an electric current running through the OLED 21.
  • the OLED 21 thus emits light during the ground-level period of the scan-ground line SGk. If the data on the data line DL1 is LOW, on the other hand, the gate node of the NMOS transistor 132 becomes LOW, resulting in no electric current running through the OLED 21. The OLED 21 thus does not produce light during the ground-level period of the scan-ground line SGk.
  • the simple circuit construction shown in Fig. 20 achieves the operation required of a pixel circuit, with only three types of lines laid out in the active-matrix configuration.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
EP04300319A 2004-06-09 2004-06-09 Aktivmatrix-Anzeigevorrichtung mit verringerter Anzahl von Electroden Withdrawn EP1605431A1 (de)

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EP04300319A EP1605431A1 (de) 2004-06-09 2004-06-09 Aktivmatrix-Anzeigevorrichtung mit verringerter Anzahl von Electroden

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113781951A (zh) * 2020-06-09 2021-12-10 京东方科技集团股份有限公司 一种显示面板及驱动方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0653741A1 (de) * 1993-10-12 1995-05-17 Nec Corporation Anordnung von stromgesteuerten Lichtelementen und Herstellungsverfahren
US6380689B1 (en) * 1999-10-06 2002-04-30 Pioneer Corporation Driving apparatus for active matrix type luminescent panel
US6475845B2 (en) * 2000-03-27 2002-11-05 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0653741A1 (de) * 1993-10-12 1995-05-17 Nec Corporation Anordnung von stromgesteuerten Lichtelementen und Herstellungsverfahren
US6380689B1 (en) * 1999-10-06 2002-04-30 Pioneer Corporation Driving apparatus for active matrix type luminescent panel
US6475845B2 (en) * 2000-03-27 2002-11-05 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113781951A (zh) * 2020-06-09 2021-12-10 京东方科技集团股份有限公司 一种显示面板及驱动方法

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