EP1588319A1 - Module for a hybrid card - Google Patents
Module for a hybrid cardInfo
- Publication number
- EP1588319A1 EP1588319A1 EP04700743A EP04700743A EP1588319A1 EP 1588319 A1 EP1588319 A1 EP 1588319A1 EP 04700743 A EP04700743 A EP 04700743A EP 04700743 A EP04700743 A EP 04700743A EP 1588319 A1 EP1588319 A1 EP 1588319A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- integrated circuit
- chip
- predefined
- iso
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07745—Mounting details of integrated circuit chips
- G06K19/07747—Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/072—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising a plurality of integrated circuit chips
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07743—External electrical contacts
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
- G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
- G06K19/07766—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card comprising at least a second communication arrangement in addition to a first non-contact communication arrangement
- G06K19/07769—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card comprising at least a second communication arrangement in addition to a first non-contact communication arrangement the further communication means being a galvanic interface, e.g. hybrid or mixed smart cards having a contact and a non-contact interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
Definitions
- the invention relates to a semiconductor assembly comprising a support layer, a first integrated circuit and a second integrated circuit.
- the invention also concerns a portable object of the smartcard type, for example, an integrated circuit card, in particular an hybrid card and more generally any smart card comprising two chips into one module.
- German patent application referenced under number DE 197 35 170 discloses a chip-module comprising a first chip (4) fixed onto a support layer (1).
- the support layer is further provided with a cavity (8) so that a second chip (3) can be fixed in a different height-configuration.
- a semiconductor assembly comprising a support layer, a first integrated circuit and a second integrated circuit, the support layer comprising a first side and a second side, the first side comprising a set of contact pads, the second side comprising a set of predefined areas, the set of predefined areas comprising a main predefined area and a plurality of auxiliary predefined areas, each auxiliary predefined area comprising a connection hole, a connection hole being connected to a contact pad, the first integrated circuit comprising at least one connection pad connected to at least one auxiliary area with connecting means, the second integrated circuit comprising at least one connection pad connected to at least one auxiliary area with connecting means, wherein the second integrated circuit is located onto the main predefined area.
- the first chip can be, for example, an ISO-chip arranged to communicate with another device using an ISO protocol, for example, the ISO 7816 protocol.
- the second chip can be, for example, an RF chip.
- the predefined areas may correspond, for example, to areas comprising connection holes
- the connecting means can be, for example, bonding wires.
- the length of the bonding wires is more uniform.
- Figure 1 illustrates a method of manufacturing the module of a hybrid card
- Figure 2 illustrates a smartcard body provided with a cavit
- Figure 3 illustrates a module into which two chips are placed in a side-by- side configuration
- FIG. 4, 5 and 6 illustrate one possible semiconductor assembly embodiment according to the invention ;
- Figure 7 and 8 illustrate another possible embodiment in which the module is connected to an antenna ; and Figure 9 illustrates another possible embodiment.
- Figure 1 illustrates a method of manufacturing the module of a hybrid card.
- a lead-frame comprises a first side (not represented) provided with eight contact pads (not represented) and a second side (LFSS) provided with ISO 7816 connection holes Cl, C2, C3, C4, C5, C6, C7 and C8.
- the connection holes (Cl, C2, C3, C4, C5, C6, C7, C8) are mechanically and electrically connected to the contact pads.
- An ISO-chip (ISOC) is placed on the second side (LFSS) of the lead-frame.
- An ISO chip is a chip, which is arranged to communicate with another device using an ISO protocol, for example, the ISO 7816 protocol. In the case of the ISO 7816 protocol the ISO chip is provided with at least five connection pads.
- an RF chip provided with two connection pads, is then stacked on the ISO chip so as to form a stacked-assembly (ISOC, RFC).
- An RF chip is a chip, which is arranged to work with an antenna.
- the connection pads of the ISO-chip are connected with bonding wires to the connection holes Cl, C2, C3, C5 and C7 of the lead-frame (LF).
- connection pads of the RF chip are also connected with bonding wires to the connection holes C4 and C8 of the lead-frame (LF).
- the geometrical distribution of the connection pads of the ISO chip and of the RF chip is made so that the bonding wires of ISO chip do not cross the bonding wires of the RF chip.
- a protective resin material can be deposited on the RF chip, the ISO chip and the bonding wires so as to obtain a module (MOD).
- the module (MOD) can be embedded in the cavity (CAN) of a card body (C) so as to obtain a hybrid card. If the height of the stacked-assembly (ISOC, RFC) is greater than the depth of the cavity (CAN), prior to the connecting step, in a thinning step, at least one of the two chips can be thinned so that the module (MOD) can be embedded in the cavity (CAN) of the card body (C) without having to modify the geometry of the cavity (CAN).
- the hybrid card is then inserted into, for example, a cardholder provided with an antenna or a mobile phone provided with an antenna.
- the RF chip of the hybrid card can thus work with the antenna of the cardholder through, in particular, the connection holes C4 and C8 and the contact pads of the lead-frame.
- the hybrid card can also be inserted in a mobile phone provided with an antenna. More generally the hybrid card can be inserted in any other portable device comprising an antenna, the antenna being arranged to work with the RF chip of the hybrid card.
- the two chips may also be placed in a side-by-side configuration.
- the RF chip (RFC) is placed next to the ISO chip (ISOC), between, for example, a row of connection holes (C5, C6, C7, C8) and the ISO chip (ISOC).
- the connections pads of the ISO-chip are connected with bonding wires (LBW, SBW) to the connection holes Cl, C2, C3, C5 and C7 of the lead-frame.
- the connection pads of the RF chip (RFC) are connected with bonding wires (LBW, SBW) to the connection holes C4 and C8 of the lead-frame (LF).
- connection holes C5, C6, C7, C8
- ISO chip ISO chip
- the RF chip (RFC) has a length and a width of 1,1mm.
- the ISO chip is put close to a row of connection holes (Cl, C2, C3, C4).
- the thinning step is not needed anymore.
- the manufacturing process of the hybrid card is thus easier to carry out.
- the risk of damaging the chip during the manufacturing process of the hybrid card is reduced thus enhancing the quality of the hybrid card.
- the RF chip and the ISO chip are less close than in a stacked configuration. The risk of having some radio- frequency interferences between the RF chip and the ISO-chip is thus reduced.
- the RF chip can be advantageously placed at the place of the connection hole C6.
- the connection hole C6 is namely generally not used in standard ISO application. In particular, this connection hole C6 can be removed.
- the ISO chip ISOC
- ISO 7816 connection holes Cl, C2, C3, C5 and C7 of the module by means of bonding wires (BW).
- Conductive tracks (CT) are added on the second side (LFSS) of the lead-frame (LF).
- the connection pads of the RF chip (RFC) are connected using bonding wires (BW) to the conductive tracks (CT).
- CT conductive tracks
- CT are connected to the connection holes C4 and C8 of the lead-frame (LF).
- connection pads of RF chip are thus connected to the connection holes C4 and C8 of the lead-frame (LF).
- the conductive tracks are made, for example, of copper. The use of conductive tracks thus enables to avoid that one bonding wire cross another bonding wire.
- the RF chip By placing the RF chip (RFC) at the place of the connection hole C6, one can use a bigger RF chip than in the side-by-side configuration illustrated in figure 3.
- the RF chip can have, for example, a width of 1,67 mm and a length of 2,34mm.
- the ISO chip does not need to be put close to the row of connection holes (Cl, C2, C3, C4).
- the length of the various bonding wires (BW) is therefore more uniform. Consequently the manufacturing process is thus easier to carry out and; in the resin-depositing step, the spreading of the protective resin material is more regular. Thus, the quality of the process is enhanced.
- the RF chip is less close from the ISO chip than in the stacked configuration illustrated in figure 1. The risk of radio-frequency interferences is thus reduced.
- no thinning step is needed.
- the above-mentioned description describes a semiconductor assembly comprising a support layer, a first integrated circuit and a second integrated circuit.
- the support layer comprises a first side and a second side.
- the first side comprises a set of contact pads.
- the second side comprises a set of predefined areas.
- the set of predefined areas comprises a main predefined area and a plurality of auxiliary predefined areas.
- Each auxiliary predefined area comprises a connection hole.
- a connection hole is connected to a contact pad.
- the first integrated circuit comprises at least one connection pad connected to at least one auxiliary area with connecting means.
- the second integrated circuit comprises at least one connection pad connected to at least one auxiliary area with connecting means.
- the second integrated circuit is located onto the main predefined area.
- the semiconductor assembly is, for example, a module that can be embedded in the card body of a smart card. More generally it can be any other assembly comprising a support layer and an integrated circuit.
- the smart card can be an integrated circuit card having the geometry of an ISO bank card.
- the integrated circuit card can also be a small sized card like, for example, a Subscriber Identity Module card or any other card like object comprising an integrated circuit.
- the support layer was a lead frame. More generally, the invention applies for any other support layer comprising a set of predefined area.
- the predefined areas correspond to the areas comprising the connection holes (C1,C2,C3,C4,C5,C6,C7,C8).
- the main area corresponds to the area comprising the connection hole C6. More generally, as illustrated in figure 9, the main predefined area does not necessarily comprise a connection hole C6. Even more generally, a main predefined area is an area onto which can be fixed an integrated circuit, for example, an RF chip.
- the second integrated circuit is an RF chip. More generally, it can be any integrated circuit than can be fixed on the main predefined area.
- the integrated circuit can be, for example, a memory chip or a chip comprising security features against chemical, or current analysis attacks.
- the module (MOD) can be connected to an antenna, which is inserted on the card, by using additional conductive areas (AC A). Then the card becomes a hybrid card that can work without using a specific cardholder.
- a wire bonding process has been used to connect a chip (RFC, ISOC) to the lead frame (LF). But any other connecting process can be used like, for example, a flip chip process.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Theoretical Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Geometry (AREA)
- Credit Cards Or The Like (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04700743A EP1588319A1 (en) | 2003-01-08 | 2004-01-08 | Module for a hybrid card |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03290044 | 2003-01-08 | ||
EP20030290044 EP1437684A1 (en) | 2003-01-08 | 2003-01-08 | Module for a hybrid card |
PCT/IB2004/000015 WO2004063980A1 (en) | 2003-01-08 | 2004-01-08 | Module for a hybrid card |
EP04700743A EP1588319A1 (en) | 2003-01-08 | 2004-01-08 | Module for a hybrid card |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1588319A1 true EP1588319A1 (en) | 2005-10-26 |
Family
ID=32479964
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP20030290044 Withdrawn EP1437684A1 (en) | 2003-01-08 | 2003-01-08 | Module for a hybrid card |
EP04700743A Withdrawn EP1588319A1 (en) | 2003-01-08 | 2004-01-08 | Module for a hybrid card |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP20030290044 Withdrawn EP1437684A1 (en) | 2003-01-08 | 2003-01-08 | Module for a hybrid card |
Country Status (2)
Country | Link |
---|---|
EP (2) | EP1437684A1 (en) |
WO (1) | WO2004063980A1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2915011B1 (en) | 2007-03-29 | 2009-06-05 | Smart Packaging Solutions Sps | CHIP CARD WITH DOUBLE COMMUNICATION INTERFACE |
EP2711874B1 (en) * | 2012-09-21 | 2015-04-15 | Oberthur Technologies | A chip module support and a method of incorporating such a chip module support in a data carrier card |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2765010B1 (en) * | 1997-06-20 | 1999-07-16 | Inside Technologies | ELECTRONIC MICROMODULE, ESPECIALLY FOR CHIP CARDS |
DE19735170A1 (en) * | 1997-08-13 | 1998-09-10 | Siemens Ag | Chip module esp. for chip card with contacts with adjacent chips |
FR2797075B1 (en) * | 1999-07-26 | 2001-10-12 | Gemplus Card Int | METHOD FOR MANUFACTURING A PORTABLE DEVICE WITH INTEGRATED CIRCUITS, OF THE SMART CARD TYPE OF REDUCED FORMAT IN RELATION TO THE STANDARD FORMAT |
-
2003
- 2003-01-08 EP EP20030290044 patent/EP1437684A1/en not_active Withdrawn
-
2004
- 2004-01-08 EP EP04700743A patent/EP1588319A1/en not_active Withdrawn
- 2004-01-08 WO PCT/IB2004/000015 patent/WO2004063980A1/en active Application Filing
Non-Patent Citations (1)
Title |
---|
See references of WO2004063980A1 * |
Also Published As
Publication number | Publication date |
---|---|
WO2004063980B1 (en) | 2004-10-07 |
EP1437684A1 (en) | 2004-07-14 |
WO2004063980A1 (en) | 2004-07-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6288904B1 (en) | Chip module, in particular for implantation in a smart card body | |
US6719206B1 (en) | Data transaction card and method of manufacture thereof | |
RU2412483C2 (en) | Electronic module having double communication interface, particularly for smart cards with microchip | |
US7823322B2 (en) | Silicon chip having inclined contact pads and electronic module comprising such a chip | |
US10685275B2 (en) | Method for fabricating a smart card device | |
CN106611212B (en) | Double-interface IC card | |
US20150107092A1 (en) | Manufacture Of A Smart Card | |
JP2010522919A (en) | Double communication interface IC card | |
WO2013113945A1 (en) | Rfid antenna modules and methods | |
TWI488124B (en) | Integrated circuit film and method of manufacturing the same | |
KR20160018725A (en) | Method for making an anti-crack electronic device | |
CN107111779B (en) | Method for manufacturing a single-sided electronic module comprising an interconnection zone | |
WO2004063980A1 (en) | Module for a hybrid card | |
US7095103B1 (en) | Leadframe based memory card | |
JP2004355604A (en) | Ic module for ic card, ic card, and sim | |
KR102043102B1 (en) | Digital credit card with improved durability | |
EP1947691A1 (en) | Circuit carrier laminate and circuit carrier for mounting a semiconductor chip of a smartcard module, and manufacturing methods thereof | |
EP2636001A2 (en) | Sim card and manufacturing method | |
WO2002078080A1 (en) | Chip module with bond-wire connections with small loop height | |
KR101021501B1 (en) | Card-type information recording medium and manufacturing method therefor | |
EP1947690A1 (en) | Circuit carrier laminate and circuit carrier for mounting a semiconductor chip of a smartcard module, and manufacturing methods thereof | |
EP1837796A1 (en) | Connector for smart card | |
EP1947594A1 (en) | Circuit carrier laminate and circuit carrier for mounting a semicaonductor chip of a smartcard module, and manufacturing methods thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20050804 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR |
|
AX | Request for extension of the european patent |
Extension state: AL LT LV MK |
|
DAX | Request for extension of the european patent (deleted) | ||
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: GEMALTO SA Owner name: SCHLUMBERGER MALCO, INC. |
|
17Q | First examination report despatched |
Effective date: 20120308 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 20160802 |