CN107111779B - Method for manufacturing a single-sided electronic module comprising an interconnection zone - Google Patents

Method for manufacturing a single-sided electronic module comprising an interconnection zone Download PDF

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Publication number
CN107111779B
CN107111779B CN201680004744.8A CN201680004744A CN107111779B CN 107111779 B CN107111779 B CN 107111779B CN 201680004744 A CN201680004744 A CN 201680004744A CN 107111779 B CN107111779 B CN 107111779B
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China
Prior art keywords
module
metallization
chip
carrier
interconnection
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CN201680004744.8A
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Chinese (zh)
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CN107111779A (en
Inventor
S.奥托邦
L.多塞托
L.查理斯
T.拉维龙
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Thales Digital Security France Easy Stock Co
Thales DIS Design Services SAS
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Gemalto SA
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Publication of CN107111779A publication Critical patent/CN107111779A/en
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745Mounting details of integrated circuit chips
    • G06K19/07747Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • G06K19/07754Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna the connection being galvanic
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07766Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card comprising at least a second communication arrangement in addition to a first non-contact communication arrangement
    • G06K19/07769Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card comprising at least a second communication arrangement in addition to a first non-contact communication arrangement the further communication means being a galvanic interface, e.g. hybrid or mixed smart cards having a contact and a non-contact interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating

Abstract

The invention relates to a method for manufacturing an electronic chip module (17), said electronic chip module (17) comprising a metallization accessible from a first side of the metallization and an integrated circuit chip disposed from a second side of said metallization opposite to said first side. The method is characterized in that it comprises a step of forming an electrical interconnection element (9C, 19C, 30), said electrical interconnection element (9C, 19C, 30) being directly connected to said chip and being disposed from a second side of said metallization, distinct from said metallization. The invention also relates to a module corresponding to said method and to a device comprising said module.

Description

Method for manufacturing a single-sided electronic module comprising an interconnection zone
Technical Field
The invention relates to a method for manufacturing an electronic chip module comprising a metallization (or electrical contact surface) accessible from a first side of the metallization and an integrated circuit chip disposed from a second side of said metallization opposite to said first side.
The module is preferably for electrical interconnection with an interconnection terminal disposed in a carrier of the device.
The invention relates in particular to an electronic chip device, such as a chip card comprising such a module. Such devices may include various electronic components, such as, for example, a display, a keyboard, a battery, etc.; these devices may generate functions such as generating a single use number (OTP), allowing the display of the most recent banking transaction performed (all in relation to standard functions of the type of payment, transfer, identification, etc.).
The invention also relates to the field of electronic supports, such as contact and/or contactless chip cards or hybrid cards, radiofrequency tickets or tags, radiofrequency transponders, inserts (or inlays) integrating or constituting such modules.
Such an electronic chip carrier or device may in particular comply with the ISO/IEC 14443 or ISO 78016 standard.
The term "electric circuit" means all or part of an electric current conducting element, in particular an electric contact surface, an electric conducting trace, a connection, a redirecting trace, an electric contact related or unrelated to at least one integrated circuit or electronic/electric component (capacitance, coil, resistance, etc.) connected to the electric circuit. Said integrated circuit chip is a chip known in the field of chip cards, in particular a dual interface (contact and contactless), an electroluminescent diode, an audio sensor, a microcontroller, and (in particular) a Near radio frequency field communication controller NFC (Near field communication).
Background
Us patent 5,598,032 describes an assembly method for a module connected to an antenna embedded in a carrier of a (contact and contactless) hybrid chip card, it being known to provide a cavity in the carrier so that the connection face of the antenna is accessible for connection with the module when the module is transferred into the cavity. Any kind of electrically conductive interconnection element may connect the connection area of the module disposed outside the envelope with the connection area of the antenna.
Furthermore, it is known to manufacture a chip card module by the following steps.
-implementing conductive tracks or conductive planes (or metallizations) on two opposite faces of a continuous dielectric carrier or insulating carrier,
-transferring at least one integrated circuit chip and fixing it on the carrier or the face via the back side of the at least one integrated circuit chip,
connecting the chip to electrically conductive contact faces disposed on the module exterior face and to interconnect faces disposed on the module interior face, in particular by means of bonding wires,
encapsulating at least the chip and/or its connections with a protective resin in an encapsulation zone around the chip,
-placing a conductive glue on the interconnection faces for connection to an antenna disposed in the card body,
the module is cut and transferred into the cavity of the card body in order to connect the interconnection terminals disposed in the card body, in particular belonging to the radio-frequency antenna.
Technical problem
The double-sided modules used in chip cards of the hybrid type (contact and contactless) require expensive metallization (in particular by electrochemical plating) on the two opposite main faces of the dielectric carrier film.
Disclosure of Invention
The invention proposes, in a preferred implementation, the use and configuration/adaptation of a single-sided metallization module for realizing the interconnection zone.
The module can connect, in particular, the interconnect terminals disposed in the carrier via the interconnect regions formed according to the invention.
The invention therefore concerns a method for manufacturing an electronic chip module comprising a metallization accessible from the outside of a first side of the metallization and an integrated circuit chip disposed from a second side of said metallization opposite to said first side, characterized in that it comprises a step of forming an electrical interconnection element (9C, 19C, 30) which is distinct from said metallization, is directly connected to said chip and is disposed from said second side of said metallization.
In other words, the interconnect element may extend over/on or through/along the interconnect region "Z".
The invention thus allows to dispense with a double-sided module. The interconnecting elements of the directly connected chips are still formed from the side of the second face (the hidden face) of the module, but a much more economical connection/redirection technique like solder wires is utilized.
Other characteristics and embodiments of the method constitute alternative embodiments of the present application.
-in particular the interconnection elements extend outside the periphery of the module and in this way these elements are subsequently cut;
one end of these interconnection elements, in particular in the form of wires, may be directly connected to the contacts of the chip by soldering, while the other end is soldered to a metal conductive face (or metallization) located outside the boundaries of the module, through a hole (or connection well) provided in the metallized dielectric carrier substrate.
-the method comprises the step of encapsulating at least a part of the chip except at least a part of the interconnection element by an encapsulating material and/or an adhesive;
-the method comprises a step of forming an interconnection point made of electrically conductive material in the interconnection zone (Z) for electrically tying/electrically contacting a portion of at least one interconnection element;
-the method comprises a step of severing the interconnection elements during the step of cutting/severing the modules from the strip;
in this way, the invention allows for easy formation of an interconnection element that is mechanically sufficiently stiff/stable for holding the interconnection element in place in the interconnection zone Z prior to connection.
The invention also aims at a method for manufacturing an electrical and/or electronic device comprising a carrier and a module obtained according to one of the preceding claims, fixed to the carrier; characterized in that the method comprises the following steps:
-forming a carrier with said ends of the second circuit, said ends being accessible in/on said carrier,
-transferring the module onto the carrier, the first circuit of the module being connected to said ends of the second circuit.
The invention also aims at a module and a device corresponding to the method.
In particular, it is aimed at an electronic chip module comprising a metallization accessible from a first side of the metallization and an integrated circuit chip disposed from a second side of said metallization opposite to said first side, characterized in that it comprises a step of forming an electrical interconnection element (9C, 19C, 30) which is distinct from said metallization, is directly connected to said chip and is disposed from said second side of said metallization.
It is also an object to an electronic chip module comprising an integrated circuit chip accessible on a first side of a dielectric substrate and on a side of a second side opposite to the first side,
characterized in that the module comprises electrical interconnection elements connecting the chips and extending over/on the second side of the substrate, extending along the second side of the substrate.
The device may preferably constitute a chip card integrated with one of the following components: a display with or without its operating circuit, a fingerprint sensor, a sensor of another physical quantity (radiation, temperature, chemical analysis, etc.), an energy source (solar cell, energy-harvesting element, primary or rechargeable battery, etc.).
The form factor of the card may be that of an ID0 card, a plug-in UICC, an electronic passport, a ticket with a thickness of less than 0.8 mm.
Drawings
Fig. 1 and 2 illustrate a prior art chip card module in top view and cross-section, respectively;
figures 3 and 4 illustrate the steps of a module implementing an embodiment of the method according to the invention according to two variants;
figure 5 is a partial section view of the module illustrated in one of the two previous figures;
figures 6 and 7 illustrate the steps of placing conductive interconnect material on the module of figures 3 and 4;
figures 8 and 9 illustrate the steps of placing the conductive interconnect material and cutting/intercepting the modules from the carrier tape, respectively, according to a preferred embodiment of the method of the invention.
Figures 9A and 10 illustrate two variants of forming the interconnection element;
figure 11 illustrates the transfer of the module and the connection of the module to the interconnection terminals disposed in the carrier;
figure 12 illustrates a variant of implementing the interconnection element with a flexible conductive sheet;
figures 13 and 14 illustrate, respectively, the placement of conductive material on the terminal portions of the conductive tracks in the cavity of the carrier body before the transfer and the connection of the modules according to another electrical interconnection.
Detailed Description
Fig. 1 and 2 illustrate a module 7 of a hybrid integrated circuit chip card of the prior art. The module 7 comprises: contact surfaces 10, 11 on a dielectric carrier or insulating carrier, in particular of the LFCC (Lead frame laminate Lead frame) type; at least one integrated circuit chip 8 is placed on the carrier 20 or on a contact or contactless metal surface. The contact surface is used to connect the contacts of the card reader to the chip.
The module likewise comprises connections 9, the connections 9 being used in particular for connecting the contact faces by means of bonding wires, by means of conductive glue or the like, the chip being either flipped (flip-chip) or not flipped; the module comprises an encapsulation of the chip and/or its connections with a protective material 14, such as a resin (glob top), which may be applied, for example, in the form of drops or by means of a replica mold.
The connection 9 connects the contact surfaces through a hole 22 provided in the insulating carrier.
The inner surface of the module, which extends almost from the edge of the envelope up to the edge of the module, may constitute an adhesive surface of the module in the plane of the cavity provided in the card body.
The module also comprises connection means 24 for connecting an antenna embedded in the card body (not shown) housing the module. These means 24 connect the two conductive faces 11 of the module through two holes 23 in the adhesive surface of the module located on the card body or at least outside the protective material 14. These two faces 11 are connected (here by means of bonding wires passing through the holes 23) to the radio-frequency contacts of the chip.
Fig. 3 and 4 illustrate the steps of implementing a module 27 with a chip 8 according to a first embodiment with two variants.
According to a characteristic of a preferred mode of manufacturing a device comprising an electronic chip module (17) according to the invention, the method comprises a step of realising a metallization (or electrical contact surface) accessible from a first side of the metallization. Here, metallization is realized on a first side of the dielectric substrate; the method further comprises the step of transferring the integrated circuit chip to a second side of the metallization opposite to said first side. The elements may extend over/on/along the metallization (in the case of metallization without dielectric; or in the case of metallization carried by dielectric hollowed out at the contact faces, behind the dielectric substrate on the side of the chip to be buried in the card body). When a dielectric base is present, the interconnect element may extend along/over/on the dielectric of a second side opposite to the first side of the metallization. Thus, the elements may extend over/along the metallization or dielectric substrate as the case may be.
Here in this example, the chip is disposed from a second side of the dielectric opposite the first side. In principle, the chip is connected to the contact surface (or metallization) by means of a bond wire.
The same reference numbers from one figure to another indicate the same or similar elements. The modules are formed on an insulating dielectric film strip 37 that includes metallization that defines a plurality of module locations. The metallization is laminated or patterned on one side of the dielectric in a known manner. Alternatively, the module may be formed on the dielectric membrane instead of the tape.
The module 27 with the integrated circuit chip or electronic chip 8 can be of almost the same type as those on the previous figures, except that the interconnecting elements extend from the chip towards the module outer shaft and are different from the first metallization.
The module 27 here comprises a substrate 20 and preferably a protective material 14 at least partially encapsulating the electronic circuit 28 in an encapsulation region 14E. The encapsulated zone 14E is surrounded by a module or bonded peripheral securing surface 14C.
The electronic chip 28 is connected to the contact face 10 in any known manner through the hole 22 (and in this case by a bonding wire).
The chip 8 preferably implements communication functions with contact and contactless card readers. The chip 8 comprises contacts for contact communication of the ISO7816 type and two contacts for contactless communication.
However, the die may enable interconnection to other circuitry (e.g., display, keyboard, switches) disposed in the carrier in addition to the antenna.
In this case, the chip is usually mounted on the module by fixing the rear side of the chip to the module (as in fig. 1). The chip active face carrying the electrical connection contacts of the chip is oriented towards the outside of the module.
In a variant of the invention, it is possible to envisage that the substrate 20 is not present, the faces or metallizations being therefore integrally retained via an encapsulation or a resin.
According to one feature, the method comprises a step of forming electrical interconnection elements (9C, 19C, 30) associated with the chip and extending on/over the second face or metallization of the substrate without being electrically connected to the metallization at least in the adhesion zone (at the periphery of the envelope) of the module.
In the example of fig. 3 and 4, the interconnection element according to the preferred mode is realized in the form of a conductive soldering wire 9C. One end of these wires is directly connected to the contacts of the chip 8 by soldering, while the other end is soldered on the contact (or metallization) surface outside the boundaries of the module 27 through holes (or connection wells) 22C, 22L provided in the dielectric substrate.
The extended solder well 22L allows a greater variety of chip contact configurations to be utilized.
According to one feature of the embodiment, the interconnection elements 9C, 19C extend in the direction of the periphery of the module 27 or beyond it; these interconnecting elements are then severed, particularly when the module is cut from its roll carrier tape 37.
In this example, the weld line 9C of the non-contact joint extends beyond the limited boundary of the module 27 to be welded in a well 22C located outside the module boundary. This zone Zt outside the zone of the module 27 corresponds to the working zone or zone of the strip 37 where the appropriate current is introduced to the module.
According to a preferred feature, the method may comprise the step of at least partially encapsulating said chip with an encapsulating material except for at least a part of the interconnection elements (extending in the interconnection zone Z).
In the examples in fig. 3-5, the chip and its contact-type wire connections 9 are encapsulated. Also enclosed is the initial part of contactless communication line 9C. The remaining portion extending from the encapsulating resin up to the reserve well 9C is not encapsulated by the insulating encapsulating resin.
According to another characteristic of a preferred mode, the method may comprise a step of forming in the interconnection zone an interconnection point 30 made of electrically conductive material so as to electrically tie/electrically contact a portion of the at least one interconnection element 9C in the interconnection zone Z.
In the example in fig. 6 and 7, the placing of at least one drop 30 of conductive material is performed, which comprises in particular particles made of silver on each conductive line 9C. Each drop forms a contact that rests on dielectric substrate 20 and extends high while restraining and contacting each conductive line 9C.
Thus, the well 22C or the well 22L has the following functions for this purpose: the wires 9C are temporarily fixed in place in the interconnect region at least during the encapsulation step or at least during the formation of the conductive contacts. Once encapsulation is performed or at least conductive contact 30 is formed, conductive line 9C is held in place almost mechanically on the trace through interconnect region "Z".
In fact, during handling of the strip 37 during manufacture, it is possible that the electrically conductive wires 9C, which are not mechanically held, are located in undesired positions under the influence of movements or vibrations caused by shifting the module from one manufacturing operating door to another.
As indicated, this problem can be alleviated by adding bond wires on the same joint and by placing multiple wire paths in the interconnect region "Z". Thereby increasing the chance of retaining at least one wire in the interconnect region "Z". Increasing the number of lines on the same chip contact also allows for improved electrical contact with the silver particles of the conductive material contact 30.
Alternatively, in a general manner, in order to fix the (initially free) end of the interconnection element, the interconnection line or interconnection element 9C may be held by adhesion to the adhesive, in particular in the interconnection zone "Z", with an interposed adhesive being laid on the module (at least in the adhesion zone of the module).
According to another characteristic of the preferred mode, the severing of the interconnection elements is carried out during the step of cutting/shearing the module from the substrate.
In the example in fig. 9, the conductive line 9C is cut off (dotted line D) at the time of cutting and transferring the module.
Alternatively, in fig. 10, the wires may be cut before the module is intercepted, in particular after the silver conductive contacts are formed (fig. 9A).
Alternatively (fig. 10), the wire 9C may be formed such that it terminates at or passes through the interconnect zone "Z" without being soldered as such in the well 22C. Prior to encapsulation, the wire is subjected to bending or buckling imparted by a welder so as to have an end portion adjacent to the surface of the insulating substrate.
The modules may thus be retained prior to interconnection, in particular by being transferred into the receiving cavities of the carrier (illustrated in fig. 10); or as illustrated in fig. 9A, the module may also and preferably houses conductive interconnects 30 formed by the placement of conductive material. This has the advantage of holding the line 9C in place and ready for subsequent interconnection.
In a general manner, harder conductive lines or interconnection elements may be used, in particular in the form of patches or by bisecting or tripartiting (not shown) the lines 9C on the same contacts.
Thus, for example, as illustrated in fig. 12, an interconnect element in the form of a conductive plate/sheet may be used for greater rigidity or mechanical stability. These conductive plates may have a width of, for example, 0.05 mm to 0.5 mm.
A conductive strip may be soldered directly to a conductive point formed on the contact without contacting the chip. The other end of the strap may remain suspended or be welded or otherwise secured outside the module area. The severing of the tape fixed outside the module area may then take place while cutting/severing the modules from the continuous carrier (lead frame).
In fig. 12, a flexible sheet 19C connects the chips via a first electrical connection relay well 22C (preferably located in an encapsulation region containing a protective material (resin)) near the peripheral adhesive region and the interconnection region "Z" of the module. The sheet is welded via its ends to two wells 22C (into the metallization 10) located in the module area 27 and outside the module area 27, respectively.
If necessary, each tab (of a larger cross section, two to 10 times larger than the diameter of the bonding wire) can be connected directly to the chip contacts. The chip contacts typically have a size of 50 to 100 μm. These sheets/strips have a size comprised between 0.1mm and 0.5mm and can be soldered on points (bumps) previously realised on the contacts. Therefore, a conductive strip (or conductive strip) having a larger width can connect the small contacts.
Preferably, the sheet is placed on (or even lightly adhered to) the dielectric close to the bottom of the chip. The interconnect lines may connect the die contacts to the die bottom by soldering and also connect each of the pads to the die bottom by soldering. The other end of the sheet may be secured by welding over a relay or work surface in a well 22C outside the module surface. The end will then be cut for its insertion by the interception of the module.
For better robustness and mechanical protection of the whole, the connection from the weld line to the tab may preferably be encapsulated by an encapsulating material 14. The sheet 19C is mechanically held in place by means of the encapsulation 14 and or a possible adhesion of one end on the dielectric in close proximity to the chip in the zone 14E.
This latter embodiment avoids having a relay conductive island (slot) (short circuit source accessible from the outside) in the well 22C formed in the metallization 10.
Alternatively, the conductive line 9C may be fixed on the dielectric substrate by heat pressing or heat bonding as well. The substrate may have a surface coating that provides adhesive properties to allow for adhesion to the thread 9C or sheet 19C.
Thus, the wires may be held in place in the interconnect region without extending beyond the module region 27.
According to a feature of a preferred form of the invention, the module is connected to the connection end 32 of the carrier during the process of securing the module to the carrier 40 (fig. 11).
The module in place in the carrier cavity in the case of a chip card body is illustrated in fig. 11.
The conductive contacts 30 of the module electrically contact terminal portions 32 of the circuit, here an antenna, located in the carrier 40 by elastic deformation. The electrical connection is achieved by simply turning the module into cavities 33 and 31. The module is fixed by an adhesive 33.
The invention provides a method for manufacturing an electrical and/or electronic device comprising a module as described previously.
The device may comprise a carrier 40 equipped with at least one cavity 31, 33, said cavity 31, 33 being provided in said carrier and the module being fixed in said cavity.
A carrier 40 may be preformed, the carrier 40 having incorporated therein the ends of the second circuit 32 and at least one cavity 31, 32, the at least one cavity 31, 32 being disposed over the connection end 32 of the second circuit so as to expose the ends 32 or to make the ends 32 accessible;
the module is then transferred into the cavity, the module being connected to said ends of the second circuit.
Alternatively (fig. 13 and 14), the conductive material is routed over terminal portions 32 of the carrier that are located in cavities 32, 32 of the carrier.
The modules transferred in the cavities 31, 33 may conform to any of the previously described implementations. The module comprises an interconnection zone Z comprising conductive interconnection elements 9C, 19C, 30 held in this zone, either individually (while attached to the chip) or bound to conductive contacts 30 or disposed in a nearby encapsulating material.
The invention thus enables an interconnection zone "Z" different from the metallization located on the first side of the module, in particular those used for connecting a contact reader. These interconnect regions advantageously use conventional interconnect elements (in particular conductive lines 9C) which are identical to those used for connecting the chip to the metallization of the module.
The chip may also be flip-chip mounted. Interconnect lines may be soldered on relay metal areas or redirection traces (outside the bond area of the module in the carrier) located near the location of the die in area 14E.
The conductive lines 9C may extend from the relay area toward the outer periphery of the module while remaining suspended in air waiting for interconnection with the terminal portions of the carrier.
Preferably, as before, conductive contacts 30 are formed that bound the wires. Alternatively, a conductive sheet 19C harder than a wire is used for remaining in the air at the time of interconnection; multiple wires 9C may also be soldered on the same relay area for facilitating interconnection.
If necessary, the invention provides for the formation of a loop portion (or loop portions) for soldering to the chip contacts or relay surfaces, which loop portion(s) passes over the interconnection zone Z from the chip contacts or from the relay surfaces and back to the point of departure, either in the usual mounting manner or in a flip-chip manner.
The loop portions may receive conductive material in the form of contacts at the interconnection zone Z.
The loop or lug from the chip contact is thus realized, which has the following advantages: has better mechanical stability than a single wire with free ends in air.
The mechanical stability of the interconnection elements 9C, 19C is important to ensure a good electrical connection (and a good positioning of the interconnection elements) when the module is transferred and connected to the respective end of the carrier.
The present invention provides for interconnecting the module with a second circuit formed against the insulating substrate 20 or on the insulating substrate 20, if necessary. The circuit may be, for example, an antenna formed by printing a conductive material.
Thus, the module is not necessarily inserted in the carrier.
Alternatively, the metallization may be disposed on one or the other side of the dielectric film. In the case where the metallizations are disposed on the back side of the carrier film (the side opposite the carrier), the openings allow access to the metallizations.
If necessary, the interconnection elements are realized as previously described, but furthermore an insulating material is disposed in the interconnection zone Z for isolating the metallization positioned upright alongside the conductive lines or sheets.

Claims (22)

1. A method of manufacturing an electronic chip module, the electronic chip module comprising:
-a metallization and an integrated circuit chip, the metallization being accessible from a first side of the metallization, the integrated circuit chip being disposed from a second side of the metallization opposite to the first side,
-an electrical interconnection element, distinct from the metallization, directly connected to the chip and disposed from a second side of the metallization,
characterized in that the electrical interconnection element is realized on a single-sided metallization module.
2. The method of claim 1,
the interconnect element extends over or along the metallization or the dielectric substrate.
3. A method according to claim 1, characterised in that the interconnecting elements extend outside the periphery of the module and in that these elements are subsequently cut off as such.
4. The method of claim 1,
one end of these interconnection elements is directly connected to the contacts of the chip by soldering, while the other end is soldered to a conductive surface or metallization located outside the boundaries of the module through holes or connection wells provided in the dielectric substrate.
5. The method of claim 1,
the method comprises the step of encapsulating at least a portion of the chip except at least a portion of the interconnection element by an encapsulating material and/or an adhesive.
6. The method of claim 1,
the method comprises the step of forming an interconnect point made of an electrically conductive material in the interconnect region for electrically tying/electrically contacting a portion of the at least one interconnect element.
7. The method of claim 1,
the method comprises the step of severing the interconnecting elements during the step of cutting/severing the modules from the strip.
8. The method of claim 1, wherein the interconnect element is disposed only inside an outer perimeter of the module.
9. A method according to claim 1, characterized in that the interconnection element is held in place over or along the interconnection zone by gluing.
10. Method according to claim 9, characterized in that the bonding is performed via an insert adhesive of the module or by hot pressing or thermal bonding on the bonding surface of the module.
11. A method for manufacturing an electrical and/or electronic device comprising a carrier and a module obtained according to claim 1 fixed to the carrier, characterized in that it comprises the following steps:
forming a carrier with a connection end of the second circuit, said connection end being accessible in/on said carrier,
-transferring the module onto said carrier, the first circuit of the module being connected to said connection terminals of said second circuit.
12. The method of claim 11,
the step of connecting the modules to said connection terminals is performed during the fixing of the modules on a carrier, the electrical interconnection elements or points of the modules connecting said connection terminals of said carrier.
13. A method according to claim 12, including the step of placing a conductive material over the connection terminals or traces.
14. A method according to claim 11, wherein the interconnection elements are held in place over or along an interconnection zone prior to transferring the module onto the carrier.
15. The method of claim 14, wherein the interconnection elements are held in place by bonding, performed via an insertion adhesive of the module or by hot pressing or thermal bonding on a bonding surface of the module.
16. A method as claimed in claim 11, further comprising the step of placing a conductive material on the connections or traces prior to transferring the module onto the carrier.
17. The method of claim 11, wherein the second circuit comprises an antenna or a display or a keyboard or a switch.
18. An electronic chip module comprising:
-a metallization and an integrated circuit chip, the metallization being accessible from a first side of the metallization, the integrated circuit chip being disposed from a second side of the metallization opposite to the first side,
-an electrical interconnection element, distinct from the metallization, directly connected to the chip and disposed from a second side of the metallization,
characterized in that the electrical interconnection element is realized on a single-sided metallization module.
19. The electronic chip module of claim 18, comprising an electrical contact surface accessible on a first side of a dielectric substrate and an integrated circuit chip on a side of a second side opposite the first side,
characterized in that the module comprises electrical interconnection elements connected to the chips and extending over/along the second side of the substrate.
20. The module of claim 18, wherein
The chip is at least partially encapsulated by an encapsulating material and/or an adhesive, and at least a portion of the interconnect element is not encapsulated by the encapsulating material and/or the adhesive.
21. A device comprising the module of claim 18.
22. A method of manufacturing an electronic chip module, the electronic chip module comprising:
-a metallization and an integrated circuit chip, the metallization being accessible from a first side of the metallization, the integrated circuit chip being disposed from a second side of the metallization opposite to the first side,
-an electrical interconnection element, different from the metallizations, directly connecting the chip to at least one of the metallizations and directly connecting the at least one of the metallizations to at least another one of the metallizations and being disposed from a second side of the metallizations,
wherein the method comprises implementing the electrical interconnect element on a single-sided metallization module.
CN201680004744.8A 2015-02-20 2016-02-09 Method for manufacturing a single-sided electronic module comprising an interconnection zone Active CN107111779B (en)

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CA2968070C (en) 2021-05-11
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EP3059698A1 (en) 2016-08-24
US10282652B2 (en) 2019-05-07
JP2019071435A (en) 2019-05-09
US20170372186A1 (en) 2017-12-28
EP3869409A1 (en) 2021-08-25
KR20170081693A (en) 2017-07-12
JP2018505553A (en) 2018-02-22
WO2016131682A1 (en) 2016-08-25
PL3059698T3 (en) 2021-10-25
CN107111779A (en) 2017-08-29
ES2867102T3 (en) 2021-10-20
EP3059698B1 (en) 2021-03-31
CA2968070A1 (en) 2016-08-25
BR112017015014A2 (en) 2018-01-23
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AU2016221971B2 (en) 2019-01-31
JP6756805B2 (en) 2020-09-16

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