EP1573602A1 - Nested design approach - Google Patents
Nested design approachInfo
- Publication number
- EP1573602A1 EP1573602A1 EP02795945A EP02795945A EP1573602A1 EP 1573602 A1 EP1573602 A1 EP 1573602A1 EP 02795945 A EP02795945 A EP 02795945A EP 02795945 A EP02795945 A EP 02795945A EP 1573602 A1 EP1573602 A1 EP 1573602A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- substrate
- master
- subset
- netlist
- master substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2113/00—Details relating to the application field
- G06F2113/18—Chip packaging
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5382—Adaptable interconnections, e.g. for engineering changes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
Definitions
- the present invention generally relates to chip package designs and more
- the packages protect the chip from environmental degradation and form electrical power and signal connections to the printed circuit board.
- the chips generally
- packages that have a master substrate and at least one subset substrate of the master substrate.
- the subset substrate is a portion of the master substrate and has an identical pin out pattern as
- the subset substrate has identical internal net lists as that portion of the master substrate.
- the subset substrate is adapted to accommodate a smaller
- the master substrate is the largest substrate in the menu.
- the invention also prepares a menu of chip packages. The invention selects a master substrate
- the master design represents the largest possible logical netlist and largest
- netlist is not changed or revised in any way except that programmatic (e.g., from the
- the invention designs the substrate with the largest
- the subset netlists can be delivered to the customer much more quickly
- Figure 1 is a schematic diagram of different ball grid array patterns which
- FIGS 2A and 2B are schematic diagrams of the BSM assignments of the
- Figures 3A and 3B are schematic diagrams of the die footprint on the TSM of
- Figures 4A and 4B are schematic diagrams of the first internal layer wiring of the V2 power level connections for the chip package using the master netlist and a subset
- Figures 5A and 5B are schematic diagrams of the first internal layer wiring of
- Figures 6A and 6B are schematic diagrams of the first internal layer wiring of
- Figures 7A and 7B are schematic diagrams of the first internal layer wiring of
- Figures 8A and 8B are schematic diagrams of the second internal layer wiring
- Figures 9A and 9B are schematic diagrams of the second internal layer wiring
- Figures 10A and 10B are schematic diagrams of the second internal layer
- FIGs 11 A and 1 IB are schematic diagrams of the third internal layer wiring
- Figures 12A and 12B are schematic diagrams of the third internal layer wiring
- Figures 13A and 134B are schematic diagrams of the second internal layer
- Figures 14A and 14B are schematic diagrams of the BSM array pattern for the
- the invention reduces the amount of design time and
- the invention designs the wiring connections of a package to allow that package to be used generically with a wide variety of semiconductor
- the invention creates a master (or super-substrate) design the of the largest substrate
- the invention represents
- the substrate at the bottom surface metallurgy (BSM) pads
- the substrate is predetermine for a menu of substrates.
- the pattern of the BSM pads is pre-assigned for all
- netlists, and the physical topology of the I/O support the logical deletion of unneeded nets for subordinate packages.
- the outermost I/O at the TSM plane remains the outermost row at the BSM plane (thus, the
- the master substrate has a size of 42.5 X 42.5 mm.
- the master substrate has a size of 42.5 X 42.5 mm.
- Figure 1 illustrates a number of subsets of the master substrate (shown in different scaling)
- the substrate could comprise ceramic, organic, plastic, semiconductor, etc.
- Figures 2A and 2B show internal wiring net lists within chip packages
- substrate shown in Figure 2A is substantially larger and would be useful with a substantially larger chip than the substrate shown in Figure 2B.
- the package of Figure 2B can be designed
- a master or super-substrate e.g., largest supportable netlist for the chip
- Figures 3A-14B represent the various layers within two different substrates
- the electrical connections and wiring positions are identical for the master and the subset except that the subset does not include the peripheral region 30 that is
- the master design represents the largest possible logical netlist and largest
- netlist is not changed or revised in any way except that programmatic (e.g., from the
- the subset chip package (B) is derived simply by the deletion of wiring on each layer
- the invention discloses a hierarchical system of congruent logical and
- topological coherence chip package that has a master substrate and at least one subset substrate of the master substrate.
- the master substrate has the largest logical and physical
- the subset substrate is derived by programmatic
- Congruent chip packages mean that for
- the invention designs the substrate with the largest
- the subset netlists can be delivered to the customer much more quickly
Abstract
Description
Claims
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2002/040671 WO2004061726A1 (en) | 2002-12-18 | 2002-12-18 | Nested design approach |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1573602A1 true EP1573602A1 (en) | 2005-09-14 |
EP1573602A4 EP1573602A4 (en) | 2009-08-26 |
Family
ID=32710256
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP02795945A Withdrawn EP1573602A4 (en) | 2002-12-18 | 2002-12-18 | Nested design approach |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1573602A4 (en) |
JP (1) | JP4700967B2 (en) |
CN (1) | CN1695149A (en) |
AU (1) | AU2002360668A1 (en) |
WO (1) | WO2004061726A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006202977A (en) * | 2005-01-20 | 2006-08-03 | Sony Corp | Substrate and manufacturing method thereof, and semiconductor package and manufacturing method thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5608638A (en) * | 1995-02-06 | 1997-03-04 | Advanced Micro Devices | Device and method for automation of a build sheet to manufacture a packaged integrated circuit |
US5777383A (en) * | 1996-05-09 | 1998-07-07 | Lsi Logic Corporation | Semiconductor chip package with interconnect layers and routing and testing methods |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5953236A (en) * | 1995-10-31 | 1999-09-14 | Vlsi Technology, Inc. | Method and apparatus for implementing engineering change orders in integrated circuit designs |
JPH10150120A (en) * | 1996-11-19 | 1998-06-02 | Denso Corp | Printed wiring board, bga type lsi package and electronic device |
US6297565B1 (en) * | 1998-03-31 | 2001-10-02 | Altera Corporation | Compatible IC packages and methods for ensuring migration path |
JP3751762B2 (en) * | 1998-12-08 | 2006-03-01 | 株式会社東芝 | Semiconductor device manufacturing method and original plate |
-
2002
- 2002-12-18 WO PCT/US2002/040671 patent/WO2004061726A1/en active Application Filing
- 2002-12-18 AU AU2002360668A patent/AU2002360668A1/en not_active Abandoned
- 2002-12-18 CN CNA02829968XA patent/CN1695149A/en active Pending
- 2002-12-18 EP EP02795945A patent/EP1573602A4/en not_active Withdrawn
- 2002-12-18 JP JP2004564625A patent/JP4700967B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5608638A (en) * | 1995-02-06 | 1997-03-04 | Advanced Micro Devices | Device and method for automation of a build sheet to manufacture a packaged integrated circuit |
US5777383A (en) * | 1996-05-09 | 1998-07-07 | Lsi Logic Corporation | Semiconductor chip package with interconnect layers and routing and testing methods |
Non-Patent Citations (1)
Title |
---|
See also references of WO2004061726A1 * |
Also Published As
Publication number | Publication date |
---|---|
AU2002360668A1 (en) | 2004-07-29 |
JP4700967B2 (en) | 2011-06-15 |
JP2006511954A (en) | 2006-04-06 |
WO2004061726A1 (en) | 2004-07-22 |
EP1573602A4 (en) | 2009-08-26 |
CN1695149A (en) | 2005-11-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20050616 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LI LU MC NL PT SE SI SK TR |
|
AX | Request for extension of the european patent |
Extension state: AL LT LV MK RO |
|
DAX | Request for extension of the european patent (deleted) | ||
RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: WALLING, R., PAUL Inventor name: PAPAE, A., KENNETH Inventor name: KLINE, ERIC Inventor name: FRANKEL, L., JASON Inventor name: CRANMER, S., MICHAEL Inventor name: COLE, S., MARIE Inventor name: BHATIA, S., HARSARAN |
|
A4 | Supplementary search report drawn up and despatched |
Effective date: 20090723 |
|
17Q | First examination report despatched |
Effective date: 20110406 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 20130813 |