Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/39—Circuit design at the physical level
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
  • H10W70/65—Shapes or dispositions of interconnections
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2113/00—Details relating to the application field
  • G06F2113/18—Chip packaging
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
  • H10W70/641—Adaptable interconnections, e.g. fuses or antifuses

Definitions

• the present invention generally relates to chip package designs and more
• the packages protect the chip from environmental degradation and form electrical power and signal connections to the printed circuit board.
• the chips generally
• packages that have a master substrate and at least one subset substrate of the master substrate.
• the subset substrate is a portion of the master substrate and has an identical pin out pattern as
• the subset substrate has identical internal net lists as that portion of the master substrate.
• the subset substrate is adapted to accommodate a smaller
• the master substrate is the largest substrate in the menu.
• the invention also prepares a menu of chip packages. The invention selects a master substrate
• the master design represents the largest possible logical netlist and largest
• netlist is not changed or revised in any way except that programmatic (e.g., from the
• the invention designs the substrate with the largest
• the subset netlists can be delivered to the customer much more quickly
• Figure 1 is a schematic diagram of different ball grid array patterns which
• FIGS 2A and 2B are schematic diagrams of the BSM assignments of the
• Figures 3A and 3B are schematic diagrams of the die footprint on the TSM of
• Figures 4A and 4B are schematic diagrams of the first internal layer wiring of the V2 power level connections for the chip package using the master netlist and a subset
• Figures 5A and 5B are schematic diagrams of the first internal layer wiring of
• Figures 6A and 6B are schematic diagrams of the first internal layer wiring of
• Figures 7A and 7B are schematic diagrams of the first internal layer wiring of
• Figures 8A and 8B are schematic diagrams of the second internal layer wiring
• Figures 9A and 9B are schematic diagrams of the second internal layer wiring
• Figures 10A and 10B are schematic diagrams of the second internal layer
• FIGs 11 A and 1 IB are schematic diagrams of the third internal layer wiring
• Figures 12A and 12B are schematic diagrams of the third internal layer wiring
• Figures 13A and 134B are schematic diagrams of the second internal layer
• Figures 14A and 14B are schematic diagrams of the BSM array pattern for the
• the invention reduces the amount of design time and
• the invention designs the wiring connections of a package to allow that package to be used generically with a wide variety of semiconductor
• the invention creates a master (or super-substrate) design the of the largest substrate
• the invention represents
• the substrate at the bottom surface metallurgy (BSM) pads
• the substrate is predetermine for a menu of substrates.
• the pattern of the BSM pads is pre-assigned for all
• netlists, and the physical topology of the I/O support the logical deletion of unneeded nets for subordinate packages.
• the outermost I/O at the TSM plane remains the outermost row at the BSM plane (thus, the
• the master substrate has a size of 42.5 X 42.5 mm.
• the master substrate has a size of 42.5 X 42.5 mm.
• Figure 1 illustrates a number of subsets of the master substrate (shown in different scaling)
• the substrate could comprise ceramic, organic, plastic, semiconductor, etc.
• Figures 2A and 2B show internal wiring net lists within chip packages
• substrate shown in Figure 2A is substantially larger and would be useful with a substantially larger chip than the substrate shown in Figure 2B.
• the package of Figure 2B can be designed
• a master or super-substrate e.g., largest supportable netlist for the chip
• Figures 3A-14B represent the various layers within two different substrates
• the electrical connections and wiring positions are identical for the master and the subset except that the subset does not include the peripheral region 30 that is
• the master design represents the largest possible logical netlist and largest
• netlist is not changed or revised in any way except that programmatic (e.g., from the
• the subset chip package (B) is derived simply by the deletion of wiring on each layer
• the invention discloses a hierarchical system of congruent logical and
• topological coherence chip package that has a master substrate and at least one subset substrate of the master substrate.
• the master substrate has the largest logical and physical
• the subset substrate is derived by programmatic
• Congruent chip packages mean that for
• the invention designs the substrate with the largest
• the subset netlists can be delivered to the customer much more quickly

Landscapes

• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Evolutionary Computation (AREA)
• Geometry (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Design And Manufacture Of Integrated Circuits (AREA)

Applications Claiming Priority (1)

Publications (2)

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Family Applications (1)

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Citations (2)

Family Cites Families (4)

• 2002
  • 2002-12-18 JP JP2004564625A patent/JP4700967B2/en not_active Expired - Fee Related
  • 2002-12-18 EP EP02795945A patent/EP1573602A4/en not_active Withdrawn
  • 2002-12-18 CN CNA02829968XA patent/CN1695149A/en active Pending
  • 2002-12-18 WO PCT/US2002/040671 patent/WO2004061726A1/en not_active Ceased
  • 2002-12-18 AU AU2002360668A patent/AU2002360668A1/en not_active Abandoned

Patent Citations (2)

Non-Patent Citations (1)

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