EP1559106A2 - Memoire magnetique - Google Patents

Memoire magnetique

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Publication number
EP1559106A2
EP1559106A2 EP03809367A EP03809367A EP1559106A2 EP 1559106 A2 EP1559106 A2 EP 1559106A2 EP 03809367 A EP03809367 A EP 03809367A EP 03809367 A EP03809367 A EP 03809367A EP 1559106 A2 EP1559106 A2 EP 1559106A2
Authority
EP
European Patent Office
Prior art keywords
layer
magnetic
fms
fmf
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03809367A
Other languages
German (de)
English (en)
Inventor
Carsten Heide
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BTG International Ltd
Original Assignee
BTG International Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/278,005 external-priority patent/US6639830B1/en
Priority claimed from US10/278,008 external-priority patent/US6775183B2/en
Application filed by BTG International Ltd filed Critical BTG International Ltd
Publication of EP1559106A2 publication Critical patent/EP1559106A2/fr
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/10—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having two electrodes, e.g. diodes or MIM elements

Definitions

  • the invention relates to a magnetic memory cell and a memory comprising at least two magnetic memory cell.
  • Magnetic random access memories have been proposed due to their non-volatile nature. Unlike dynamic random access memory (DRAM) cells, non-volatile memory cells such as MRAM cells do not require complex circuitry for perpetual electronic refreshing of the stored information.
  • the first of such MRAMs were based on magnetic multi-layer structures, deposited on a substrate.
  • US Patent No. 5,343,422 discloses a structure in which two layers of ferromagnetic material are separated by a layer of nonmagnetic metallic conducting material.
  • One of the magnetic materials called the ferromagnetic fixed layer (FMF)
  • FMF ferromagnetic fixed layer
  • the other magnetic layer called the ferromagnetic soft layer (FMS)
  • FMS ferromagnetic soft layer
  • the magnetic moment of this ferromagnetic soft layer is free to change direction between parallel and anti-parallel alignment relative to the easy-axis, and as a consequence, also relative to the magnetic moment of the ferromagnetic fixed layer on application of an external magnetic field.
  • the state of the storage element represents a logical "1" or "0" depending on whether the directions of the magnetic moments of the magnetic layers are in parallel or anti-parallel alignment, respectively. Because the resistance of the storage element is different for different mutual orientations of the magnetic moments, the structure acts as a spin valve. It thus allows the sensing of the state of the storage element by measuring the differential resistance DR/R with a current, where DR is the difference in resistance of the storage element for two different states of relative orientation of the magnetic moments, and R is the total resistance of the structure in the lower resistance state.
  • Switching between these orientations can be achieved by passing write currents in the vicinity of the FMS, usually by using write lines which run past the layered structure on either side. These write currents, which do not pass through the layered structure itself, induce a magnetic field at the location of the FMS which alters the orientation of the FMS, if it is stronger than the coercive field HC of the FMS.
  • the state of the cell disclosed in US 6,072,718 is written by sending simultaneously a current through the word and bit line crossing at the location of the cell. Each of these currents causes a magnetic field at the location of the memory cell. As the word lines and the bit lines are pe ⁇ endicular to each other, the orientations of the magnetic fields caused by the currents at a crossing point of a bit line and a word line are perpendicular, too.
  • One of the magnetic fields the so called hard-axis field, extends parallel to the magnetic hard-axis of the ferromagnetic soft layer, while the other one of the magnetic fields, the so called easy-axis field, extends parallel to the magnetic easy- axis of the ferromagnetic soft layer.
  • the hard-axis field which stays perpendicular on the magnetic moment of the ferromagnetic soft layer, is applied to the ferromagnetic soft layer in order to move the magnetic moment out of its actual orientation and the easy-axis field is used to set the new orientation of the magnetic moment with respect to the easy-axis of the ferromagnetic soft layer.
  • a magnetic storage device which comprises a first and a second ferromagnetic layer and a tunnel barrier which is disposed between both ferromagnetic layers.
  • the first ferromagnetic layer is a ferromagnetic fixed layer whereas the second ferromagnetic layer is a ferromagnetic soft layer which can change the orientation of its magnetic moment.
  • the device can be written directly by applying a voltage across the cell which can switch the orientation of the magnetic moment of the ferromagnetic soft layer with respect to the ferromagnetic fixed layer.
  • the switching is effected by means of an induced exchange interaction between the ferromagnetic fixed layer and the ferromagnetic soft layer related to spin-polarised electrons tunnelling through the tunnelling barrier. Since the addressing of the cells in the write process is direct, array wide selectivity is achieved.
  • the tunnel barrier has to be as thin as possible. Because the tunnelling current increases exponentially with decreasing thickness of the tunnelling layer, local variations due to the manufacturing process become particularly pronounced for thin barriers. The less uniform the current distribution within the cell, the higher the total current has to be to create a strong enough excitation throughout the entire ferromagnetic soft layer. However, a too strong a current will eventually break the tunnel junction. Therefore, in GB 2 343 308 materials for the tunnelling layer have been proposed with a low energy barrier. Nevertheless, from a manufacturing point of view, there is still a very strong a focus on the quality of the manufacturing process.
  • the object is achieved by a magnetic memory cell comprising
  • FMF ferromagnetic fixed
  • FMS ferromagnetic soft
  • said first intermediate layer is adapted to allow a spin-polarized write current to pass between said first FMF layer and said FMS layer, said write current having an amount sufficient to change a relative orientation of said first and third magnetic moments
  • said second intermediate layer is adapted to influence the resistance between said second FMF layer and said FMS layers at a predetermined read voltage in dependence on a relative orientation of said second and third magnetic moments, said read voltage creating a spin-polarized current amount lower than said write current amount, and wherein said first and second magnetic moments are in a predetermined parallel or antiparallel alignment relative to each other.
  • the memory cell of the invention combines the benefits of known types of magnetic memory cells, while eliminating their drawbacks.
  • the memory cell according to the invention comprises two cell sections: a first cell section has the first FMF layer, the FMS layer, and the first intermediate layer between the first FMF layer and the FMS layer.
  • a second cell section includes the second FMF layer, the FMS layer, and the second intermediate layer between the second FMF layer and the FMS layer.
  • a ferromagnetic fixed layer is a layer with a coercive field high compared to that of a ferromagnetic soft layer.
  • the cell sections provide different main functionalities in the memory cell of the invention.
  • the first cell section primarily serves for writing the cell.
  • Writing means changing the relative orientation of the magnetic moments of the first and third magnetic moments, that is, of the first FMF layer and the FMS layer. It will be explained below how writing of the memory cell can be accomplished.
  • the second cell section primarily serves for reading the cell. Reading, in the current context, means ascertaining the relative orientation of the second and third magnetic moments. Since the relative orientation of the magnetic moments of the first and second FMF layers is fixed in the memory cell of the invention, knowing the relative orientation of the second and third magnetic moments implies the knowledge of the relative orientation of the first and third magnetic moments. Therefore, the state of the memory cell as written with the aid of the first cell section can be determined from a measurement of the relative mutual orientation of the second and third magnetic moments in the second cell section.
  • this FMS layer is shared by the first and second cell sections. Sharing an FMS layer in this context means that the respective layer is used in the writing as well as in the reading process.
  • each cell section preferably has one FMS layer. It is important that, in an embodiment comprising more than one FMS layer, the FMS layers are mutually coupled by a magnetostatic interaction. This coupling effects an antiparallel alignment of the orientation of the FMS layers of the first cell section and the second cell section. This coupling is accomplished by providing a FMS layer in the first cell section that has a magnetic moment sufficiently high to impose on the magnetic moment of the FMS layer in the second cell section, given a distance between the two FMS layers. A lower magnetic moment in the FMS layer in the first cell section is needed for a smaller distance between the FMS layers. Thus, both parameters can be adjusted to achieve an optimized cell design. However, as a boundary condition, the magnetic moment of the FMS layer in the first cell section has to be small enough to allow changing this magnetic moment with the aid of the writing current in the first cell section.
  • the FMS layer in the first cell section is used for writing the memory cell.
  • Writing the FMS layer in the first cell section implies writing the second FMS layer in the second cell section due to the magnetostatic coupling of these two layers. Therefore, the magnetic moment of the FMS layer in the second cell section always reflects the information contained in the magnetic moment of the FMS layer of the first cell section of the memory cell of the invention.
  • An MTJ cell section is used to read the state of the MTJ cell section, i.e., to ascertain the relative orientation of the magnetic moments of the ferromagnetic fixed and soft layers of magnetic memory cell.
  • the coupling between the cell sections makes sure that both cell sections share the same state. Sharing the same state means that there is a unequivocal relation between the relative orientation of the magnetic moments.
  • a first embodiment wherein respective extensions of said first FMF layer, said first intermediate layer, and said FMS layer in a direction pe ⁇ endicular to the layer planes, as well as the respective materials of these layers are such as to allow a change of an orientation of said first and third magnetic moments relative to each other with the aid of a current of at least said writing current amount.
  • a second embodiment wherein respective extensions of said second FMF layer, said second intermediate layer, and said FMS layer in a direction pe ⁇ endicular to the layer planes, as well as the respective materials of these layers are such as to form, given a predetermined writing voltage applied across these layers, a low ohmic resistance if the second and third magnetic moments are in parallel alignment, and to form a high ohmic resistance if the second and third magnetic moments are in antiparallel alignment.
  • a third embodiment wherein said second FMF layer, said second intermediate layer, and said FMS layer form a magnetic tunnel junction.
  • a fourth embodiment comprising a current selection element adapted to allow a current of up to at least a predetermined writing current amount to pass across the first FMF, the first intermediate layer and the FMS layer in directions pe ⁇ endicular to the layer planes, and a reading current amount to pass across the first second FMF layer, the second intermediate layer and the FMS layer in one direction pe ⁇ endicular to the layer planes at a predetermined reading voltage.
  • a fifth embodiment comprising a first FMS layer and a second FMS layer, wherein the magnetic moments of said first and second FMS layers are coupled to each other by magnetostatic interaction.
  • a sixth embodiment wherein said FMS layers are separated by a conductive layer.
  • Figure 1 shows a first embodiment of a memory cell in a cross sectional view
  • FIG. 2 shows a schematic circuit diagram for read/write operations with the memory cell of Figure 1
  • Figure 3 shows a cross sectional view of the first embodiment of a memory cell as to be integrated into a memory cell array
  • Figure 4 shows a circuit diagram for an array of memory cells
  • Figure 5A shows a second embodiment of a memory cell in the form of a two- terminal device
  • Figure 5B shows the second embodiment of a memory cell as to be integrated into a memory cell array
  • Figure 6 A shows a third embodiment of a memory cell.
  • Figure 6B shows the third embodiment of a memory cell as to be integrated into a memory cell array
  • Figure 9 shows a partial, cross sectional view of a further embodiment of a memory cell with a flux closure structure
  • Figure 10 shows a cross sectional view of an array of memory cells with a flux closure structure.
  • Figure 1 shows a first embodiment of a memory cell. Only the basic structure of the memory cell is shown. Especially, not all structural elements needed to integrate the memory cell into an array and to allow writing and reading the cell are shown. This will be addressed below in the context of the description of Figures 2 and 3.
  • the memory cell comprises a first cell section 10 comprising a first ferromagnetic fixed layer 11, a first ferromagnetic soft layer 13 and a non-magnetic layer 15 sandwiched between the first ferromagnetic fixed layer 11 and the first ferromagnetic soft layer 13.
  • the first cell section will hereinafter also be referred to as the GMR cell section.
  • first ferromagnetic fixed layer 11 and the first ferromagnetic soft layer 13 all materials showing a giant magnetoresistance effect may in principle be used. Such materials comprise for example the ferromagnetic elements cobalt (Co), iron (Fe), nickel (Ni) and ferromagnetic alloys containing these elements and iron zirconium (FeZr).
  • the magnetic moment of the first ferromagnetic fixed layer 11 may be pinned by using an anti-ferromagnet or preferably a synthetic antiferromagnetic structure, e.g. a sandwich structure with layers of cobalt and copper.
  • the first ferromagnetic fixed layer 11 should be made such as to have a high coercive field with respect to the first ferromagnetic soft layer 13. This can either be achieved by making the first ferromagnetic fixed layer rather thick with respect to the thickness of the first ferromagnetic soft layer, or by choosing a material having a high intrinsic coercive field (so called hard ferromagnetic material). On the other hand, the first ferromagnetic soft layer should be made from a material having a coercive field which is considerably smaller than the coercive field of the first ferromagnetic fixed layer.
  • nickel, doped ferromagnetic semiconductor materials such as GeMn or GaAsMn (Ge: germanium, Ga: gallium, As: arsenic, Mn: manganese), or a combination of a metallic ferromagnetic material and a ferromagnetic semiconductor material may be chosen for the first ferromagnetic soft layer.
  • Useful combinations of ferromagnetic metallic and ferromagnetic semiconductor materials may be layer stacks like GeMn/NiFe/GeMn, NiFe/GeMn/NiFe, Fe/FeSi Fe (Si: silicon), or Fe(Ni)Zr/CrO2/Fe(Ni)Zr (Zr: zirconium).
  • the first ferromagnetic fixed layer 11 and the first ferromagnetic soft layer 13 are fabricated to have easy axes of magnetisation that align with each other.
  • a material with a particularly high anisotropy such as Co-Pt-Cr alloy (Pt: platinum)
  • Pt platinum
  • the direction of magnetisation of the first ferromagnetic fixed layer 11 can be set by an unidirectional anisotropy as described, for example, in U.S. 5,465,185.
  • the magnetic moment of the first ferromagnetic soft layer 13 may adopt two possible orientations along its easy axis, which define the two states of the memory cell, namely parallel or anti-parallel to the magnetic moment of the first ferromagnetic fixed layer.
  • the first ferromagnetic soft layer 13 may be fabricated to have a low coercivity by giving it an elliptical, a hexagonal or an octagonal shape, or forming tapers at the corners in order to suppress the effects of edge domains.
  • the memory cell further comprises a second cell section 20.
  • the cell section
  • the second cell section 20 has a second ferromagnetic fixed layer 21, a second ferromagnetic soft layer 23, and an insulation layer 25.
  • the second cell section 20 will hereinafter also be referred to as the MTJ cell section.
  • the structure of the MTJ cell section 20, the materials and the respective thickness of the individual layers, are those used in Magnetic-Tunnel- Junction memory cells known in the art.
  • the memory cell is in contact with two bit lines 51 and 52 and one word line 61. It is noted that the names word line and bit line for the lines may be interchanged. The attribution of the names is chosen arbitrarily. This will be described in more detail in the following.
  • the FMF layer 11 of cell section 10 is in contact with the first bit line 51. Between the first bit line 51 and the ferromagnetic fixed layer 11 may be provided an additional contact layer (not shown) which may be made, e.g., of copper or platinum.
  • the FMS layer 13 is in contact with word line 61. An additional contact layer may be provided between FMS layer 13 and word line 61 as well.
  • Word line 61 is, on the other side, also in contact with FMS layer 23 of the second cell section 21. Thus, word line 61 intersects the memory cell between the GMR section 10 and the MTJ section 20. The second bit line is in contact with the FMF layer 21 of the MTJ section 20.
  • Figure 2 shows a circuit diagram for read/write operations with the memory cell of Figure 1.
  • the same reference numerals are used in Figure 2 for elements identical with those of Figure 1.
  • the diagram is an equivalent electrical circuit diagram for explanatory pu ⁇ oses. It does not show the physical structure of the memory cell of Figure 1 nor does it show a circuit used for reading and writing a memory array.
  • GMR cell section 10 and MTJ cell section 20 are shown in Figure 2 as simple blocks. Also shown are the first and second bit lines 51 and 52, and the word line 61. The bit lines 51 and 52 would extend pe ⁇ endicularly to the plane of the diagram of Figure 2 in an actual circuit for a memory array.
  • Voltage source NI is connected with bit line 51 on one side and with word line 61 on the other side.
  • a first closed circuit section is formed comprising a first output port of voltage source NI, bit line 51, GMR cell section 10, word line 61, and a second output port of voltage source VI.
  • Voltage source V2 is connected with bit line 52 on one side and word line 61 on the other side.
  • a second closed circuit section is formed comprising a first output port of voltage source V2, bit line 52, MTJ cell section 20, word line 61 and a second output port of voltage source V2.
  • the second output ports of voltage source NI and N2 share a common electrical potential.
  • a write current is generated in the first circuit section leading through GMR cell section 10 by generating an appropriate voltage between the output ports of voltage source NI.
  • the sign of the voltage to be applied depends on the current state of the cell, i.e., the relative orientation of the magnetic moments of FMF layer 11 and FMS layer 13.
  • the write current leading through the cell can in a further embodiment be supported by a current passing by the cell. This will be explained below with reference to Figure 7.
  • non-polarized electrons are led through the cell section 10 become spin-polarized when passing through the ferromagnetic fixed layer 11 of the GMR cell section 10.
  • the spin of the electrons will be aligned in parallel orientation with respect to the magnetic moment of the ferromagnetic fixed layer after they have passed through this layer.
  • electrons are reflected from the FMF layer, for instance, when a voltage of opposite sign is applied, they will be in anti-parallel alignment with the magnetic moment of the FMF layer.
  • the number of electrons having a spin which is aligned in parallel or anti-parallel, respectively, to the magnetic moment of the ferromagnetic fixed layer 11 is higher than the number of electrons having a spin in anti-parallel or parallel orientation, respectively, with respect to the magnetic moment of the ferromagnetic fixed layer 11.
  • the spin polarisation i.e.
  • the nonmagnetic layer 15 should be thick enough to prevent a permanent coupling of the orientation of the ferromagnetic soft layer's magnetic moment to the ferromagnetic fixed layer's magnetic moment.
  • the non-magnetic layer 15 should, depending on the material, have a thickness of more than about 50 A.
  • the coupling strength between the ferromagnetic fixed layer 11 and the ferromagnetic soft layer is not constant but depends on the thickness of the non-magnetic, preferably conductive layer 15. This dependency results in different ratios Hsat/HAP of the magnetic saturation field Hsat to the magnetic field HAP in case of anti parallel alignment of the magnetic moments of the ferromagnetic layers for different thicknesses of the non-magnetic layer 15.
  • the Hsat/HAP-ratio at about 8 A a first maximum in the Hsat/HAP-ratio occurs. This maximum means that the magnetic moments of both ferromagnetic layers are coupled in anti-parallel orientation.
  • a minimum in the Hsat/HAP-ratio occurs at about 10-15 A, which means that the magnetic moments of the ferromagnetic layers are coupled in parallel orientation. Between the maximum and the minimum, i. e., at about 9 A, no fixed coupling of the magnetic moments of both ferromagnetic layers exists.
  • a thickness between a maximum and a minimum may also be chosen as a thickness for the nonmagnetic layer 15.
  • a thickness for the nonmagnetic layer 15 In the cobalt-copper-system such a thickness would be about 9 A, about 17 A, or about 22 A.
  • the coupling between the magnetic moments of the ferromagnetic layers becomes negligible above a thickness of about 30 A.
  • Correlation of the magnetic states of the GMR cell section 10 and the MTJ cell section 20 is established by a magnetostatic coupling of the FMS layers 13 and 23. Due to the coupling the FMS layers will always have an anti-parallel alignment of their magnetic moments. Thus, when the magnetic moment of the FMS layer 13 is switched, the magnetic moment of the FMS layer 23 will switch by interaction with the new magnetic moment of FMS layer 13.
  • FMS layer 13 may for instance have a higher magnetic moment than FMS layer 23, e.g., by choice of respective layer thickness or layer material.
  • FMS layer 23 may also have a lower coercive field than FMS layer 13 in order to enhance the coupling.
  • the thickness of the word line 61 is kept small enough not to prevent a coupling.
  • care must be taken in the design of the cell structure with respect to the coupling of the FMS layers not to impede the electrical function of the MTJ section in the reading process, which will be described in the following. For instance, a magnetostatic coupling of FMS layer 23 to FMF layer 21 must be avoided.
  • a read voltage is applied in the second circuit section leading through MTJ section 20 by generating an appropriate voltage between the output ports of voltage source V2.
  • the resistance of the MTJ cell section 20 is high or low. Electrons passing the FMF layer 21 are spin-polarized as described above for FMF layer 11. If the magnetic moments of the FMF layer 12 and the FMS layer 23 are in parallel alignment, the potential barrier represented by the insulating (or high-resistance) layer 25 is small enough to allow a substantial amount of spin- polarized electrons to tunnel through this layer. The parallel alignment of the magnetic moments therefore constitutes the low-resistance state of the MTJ cell section 20.
  • Figure 3 shows a cross sectional view of the first embodiment of a memory cell as to be integrated into a memory cell array.
  • the memory cell of this embodiment comprises a first current selection element 30 and a second current selection element 40.
  • Current selection element 30 is inco ⁇ orated in the memory cell between bit line 51 and GMR cell section 10, contacting the FMF layer 11.
  • Current selection element 30 is a Zener diode.
  • the Zener-diode is formed on or in a semiconductor substrate such as silicon (Si) and contains p- and n-doped layers which are e.g. formed of Silicon. A pn-junction is formed between the p-doped and the n-doped layers.
  • the Zener-diode can be operated through a reverse breakdown voltage in the avalanche breakdown region.
  • the Zener-diode accommodates two operational regimes. One regime for the read operation and the other one for write operations where, for writing at least one of the two possible logical states, a reverse voltage has to be applied to the Zener-diode that exceeds the breakdown voltage.
  • any other current control or current selection device with an I-V-characteristics or operational regime similar to a Zener-diode may be used.
  • a double barrier structure, such as a transistor may be used.
  • current selection element 30 has the following characteristics: it allows a current of up to at least a predetermined writing current amount to pass across the GMR cell section between bit line 51 and word line 61, and prohibits a current to pass across the cell in a second direction opposite to said first direction, unless the current amount in the second direction is higher than a predetermined reading current amount, which reading current amount is lower than said writing amount.
  • reading currents are to be passed through MTJ cell section 20 of the addressed cell only, not through GMR cell section 10 nor through other cells in a memory cell array. Also, reading only requires one current direction in the MTJ element.
  • the current selection device 30 should therefore be adapted to prohibit a flow of a reading current though the GMR cell section 10 when the reading current is to be passed through MTJ cell section 20.
  • the second current selection element 40 may be a Zener diode as well. However, it has different current-voltage characteristics than current selection element 30.
  • Current selection device 40 is adapted to allow a current flow in one direction pe ⁇ endicular to the layer planes, such that the current is influenced substantially by the magnetic tunnel junction effect described above. "Substantially" means in this context, that the contrast between the two resistance states of the MTJ section described earlier is high enough to be detected reliably in an electrical measurement.
  • the reading voltage to be applied to the magnetic tunnel junction is low enough to fall within the range of voltages that create a current amount through word line 61 that is below the writing current amount as described above for the current selection device 30.
  • FIG. 4 shows a circuit diagram for an array of memory cells.
  • the memory cells used here are those of the embodiment of Figure 3. Four memory cells are shown. Each is indicated by a rectangle with dashed outlines.
  • Each memory cell has two cell sections.
  • a first cell section indicated by a block labelled G is the GMR cell section 10 of the cell of Figure 3.
  • the GMR cell section is connected to the circuit symbol of a Zener diode, referencing to the current selection element 30.
  • GMR cell section G and the pertaining Zener diode are connected between a write bit line 51' and word line 61'.
  • a second cell section indicated by a block labelled M is the MTJ cell section 20 of Figure 3.
  • the GMR cell section is connected to the circuit symbol of a Zener diode, referencing to the current selection element 40.
  • MTJ cell section M and the pertaining Zener diode are connected between a read bit line 52' and word line 61'.
  • a third memory cell is provided along bit lines 51' and 52', being further connected to a word line
  • a fourth memory cell is provided along word line 62', and is further connected to bit lines 53' and 54'.
  • Word lines 61' and 62' are connected to respective output ports (not shown) of a word line driver Dl.
  • Bit lines 51' through 54' are connected to respective output ports of a bit line driver D2.
  • Addressing for writing or reading from a selected memory cell follows a matrix system well known in the art with one important modification.
  • Word line driver Dl is adapted to provide a predetermined electrical potential at an output port connected to a selected word line. There may be a difference between the potential applied in a writing process and that applied in the reading process. However, preferably the potential applied to the selected word line is the same irrespective of a write or read process.
  • Bit line driver D2 is adapted to provide either a predetermined electrical write potential at a write output port connected to a selected write bit line, or a predetermined electrical read potential at a read output port connected to a selected read bit line.
  • the write potential and read potential are chosen to provide the write current and read voltage described above with reference to Figures 2 and 3.
  • Figure 5A and Figure 5B show a second embodiment of a memory cell in the form of a two-terminal device.
  • Figure 5A shows the general structure of the cell.
  • Figure 5B shows the memory cell as to be integrated into a memory cell array, i.e., provided with current selection elements.
  • the structure of the memory cell is similar to shown of Figure 1 and Figure 3. Therefore, the same reference numerals are used for corresponding layers.
  • the following description concentrates on the structural and operational differences to the earlier embodiment.
  • the memory cell of Figure 5 A has no bit line integrated into the cell structure.
  • the cell comprises a GMR cell section 10 which is connected to a bit line 68, and an MTJ cell section 20, which is connected to a word line 58.
  • a conductive layer 29 sandwiched between the FMS layers 13 and 23 connects the GMR cell section and the MTJ cell section.
  • the conductive layer is not shared by any other memory cell.
  • the word line 61 of the cell of Figure 1 is also a "conductive layer" but is shared by all memory cells connected to it.
  • the magnetic moments of FMF layers 11 and 21 are aligned in parallel.
  • an alternative embodiment has the same structure, but with an antiparallel alignment of the magnetic moments of these layers.
  • the writing operation of the memory cell follows the same general principle as that for the memory cell of Figure 3.
  • a write current is passed through the cell between bit line 68 and word line 58.
  • the current amount and direction are selected to effect a change of the relative orientation of the FMF layer 11 and the FMS layer 13 by switching the orientation of FMS layer 13.
  • FMS layer 13 and FMS layer 23 are magnetostatically coupled so that they will always be in antiparallel alignment.
  • the write current must also pass the MTJ cell section 20.
  • a read voltage is applied to the cell between word line 58 and bit line 68.
  • the read voltage is lower than the write voltage.
  • the read voltage is chosen to have the current flow through the cell influenced strong enough by the spin- valve effect of the magnetic tunnel junction of MTJ cell section 20. This way a contrast between the two alignment states can be detected in an electrical measurement by applying the read voltage across the cell. Since all other layers in the cell are conductive, the influence of these layers on the read current is small in comparison with the influence of the magnetic tunnel junction, so that the of the orientation of the magnetic moments of the further FMF and FMS layers 11 and 13 does not hinder the read operation substantially.
  • current selection element 40' has the following electrical characteristics: It allows a write current amount to flow across the cell at a voltage high enough to cross the tunnel junction.
  • the write current amount necessary has been described above in the context of the description of Figures 1 to 4.
  • the write current amount is allowed to flow in either direction across the cell.
  • the current selection element further allows a read current to flow across the cell in one direction at a predetermined read voltage.
  • the read voltage is smaller than the write voltage. It is chosen small enough to provide read currents, either in a low-resistance or in a high-resistance state of the MTJ cell section, that does not change the orientation of the magnetic moment of the FMS layer 13 or 23.
  • Figures 5A and 5B has the advantage that only one current selection device 40' is needed. Also, this embodiment can rely on known memory circuit architectures for MRAM devices since only one word and bit line are needed per cell.
  • FIG. 6A A further embodiment of the memory cell of the invention will now be described with reference to Figures 6 A and 6B.
  • the reference numerals used are based on those used for embodiments described above where structural elements are identical.
  • the following description focuses on the differences to the embodiment of Figures 5A and 5B.
  • the structure of FMS 13, conductive layer 29, and FMS 23 seen in Figure 5A is replaced by a single FMS layer 27. This way, the GMR cell section and the MTJ cell section share the same FMS layer.
  • a write current is sent through the cell between word line
  • a read voltage is applied between word line 58 and bit line 68. As described above, the read voltage is chosen to have the current flow through the cell influenced strongly enough by the spin- valve effect of the magnetic tunnel junction of MTJ cell section 20.
  • the switching of the cell may be supported by one or more additional currents passing by the location of the memory cell. With such additional currents the current led through the memory cell to perform the direct switching may be reduced. For passing the additional currents by the memory cell, either the word lines and the bit lines or additional lines which are specially provided for this task can be used.
  • Figure 7 shows a schematic timing diagram for an exemplary process of switching the magnetic moment of a ferromagnetic soft layer in a memory cell, in which the different currents used in the switching process are depicted against time. In total, the switching process takes between 0.2 and 5 ns.
  • a current (HTA) generating a hard axis field i.e., a magnetic field in alignment with the direction of the hard axis of the ferromagnetic soft layer, is passed by the memory cell through an appropriate one of the word and the bit line.
  • HTA current
  • the hard axis is pe ⁇ endicular to the soft axis of magnetisation, the magnetic moment of the ferromagnetic soft layer is substantially rotated out of its previous alignment with the easy axis towards an alignment with the hard axis.
  • a fast rising current pulse J ⁇ A which generates a field approximately twice as strong as the coercive field of the ferromagnetic soft layer is switched off, when the magnetic moment of the ferromagnetic soft layer is rotated in plane by approximately 45 to 135 degrees away from its original position. If such a strong current pulse is applied for longer times, i.e. at least for the time it takes to carry out a 180 degree rotation for the magnetic moments of the ferromagnetic soft layer array wide selectivity is lost which is known as the quasi ballistic time limit for magnetization reversal and of the order of 150 ps for a thin NiFe layer.
  • a much weaker current LEA may be passed by the memory cell generating an easy axis field, i.e. a magnetic field in alignment with the direction of the easy axis of the ferromagnetic soft layer.
  • the magnetic field generated by current IEA tends to rotate the magnetic moment of the ferromagnetic soft layer into alignment with the easy axis of the layer.
  • the alignment is either rotated towards a parallel or an anti-parallel state with respect to the easy axis and, as a consequence, with respect to the magnetic moment of the ferromagnetic fixed layer.
  • One of both states represents a logical "0" while the other represents a logical "1".
  • a direct current LD is led through the memory cell to effect the switching of the magnetic moment of the ferromagnetic soft layer into the desired orientation. That is, while IHA serves to disturb the previous alignment at the beginning of the switching sequence, IEA and ID together will effect the switching into the desired new orientation of the magnetic moment.
  • the current IEA and the direct current ID may be set back to zero any time between 0.2 and 5 ns after initiating the switching process, i.e. initiating the direct current and the current IHA. There ought to be some temporal overlap between ID or IEA , respectively, and IHA.
  • the present invention proposes a design for a memory cell array in which the formation of domains can be suppressed without negatively affecting the integration level of the memory cell array.
  • This objective is achieved by providing a flux return structure for closing the flux of the ferromagnetic fixed layers along one dimension and flux closure of the bit and/or write line and ferromagnetic soft layer along a second dimension of MRAM cells, in particular magnetic memory cells as described with respect to Figures 1 to 6.
  • Figure 8 The embodiment shown in Figure 8 is based on that of Figure 3.
  • the view shown in Figure 8 is a cross sectional view.
  • the sectional plane shown here is pe ⁇ endicular to that of Figure 3.
  • the embodiment of Figure 8 comprises a flux closure structure 110 on the side walls of the memory cell.
  • the flux closure structure extends around all side walls of the memory cell.
  • the flux closure structure extends along the side walls in a direction from the bottom to the top of the cell along the FMS layers 13 and 23 and the word line 61 sandwiched between the FMS layers.
  • word line 61 cuts through the flux closure structure 110 in a direction pe ⁇ endicular to the sectional plane of Figure 8.
  • Flux closure structure 110 is made from a soft magnetic insulating material such as a soft ferrite.
  • a thin insulating coating can be provided which is then covered with a soft magnetic metal film such as NiFe (not shown).
  • FIG. 9 A second design providing a flux closure for the bit and/or write line and a ferromagnetic soft layer is shown in Figure 9 along a first direction.
  • a cross section of a part of inventive memory cell of Figure 6B is shown comprising bit line 68, FMF layer 11, conductive layer 15, and FMS layer 27.
  • the memory cell is coated with an insulating magnetic material such as a soft ferrite to allow the flux of the ferromagnetic soft layer 27 and the bit line 68 to close during a write process.
  • a thin insulating coating can be provided which is then covered with a soft magnetic metal film such as NiFe (not shown).
  • FIG. 10 A third design providing a flux closure for the ferromagnetic fixed layer is shown in Figure 10 in a cross sectional view of a memory array along a second direction.
  • Memory cells 301 and 302 are provided based on those shown in Figure 6B.
  • Word and bit lines are omitted in this view.
  • the memory cells are electrically separated from each other by insulating soft magnetic layers 331, 332 and 333 which may be for example of a soft ferrite, and insulating non-magnetic layers 341, 342 and 343 which may be for example made of A12O3.
  • a simplification to the design can be made when using instead of a non-magnetic insulating material the same magnetic material as for layers 331, 332 and 333.
  • Top insulating soft magnetic layer sections 351, 352 and 353 complete the flux closure for the ferromagnetic fixed layers 11 and 21 in memory cells 301 and 302. This means that the orientation of the magnetic moment of the ferromagnetic fixed layer 11 is the same in all memory cells belonging to a row. Also, FMF layers 11 and 21 have an anti-parallel alignment of their respective magnetic moments.
  • a thin insulating coating can be provided which is then covered with a soft magnetic metal film such as NiFe (not shown).

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Semiconductor Memories (AREA)
  • Hall/Mr Elements (AREA)
  • Thin Magnetic Films (AREA)

Abstract

L'invention porte sur une cellule à mémoire magnétique pour MRAM comportant: une première couche ferromagnétique à orientation fixe (FMF) présentant un premier moment magnétique; une deuxième couche FMF présentant un deuxième moment magnétique; au moins une couche faiblement ferromagnétique (FMS) présentant un troisième moment magnétique et disposée entre la première et la deuxième couche FMF; une première couche intermédiaire non magnétique disposée entre la première couche FMF et ladite couche FMS. Ladite première couche intermédiaire permet à un courant d'écriture à polarisation des spins de passer entre ladite première couche FMF et ladite couche FMS, ledit courant d'écriture présentant une intensité suffisante pour modifier l'orientation relative desdits premier et troisième moments magnétiques. Ladite deuxième couche intermédiaire influe sur la résistance entre ladite deuxième couche FMF et lesdites couches FMS pour une tension de lecture prédéterminée en fonction de l'orientation relative du deuxième et du troisième moment magnétique, ladite tension de lecture créant une quantité de courant à polarisation des spins inférieure à ladite quantité de courant d'écriture. Lesdits premier et deuxième moments magnétiques se trouvent l'un par rapport à l'autre dans un alignement parallèle ou antiparallèle prédéterminé.
EP03809367A 2002-10-22 2003-10-22 Memoire magnetique Withdrawn EP1559106A2 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US10/278,005 US6639830B1 (en) 2002-10-22 2002-10-22 Magnetic memory device
US278008 2002-10-22
US10/278,008 US6775183B2 (en) 2002-10-22 2002-10-22 Magnetic memory device employing giant magnetoresistance effect
US278005 2002-10-22
PCT/GB2003/004546 WO2004038723A2 (fr) 2002-10-22 2003-10-22 Memoire magnetique

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EP03809367A Withdrawn EP1559106A2 (fr) 2002-10-22 2003-10-22 Memoire magnetique

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US8004881B2 (en) * 2007-12-19 2011-08-23 Qualcomm Incorporated Magnetic tunnel junction device with separate read and write paths
SG175482A1 (en) * 2010-05-04 2011-11-28 Agency Science Tech & Res Multi-bit cell magnetic memory with perpendicular magnetization and spin torque switching

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US5541868A (en) * 1995-02-21 1996-07-30 The United States Of America As Represented By The Secretary Of The Navy Annular GMR-based memory element
GB2343308B (en) * 1998-10-30 2000-10-11 Nikolai Franz Gregor Schwabe Magnetic storage device
US6611405B1 (en) * 1999-09-16 2003-08-26 Kabushiki Kaisha Toshiba Magnetoresistive element and magnetic memory device
US6269018B1 (en) * 2000-04-13 2001-07-31 International Business Machines Corporation Magnetic random access memory using current through MTJ write mechanism
FR2817999B1 (fr) * 2000-12-07 2003-01-10 Commissariat Energie Atomique Dispositif magnetique a polarisation de spin et a empilement(s) tri-couche(s) et memoire utilisant ce dispositif
FR2817998B1 (fr) * 2000-12-07 2003-01-10 Commissariat Energie Atomique Dispositif magnetique a polarisation de spin et a rotation d'aimantation, memoire et procede d'ecriture utilisant ce dispositif

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AU2003276387A1 (en) 2004-05-13
WO2004038725A3 (fr) 2005-05-06
AU2003274354A1 (en) 2004-05-13
AU2003276387A8 (en) 2004-05-13
WO2004038723A2 (fr) 2004-05-06
WO2004038725A2 (fr) 2004-05-06
WO2004038723A3 (fr) 2005-05-06
EP1556862A2 (fr) 2005-07-27

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