EP1554805A2 - Dispositif logique programmable - Google Patents

Dispositif logique programmable

Info

Publication number
EP1554805A2
EP1554805A2 EP03773569A EP03773569A EP1554805A2 EP 1554805 A2 EP1554805 A2 EP 1554805A2 EP 03773569 A EP03773569 A EP 03773569A EP 03773569 A EP03773569 A EP 03773569A EP 1554805 A2 EP1554805 A2 EP 1554805A2
Authority
EP
European Patent Office
Prior art keywords
logic
logic blocks
blocks
reconfigurable
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP03773569A
Other languages
German (de)
English (en)
Inventor
Christian Siemers
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP1554805A2 publication Critical patent/EP1554805A2/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17752—Structural details of configuration resources for hot reconfiguration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17756—Structural details of configuration resources for partial configuration or partial reconfiguration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks

Definitions

  • the invention relates to a device of programmable logic with a plurality of logic blocks with configurable properties, each of which comprises at least one logic processing unit with function programs and interfaces to the other logic blocks, with at least one input and output unit assigned to the logic blocks and with means for linking the Logic blocks with each other, with the at least one processing unit of another logic block and with the at least one input / output unit.
  • a logic device can be found in US 4,870,302 A.
  • Programmable logic modules from conventional logic devices, such as processors in particular, execute programs that are loaded from a memory.
  • the software to be executed in the form of instruction words is' placed there as a machine instruction.
  • These command words are loaded, analyzed, interpreted and executed in a processing unit. The processing of a single command word triggers a large number of individual actions in the logic device.
  • the basic structure and organization of known digital logic devices, in particular of computers with microprocessors, is based on the concept of the so-called "Von Neumann computer".
  • Its central unit CPU (“Central Processing Unit"), ie its computer core, comprises in its minimal configuration as main components a main memory, a control unit and a processing unit (or arithmetic unit): -
  • the main memory stores command words (program data) and processing data (operant words) and provides these are available upon request. Furthermore, the main Store intermediate and final processing results.
  • Main memories can be implemented by volatile or non-volatile memories.
  • the control unit organizes the order in which command words are processed. It requests command words from the main memory and causes them to be executed in the processing unit. It also analyzes the command words and initiates the delivery of processing data to the processing unit. - The processing unit carries out the operation on the processing data and delivers corresponding result words to the main memory.
  • the processing unit contains a micro-program for each operation, which enables the required transmission paths.
  • the processing unit is controlled by the control unit in the respective type of operation, i.e. to the command to be processed.
  • the central unit is assigned peripheral devices, which can be external memories and input and output devices. The specified main components of the central unit can be physically separated; however, they are usually implemented on a common processor chip with a cache or, for example, an embedded ROM.
  • the linking of its logic blocks relates firstly to the coupling of data outputs to data inputs (routing link) and secondly to the processing of the input data to the output data in the individual logic blocks (logic linkage).
  • the routing link applies both to data that originate from or are led into logic blocks (Logic Elements) and to data that originate from or are routed to I / O pads. In this system of the known embodiment, only data coupling is intended.
  • US Pat. No. 6,333,641 B1 shows a programmable logic device with an array of logic modules or blocks.
  • a connection unit with vertical routing (routing) paths, horizontal routing paths and local routing paths links the logic blocks.
  • An omni (universal) bus (data exchange busbar) is placed over the array, which is linked to the array in such a way that it forms dynamically independent sub-arrays of the logic blocks of variable size, which in turn are connected to the omni-bus.
  • the Linking is established from the outset.
  • data connections are involved, ie an exchange of data.
  • the object of the present invention is therefore to design the programmable logic device with the features mentioned at the outset such that, with a high functional density, a high speed of the PLD can be achieved with simple means.
  • These measures include a reconfigurability of the logic blocks during the entire operation of the logic device in that the linking means additionally have at least one configurable switchover logic block with which a configuration of at least some of the reconfigurable logic blocks themselves and / or their connections to one another and / or their connections with the processing unit and / or their connections with the input / output unit.
  • the configuration can be done at any time, i.e. during the entire, uninterrupted operating period - not just during a start or boot phase.
  • the measures according to the invention thus mean a connection from the switchover logic block to linkage areas and thus to a corresponding configuration thereof. This makes it possible for individual blocks to perform different functions at different times; i.e. their utilization is increased accordingly. Associated with this is a corresponding performance improvement of the entire logic device compared to a microprocessor, or no performance loss in comparison to conventional PLDs.
  • PLDs Like von Neumann processors, PLDs receive two types of information, code and data.
  • the code which basically determines the week of action and is called PLDs configuration or configuration code, is usually loaded before the actual operation and is then immutable during operation.
  • the configuration determines, among other things the connections active in the block.
  • the data can change during operation and thereby also influence the current course of operations. So while the code contains all possible ways, the actual use - this corresponds to the currently running path - is (also) determined by the data.
  • the switching logic block according to the invention also receives code and data.
  • the essence of the invention now exists in controlling the remaining non-rollover PLDs by changing or modifying the code.
  • configurable blocks are connected to one another in such a way that the (runtime-variable) data are interchangeable, for example in the form that data outputs of one block are connected to data inputs of the other are.
  • the outputs of this logic block are at least partially connected to the code area of the configurable logic blocks that is inaccessible in other embodiments during operation.
  • the prior art relates to embodiments in which the configurable logic blocks couple in the data path, but do not have any influence on the code.
  • the switchover logic block can preferably be formed in a level that is different from a level with the reconfigurable logic blocks.
  • a different level of the switchover logic block is understood to mean any level that is not at the same time the level of the reconfigurable logic blocks. This means that the level of the switching logic block can be above, next to or below the level of the reconfigurable logic blocks. These levels can advantageously be at least largely equivalent.
  • the switchover logic block can preferably have at least one status memory which contains information relating to the functions of the individual reconfigurable logic blocks contains, so that the configuration of the selected reconfigurable logic blocks takes place according to the functional information of the current status.
  • FIG. 1 shows the basic structures of four simple, known machine types
  • FIG. 2 shows the basic structure of a so-called "sequential"
  • FIG. 3 the schematic structure of a partially reconfigurable PLD
  • FIG. 4 the schematic structure of a logic device according to the invention.
  • SFSM Simulsion Finite State Machines
  • the model shown here is suitable for defining a sequence of configurations in the PLD, and it is precisely this sequence that can generate a significantly higher functional density (synonymous with drastically reduced costs for production and operation) of a PLD without loss of performance.
  • FSM Finite State Machines
  • An FSM consists of a 6-tuple ⁇ A, X, Y, f, g, an).
  • A ⁇ a 0 , i, ... a M ) is the finite set of states, where a 0 means the starting state.
  • f A x X ⁇
  • A means transition function (Next State Decoder)
  • State coding In the case of synchronous switching mechanisms with synchronized inputs (not for Mealy automat according to FIG. 1d), any codes for the states from Z can be specified. In the Medvedev automaton according to FIG. 1b, however, the codings must match the desired output signals; In the Moore automaton according to FIG. 1c, on the other hand, the codings can be selected such that simplified switching networks for next state decoders (f) and output decoders (g) result.
  • the FSM should be adopted as the basic model.
  • SFSM Sequential Finite State Machine
  • a sequential finite state machine consists of a 5-tuple (B, B 0 , C, V, h).
  • B ⁇ B 0 , ... B ⁇ ) represents a finite set of finite state machines (FSM)
  • B 0 is the start FSM
  • C ⁇ C 0 , ... C ⁇ ) describes a finite set of states for identifying the current FSM.
  • V ⁇ V lr .. V N
  • Vj (vi, ... v L ) i, where Vi € ⁇ 0, 1, - ⁇ . h: B x V — ⁇ B is called FSM transition function (Next FSM decoder).
  • FPGAs Field-Programmable Gate Arrays
  • h u, v, c
  • registers for FSM coding as well as in the reloadable part.
  • the problem here is the loss of performance when reloading. This can be seen from the following example:
  • the popular traffic light as an example for a finite state machine can also be used as an example for a sequential FSM if you think of a night mode.
  • the word mode already shows the way: switching between individual FSMs should be something like a mode change, and day and night mode are mutually exclusive.
  • FSMl now integrates the day traffic light, FSM2 the night traffic light (e.g. yellow flashing for the side streets), and the higher-level sequencer uses a time signal to decide which FSM is to be carried out and which is at rest.
  • the sequencer is implemented as FSM0.
  • Context PLDs (dMC-PLDs) "selected.
  • routing resources are also affected by the switchover, since not only logic, but also connections must lie within the block to be switched over.
  • a PLD block is reconfigurable for the logic device according to the invention Unit consisting of logical processing units with routing resources and interfaces (so-called "routing") to other blocks; this definition corresponds to the partially reconfigurable modules that are common in practice.
  • the definition of this block differs from the usual definition of the logical ones Blocks off.
  • FIG. 3 denotes a partially reconfigurable PLD device or structure
  • this architecture in such a way that - apart from the I / O resources 5 on the outer edge - each PLD block 3A to 3D corresponds to a full CPLD ("Complex PLD") or FPGA.
  • Such architectures already exist, for example " Cypress Delta39k ",” Lattice-Vantis Godfather “architecture; however, they cannot be reconfigured in the operating state of the PLD device.
  • switchover logic block 8 In the dMC-PLD architecture of a logic device 7 according to the invention, which is indicated schematically in FIG. 4, the PLD structure 2 according to FIG. 3 is superimposed by an additional PLD.
  • This extra PLD referred to as switchover logic block 8 is not present in known logic devices and is intended to take over the switchover function h (u, v, c) (cf. FIG. 2). It therefore represents a part of linking means with which at least some of the logic blocks 3A to 3D are configured with one another and / or with the processing unit 4 and / or the input / output unit 5. This means that the outputs in FIG.
  • US Pat. No. 6,011,740 A proposes a method for storing several configuration functions in a shadow RAM, for example as a ring memory and to load the currently required information into a work cell. This procedure guarantees a maximum working speed.
  • a reloadable SRAM cell could also be considered as the actual cell, so that the above-mentioned solution comes into play; however, this means additional effort and possibly a reduction in speed due to the
  • switching means that a choice is made between predetermined programs.
  • Mutual programming can be used for adaptation (evolution) to the respective environment.
  • a simple example can be a digital PLL that adapts a frequency to a master clock by means of runtime effects.

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)

Abstract

L'invention concerne un dispositif logique (7) programmable qui comprend plusieurs blocs logiques (3A à 3D) possédant des caractéristiques configurables, des moyens pour interconnecter ces blocs logiques, ainsi qu'une unité de traitement (4) et une unité d'entrée/sortie (5). Selon l'invention, pour que les blocs logiques (3A à 3D) puissent être reconfigurés pendant le fonctionnement du dispositif logique (7), les moyens d'interconnexion comprennent par ailleurs au moins un bloc logique de commutation (8) configurable permettant de configurer au moins certains des blocs logiques (3A à 3D) reconfigurables mêmes et/ou leur liaison aux autres blocs et/ou à l'unité de traitement (4) et/ou à l'unité d'entrée/sortie (5).
EP03773569A 2002-10-24 2003-10-23 Dispositif logique programmable Ceased EP1554805A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10249676 2002-10-24
DE10249676 2002-10-24
PCT/DE2003/003524 WO2004040766A2 (fr) 2002-10-24 2003-10-23 Dispositif logique programmable

Publications (1)

Publication Number Publication Date
EP1554805A2 true EP1554805A2 (fr) 2005-07-20

Family

ID=32102969

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03773569A Ceased EP1554805A2 (fr) 2002-10-24 2003-10-23 Dispositif logique programmable

Country Status (5)

Country Link
US (1) US7161383B2 (fr)
EP (1) EP1554805A2 (fr)
JP (1) JP4160956B2 (fr)
DE (1) DE10347975B4 (fr)
WO (1) WO2004040766A2 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101198346B1 (ko) * 2003-04-08 2012-11-06 노보 노르디스크 에이/에스 크로마토그래피 고정상의 재생
DE102005005073B4 (de) 2004-02-13 2009-05-07 Siemens Ag Rechnereinrichtung mit rekonfigurierbarer Architektur zur parallelen Berechnung beliebiger Algorithmen
US8612772B1 (en) 2004-09-10 2013-12-17 Altera Corporation Security core using soft key
US8566616B1 (en) * 2004-09-10 2013-10-22 Altera Corporation Method and apparatus for protecting designs in SRAM-based programmable logic devices and the like
US20090128189A1 (en) * 2007-11-19 2009-05-21 Raminda Udaya Madurawe Three dimensional programmable devices
US8327126B2 (en) 2008-08-25 2012-12-04 International Business Machines Corporation Multicore processor and method of use that adapts core functions based on workload execution
US9349288B2 (en) 2014-07-28 2016-05-24 Econolite Group, Inc. Self-configuring traffic signal controller

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6255848B1 (en) * 1999-04-05 2001-07-03 Xilinx, Inc. Method and structure for reading, modifying and writing selected configuration memory cells of an FPGA

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4870302A (en) * 1984-03-12 1989-09-26 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US5212652A (en) * 1989-08-15 1993-05-18 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure
US6346824B1 (en) * 1996-04-09 2002-02-12 Xilinx, Inc. Dedicated function fabric for use in field programmable gate arrays
US6091263A (en) * 1997-12-12 2000-07-18 Xilinx, Inc. Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM
US6011740A (en) * 1998-03-04 2000-01-04 Xilinx, Inc. Structure and method for providing additional configuration memories on an FPGA
JP2002544699A (ja) * 1999-05-07 2002-12-24 モーフィックス テクノロジー インコーポレイテッド プログラム可能なゲートアレイ内で可変サイズの自立的サブアレイをダイナミックに定義するための装置および方法
US20020143505A1 (en) * 2001-04-02 2002-10-03 Doron Drusinsky Implementing a finite state machine using concurrent finite state machines with delayed communications and no shared control signals
US6747478B2 (en) * 2002-07-08 2004-06-08 Viciciv Field programmable gate array with convertibility to application specific integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6255848B1 (en) * 1999-04-05 2001-07-03 Xilinx, Inc. Method and structure for reading, modifying and writing selected configuration memory cells of an FPGA

Also Published As

Publication number Publication date
US20060055421A1 (en) 2006-03-16
DE10347975B4 (de) 2008-10-09
JP2006504344A (ja) 2006-02-02
WO2004040766A3 (fr) 2004-10-28
WO2004040766A2 (fr) 2004-05-13
JP4160956B2 (ja) 2008-10-08
US7161383B2 (en) 2007-01-09
DE10347975A1 (de) 2004-05-13

Similar Documents

Publication Publication Date Title
DE4417575C2 (de) Verbesserte Array-Architektur für programmierbare logische Zellen
EP0948842B1 (fr) Procede pour le transfert dynamique automatique de processeurs a flux de donnees (dfp) ainsi que de modules a deux ou plusieurs structures cellulaires programmables bidimensionnelles ou multidimensionnelles (epga, dpga ou analogues)
DE2755273C2 (fr)
DE102004045527B4 (de) Konfigurierbare Logikschaltungsanordnung
WO2004021176A2 (fr) Procede et dispositif de traitement de donnees
DE19750662A1 (de) Prozessoreinheit für ein datenverarbeitungsgestütztes elektronisches Steuerungssystem in einem Kraftfahrzeug
EP1222739A1 (fr) Circuit integre prediffuse reconfigurable
WO2000017771A2 (fr) Procedes pour configurer un bloc-materiel configurable
DE102005005073B4 (de) Rechnereinrichtung mit rekonfigurierbarer Architektur zur parallelen Berechnung beliebiger Algorithmen
WO2004079564A2 (fr) Processeur a unites de commandes diverses pour des ressources utilisees en commun
DE10347975B4 (de) Einrichtung der programmierbaren Logik
DE2951040C2 (fr)
EP1472616B1 (fr) Elements reconfigurables
EP0231434A1 (fr) Composant fabriqué en technologie des circuits intégrés pour la production de ces derniers
EP1789889B1 (fr) Dispositif informatique a architecture reconfigurable pour la reception d'un automate cellulaire global
EP0875062B1 (fr) Circuit integre con u pour prendre en charge des programmes logiciels
EP3242232B1 (fr) Production optimisee de liste de reseau totale et flux de bits
DE60003847T2 (de) Universelle vorrichtung sowie verfahren und werkzeuge zu ihrer verwendung
EP1116127B1 (fr) Unite commandee par programme
DE4447707B4 (de) Videointerface mit zur Laufzeit rekonfigurierbarer Schaltlogik
DE10238174A1 (de) Verfahren und Vorrichtung zur Datenverarbeitung
DE4447706B4 (de) Partiell zur Laufzeit rekonfigurierbarer Datenflussprozessor
EP0269811A2 (fr) Unité de réseau logique fabriquée en technologie des circuits intégrés pour la construction de ces derniers
WO2022043065A1 (fr) Procédé mis en œuvre par ordinateur et système pour l'exécution dynamique d'un programme d'application par une plateforme
DE2502005C2 (de) Schaltungsanordnung zur Zuordnung von Adressen zu Operationen zwecks Ausführung von Befehlen in einer Datenverarbeitungseinrichtung

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20050422

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR

RBV Designated contracting states (corrected)

Designated state(s): DE FR GB NL

RIN1 Information on inventor provided before grant (corrected)

Inventor name: SIEMERS, CHRISTIAN

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED

18R Application refused

Effective date: 20080124