EP1550207A2 - Appareil, procedes et articles pour le traitement de signaux multibande - Google Patents

Appareil, procedes et articles pour le traitement de signaux multibande

Info

Publication number
EP1550207A2
EP1550207A2 EP03759768A EP03759768A EP1550207A2 EP 1550207 A2 EP1550207 A2 EP 1550207A2 EP 03759768 A EP03759768 A EP 03759768A EP 03759768 A EP03759768 A EP 03759768A EP 1550207 A2 EP1550207 A2 EP 1550207A2
Authority
EP
European Patent Office
Prior art keywords
impedance matching
input signal
matching circuit
amplifying
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03759768A
Other languages
German (de)
English (en)
Inventor
Andrei Grebennikov
Eugene Heaney
Pierce Joseph 19 Heathorton Park NAGLE
Finbarr Joseph Mcgrath
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MA Com Eurotec BV
MA Com Inc
Original Assignee
MA Com Eurotec BV
MA Com Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/307,653 external-priority patent/US7187231B2/en
Application filed by MA Com Eurotec BV, MA Com Inc filed Critical MA Com Eurotec BV
Publication of EP1550207A2 publication Critical patent/EP1550207A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0277—Selecting one or more amplifiers from a plurality of amplifiers

Definitions

  • the invention relates to power amplifiers, and more particularly to multiband power amplifiers.
  • Power amplifiers used in transmitters may be optimized for use in a particular mode and frequency band to maximize efficiency. Such optimization may require the amplifier to be biased in a certain manner. Additionally, impedances usually need to be matched between components within the amplifier and between the amplifier and adjacent components. [0005] Difficulties arise, however, with the demands some communication systems place upon an amplifier. For example, in a W-CDMA or CDMA2000 transmitter, a signal with -a non- constant envelope is traditionally fed through a power amplifier. However, it is difficult to reach optimum levels of amplifier efficiency and linearity: design compromises between the two are often required. Moreover, a wide range of output power is required: typically on the order of 80 dB.
  • a transmitter may be used in CDMA800 (824-849 MHz) and CDMA1900 (1850-1910 MHz) frequency bands.
  • CDMA800 824-849 MHz
  • CDMA1900 1850-1910 MHz
  • dual-band mobile phone transceivers contain two power amplifiers, each operating within a single frequency bandwidth, and each requiring impedance matching.
  • Figure 1 shows one prior art attempt at impedance matching for a dual-band single-stage power amplifier operating in either the 800 MHz or the 1900 MHz bands.
  • a single active device with switching impedance networks 104 and 106 at the input, amplifier 102, bias control 103, voltage source 107 switching impedance network 105 and switching impedance networks 108 and 110 at the output, to provide desired input and output impedances.
  • the need for these switching impedance networks drives up the cost of the device and drives down the efficiency.
  • Amplifier 214 is matched to a first matching circuit 202.
  • a second matching circuit 204 consisting of two separate impedance networks 206 and 208 is tuned to each frequency bandwidth. Two switches 210 and 212 are necessary to this approach. This approach again drives up the cost of the device as well as driving down efficiency.
  • Multistage power amplifiers may be generally desirable as they may provide increased input resistance, increased gain and increased power handling capability, when compared to single stage power amplifiers.
  • implementations to date such as shown in multi stage embodiments of the device seen in Figure 1, have power drain as well as device cost difficulties.
  • the prior art embodiment shown in Figure 1 may be utilized in a multistage power amplifier.
  • the number of components such as impedance networks and switches is increased in 'this type of approach, thus increasing cost, size and inefficiency of the system.
  • At least one amplifying device is provided, with an input impedance matching circuit to compensate for differing input and output signal frequencies.
  • a plurality of amplifying devices may be provided with input impedance matching circuits as well as interstage impedance matching circuits and output matching circuits.
  • Figure 1 depicts a prior art dual-band device.
  • Figure 2 depicts a prior art dual-band device.
  • Figure 3 shows a preferred embodiment.
  • Figure 4 shows a preferred embodiment.
  • Figure 5 shows a preferred embodiment.
  • Figure 6 shows a preferred embodiment.
  • Figure 7 shows a preferred embodiment.
  • Figure 8 shows a preferred embodiment.
  • Figure 9 shows a preferred embodiment.
  • Figure 10 shows a preferred embodiment.
  • Figure 11 shows a preferred embodiment.
  • Figure 12 shows a preferred embodiment.
  • Figure 13 shows a preferred embodiment.
  • Figure 14 shows performance of a preferred embodiment.
  • Figure 15 shows performance of a preferred embodiment.
  • Figure 16 shows performance of a preferred embodiment.
  • the present invention comprises apparatus, methods and articles of manufacture for multiband transmitter power amplification are provided.
  • Figure 3 shows a preferred embodiment.
  • Digital Signal Processor 10 comprises an Analog to Digital Converter 11, which digitizes a multiband input signal by the use of rectangular coordinates or I,Q data. Rectangular to Polar Converter 12 then receives the I,Q data and translates it into polar coordinates.
  • a signal may take the form R, P(sin) and P(cos), where the R coordinate represents the amplitude characteristic of the signal and the P(sin) and P(cos) coordinates represent the phase characteristic of the signal.
  • the amplitude characteristics of the input signal are converted, via converter 13, along path a m , into digital pulses comprising a digital word quantized into bits B 0 to B n . , with a Most Significant Bit ("MSB") to Least Significant Bit (“LSB").
  • MSB Most Significant Bit
  • LSB Least Significant Bit
  • the digital word may be of varying lengths in various embodiments. In general, the longer the word the greater the accuracy of reproduction of the input signal.
  • the digital word provides instruction signals or controls for attenuation and/or amplification, in manner to be described further below. Of course, as is described further below, in other embodiments, a differently composed digital word may be used, as well as other types of derivation and/or provision of amplitude or other signal characteristics.
  • control component lines a m 1 - a m 7 are shown leading away from the converter 13.
  • the number of these control component lines depends, in the preferred embodiments, upon the resolution of the word. In this preferred embodiment, the word has a seven bit resolution.
  • the control component lines are consolidated into a single path a m leading into control components 22a-g.
  • the control component lines are not consolidated and instead feed into the control components individually.
  • a component may also be used, if desired, to feed any desired corrections to the amplitude characteristic through the converter 13, e.g. a lookup table, etc.
  • the phase characteristic travels along path a p .
  • the phase characteristic is first modulated onto a wave by way of Digital to Analog Converter 18 and Synthesizer 20 (which is a Voltage Controlled Oscillator in an especially preferred embodiment.)
  • Synthesizer 20 provides an output wave, which is comprised of the phase information.
  • This output wave has a constant envelope, i.e., it has no amplitude variations, yet it has phase characteristics of the original input wave, and passes to driver 24, and in turn driver lines a p 1 - a 7.
  • a time delay compensation circuit 35 provides synchronization capabilities for the phase and amplitude characteristics.
  • An input impedance matching circuit 40 matches impedance for the phase characteristic with the first amplifying device 36. Preferred embodiments of input impedance matching circuit 40 are further described below. Any input impedance matching circuit of the preferred embodiments should match impedances to compensate for the potentially changing dynamic range (possibly in the range of 80 dB) and concomitant variation in the signal provided to an amplifying device.
  • the output from amplifying device 36 which, it will be recalled, is a phase modulated component of the original input signal, is then fed to interstage impedance matching circuit 41.
  • interstage impedance matching circuit 41 Preferred embodiments of interstage impedance matching circuit 41 are further described below, and match impedance from the varying output signal of amplifying device 36 into transistor array 25a-g. Once the signal has been processed through transistor array 25a-g, as will be described in further detail below, it is combined into line 27, and passes into output impedance matching circuit 42. Preferred embodiments of output impedance matching circuit 42 are further described below.
  • output impedance matching circuit 42 will match impedance between the output of transistor array 25a-g and any load.
  • a band diplexer may be interposed here if the load is an antenna, so as to provide output among the various frequency bands.
  • the phase component it will be recalled, has been output from interstage impedance matching circuit 41. The signal is then split among driver lines a p 1 - a 7 and is fed into current sources 25a- 25g, and will serve to potentially drive current sources 25a- 25g.
  • transistors may be used as current sources 25a- 25g. Additionally, in other embodiments, one or more transistors segmented appropriately may be used as current sources 25a- 25g.
  • Path a m terminates in control components 22a-g.
  • these are switching transistors, and are preferably current sources.
  • Control components 22a-g are switched by bits of the digital word output from the amplitude component and so regulated by the digital word output from the amplitude component. If a bit is "1" or "high,” the corresponding control component is switched on, and so current flows from that control component to appropriate current source 25a-g along bias control lines 23a-g.
  • the length of the digital word may vary, and so the number of bits, control components, control component lines, driver lines, bias control lines, current sources, etc.
  • Current sources 25a-g receive current from a control component if the control component is on, and thus each current source is regulated according to that component.
  • an appropriate control component provides bias current to the current sources, as is described further below, and so the control component may be referred to as a bias control circuit, and a number of them as a bias network.
  • it may be desired to statically or dynamically allocate one or more bias control circuits to one or more current sources using a switching network if desired.
  • Each current source serves as a potential current source, and is capable of generating a current, which is output to current source lines 26a-g respectively.
  • Each current source may or may not act as a current source, and so may or may not generate a current, because it is regulated via the appropriate instruction signal, or digital word value regulating a control component. Activation of any segment, and generation of current from that segment, is dependant upon the value of the appropriate bit from the digital representation of the amplitude component regulating the appropriate control component.
  • the current sources are not an amplifying device or amplifying devices, in the preferred embodiments, rather- the plurality of current sources function as an amplifying device, as is described herein. Indeed, amplification and/or attenuation maybe considered in the preferred embodiments as functions of those embodiments, and so may an amplifying device and/or attenuating device be considered to be an electrical component or system that amplifies and/or attenuates.
  • Figure 4 shows another preferred embodiment.
  • the signal is translated into amplitude and phase components as had been described above with regard to Figure 3.
  • Identically numbered components are as set forth in Figure 3.
  • An input impedance matching circuit 40 matches impedance for the phase characteristic with the first amplifying device 136.
  • the first amplifying device 136 is desirably constructed so as to have an amplification area as a fractional value of the amplification area of transistor array 25a-g.
  • First interstage matching circuit 141 provides impedance matching between first amplifying device and second amplifying device 137.
  • Second amplifying device 137 is desirably constructed so as to have an amplification area as a fractional value of the amplification area of transistor array 25a-g, which may be greater than first amplifying device 136.
  • Second interstage matching circuit 142 provides impedance matching between second amplifying device 137 and transistor array 25a-g. Second interstage matching circuit 142 only provides one half of the desired matching at this stage. The second half is provided by interstage matching circuits 143a-g disposed on the driver lines a 1 - a p 7 respectively. These circuits are desirably high pass or low pass filters.
  • output impedance matching circuits 144a-g provide impedance matching on each of current source lines 26a-g respectively. In other embodiments, output matching circuits such as 144a-g may be not be implemented. Output impedance matching circuit 145 then provides matching to any load, e.g. a diplexer and antenna. Preferred embodiments of output impedance matching circuit 145 are further described below. [0047] As individual transistors in the array are turned on or off, the output impedance matching circuits 144a-g provide a switching impedance matching array to increase the efficiency of the array.
  • FIG. 5 shows another preferred embodiment.
  • Signals of frequency f and or f 2 are input to switch 324.
  • Switch 324 which in this embodiments is a high speed transistor, switches between the input signals to be amplified.
  • a control circuit (not shown) may be used to determine the operating bandwidth.
  • the device 300 functions as a multistage power amplifier, with a plurality of amplifying devices 302, 304 and 306 separated by interstage impedance matching circuits 308 and 310.
  • the amplifying devices are preferably transistors.
  • An input impedance matching circuit 312 matches impedance between the first amplifying device 302 and the input signal.
  • An output impedance matching circuit 314 matches impedance between the last amplifying device 306 and any load.
  • a band diplexer may be interposed here if the load is an antenna, so as to provide output among the various frequency bands. It should be noted as well that in this or other preferred embodiments, it may be desired as well to simultaneously match impedances at different frequencies.
  • Switch 324 is, in this preferred embodiment, a high speed switch or band diplexer. Switch 324 will, depending upon the frequency band, transfer the signal into impedance matching circuit 312. It should be noted that a switch is present in this embodiments in order to minimize impedance effect on the signal from the remainder of the embodiment. That is, without a switched path, "downstream" impedance on an incoming signal might affect the signal's integrity and system performance. However, other embodiments may utilize other or no input switches.
  • Interstage impedance matching circuit 308 matches the impedance between amplifying devices 302 and 304 for the different frequencies.
  • Amplifying device 304 is, in the preferred embodiments, similar to amplifying device 302.
  • interstage impedance matching circuit 310 and amplifying device 306 are, in the preferred embodiments, similar to interstage impedance matching circuit 308 and amplifying device 304 respectively.
  • the values for impedance, capacitance and resistance may be different among the components.
  • a middle stage may be provided with a second impedance matching circuit, as for example, an circuit similar to the output matching impedance circuit of the embodiments of Figures 7-10.
  • inventions of Figures 3 through 5 may be implemented on a semiconductor device where desired, such as an integrated circuit (IC) or an application-specific integrated circuit (ASIC) composition; some examples include silicon (Si), silicon germanium (SiGe) or gallium arsenide (GaAs) substrates.
  • IC integrated circuit
  • ASIC application-specific integrated circuit
  • the output impedance matching circuit 145 of Figure 4 may be, however, depending upon its construction, as is described further below with regard to various embodiments, implemented separately from a IC or ASIC.
  • FIG. 6 a preferred embodiment of an input impedance matching circuit is shown, in the preferred embodiments, this circuit is also used as an interstage impedance matching circuit.
  • the circuit comprises a series RLC circuit, which accepts input in the direction a.
  • This circuit is especially suited for broadband operation (as are the generally preferred embodiments.) Of course, in other embodiments, other circuits may be used, such as a low pass or high pass ladder filter.
  • Figure 7 shows a switching output impedance matching circuit embodiment, which may provide greater efficiency.
  • Capacitors 355, 356 and 357 are DC blocking capacitors; resistors 360 and 361 are desirably large to prevent RF leakage.
  • Transmission line 365 is a less than quarter wave line providing inductive impedance. Due to these additional components, and use of the embodiment in a non linear embodiment as was described above, the components may need to be calibrated preliminarily, which may be done using switches or p-i-n diodes for maximum efficiency.
  • Figure 8 shows another switching output impedance matching circuit embodiment, which may provide greater efficiency.
  • four single switches 380-383 and four capacitors 390-393 match the impedances.
  • Transmission line 395 is a less than quarter wave line providing inductive impedance.
  • Capacitors 390- 393 are matching capacitors.
  • the components may need to be calibrated preliminarily, which may be done using switches or p-i-n diodes for maximum efficiency.
  • switches or p-i-n diodes for maximum efficiency.
  • output impedance matching in this stage uses a parallel-circuit load network.
  • the parallel circuit load network is tuned to specific values for impedance, capacitance and resistance, according to the appropriate values of the remainder of the embodiment.
  • the load network consists of resonant circuit 501, which includes capacitor 501C, resistor 501R (with resistance R) and load 501R2 (with resistance R ⁇ ), parallel short circuited transmission line 502, and quarter wave transmission line 503.
  • Parallel short-circuited transmission line 502 and parallel capacitance 501c provide inductive impedance at a central
  • the inductive impedance of the load network may differ with different frequencies, of course. Generally, it is determined by:
  • optimum load network parameters may be defined by
  • V cc is -the supply voltage
  • P out is the output power
  • Z 0 and ⁇ are characteristic impedance and electrical length of the parallel short circuited transmission line 502, respectively.
  • FIG. 11 Another alternative embodiment is seen in Figure 11. This embodiment is preferably used in broadband embodiments when output impedances are small, on the order of about 5 Ohm. Two L-section transformers 701 and 702 with series transmission lines and parallel capacitances are added to an embodiment such as seen in Figure 11.
  • FIG. 12 A preferred embodiment of a band diplexer comprised of high-pass and low-pass filters is shown in Figure 12. Such an embodiment minimizes any insertion loss in a switched embodiment, such as that shown in Figure 5.
  • High pass filter 1100 comprises inductor 1102 and capacitors 1104 and 1106.
  • Low pass filter 1111 comprises inductors 1108 and 1110 and capacitor 1112.
  • the inductors may be replaced by a short transmission line with high characteristic impedance and the capacitors may be replaced by an open-circuit stub.
  • a band diplexer may be formed with quarter-wave or half- wave transmission lines as shown in Figure 13.
  • the transmission line lengths l ⁇ and / 2 are quarter- wave at 800 MHz to protect the higher frequency path from the lower frequency signal whereas lengths and / 5 are quarter- wave at 1900 MHz to protect the lower frequency path from the higher frequency signal.
  • length 3 is chosen to realize the parallel equivalent circuit with an open-circuit stub, i.e. the overall length + h should be half-wave at 1900 MHz as well as the overall length k + k should be half-wave at 800 MHz.
  • the series transmission lines preferably have 50-Ohm characteristic impedances.
  • one or more notch filters may be used within an output impedance matching circuit or band diplexer, thus further attenuating any undesirable frequencies. For example, suppression of the second harmonic at the 840 MHz bandwidth, (1.68 GHz) is desirable in a CDMA800/CDMA1900 embodiment. This harmonic will be within the power amplifier frequency bandwidth and so should be attenuated. Therefore, a notch filter may be used.
  • Figure 14 shows performance of a multiband, multistage power amplifier device embodiment for small parameter signal S(2,l).
  • a frequency range of 820 to 1910 MHz shows a power gain deviation of approximately 7 dB for this specific frequency.
  • Figures 15 and 16 shows performance of a multiband, multistage power amplifier device embodiment for large signals.
  • Figure 15 shows output power for two signals S 3 and S 4 at
  • Figure 16 shows power added efficiency for two signals S 5 and S 6 at 840 MHz and 1880 MHz (the central bandwidth frequencies of CDMA 800 and CDMA1900 respectively.)
  • Embodiments of the present invention may be used in dual and other multiband architectures.
  • Examples of dual band architectures are GSM900/DCS1800 or
  • CDMA800/CDMA1900 examples of triple band architectures are GSM900/

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Transmitters (AREA)

Abstract

La présente invention concerne un appareil, des procédés et des articles pour une amplification de puissance d'émetteur multibande. Selon cette invention, un ou plusieurs dispositifs d'amplification, dont au moins un peut être une ou plusieurs sources de courant, présentent des impédances adaptées à différentes fréquences d'entrée et de sortie au moyen de divers circuits d'adaptation d'impédance.
EP03759768A 2002-10-08 2003-10-08 Appareil, procedes et articles pour le traitement de signaux multibande Withdrawn EP1550207A2 (fr)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US41690102P 2002-10-08 2002-10-08
US41731302P 2002-10-08 2002-10-08
US417313P 2002-10-08
US10/307,653 US7187231B2 (en) 2002-12-02 2002-12-02 Apparatus, methods and articles of manufacture for multiband signal processing
US307653 2002-12-02
PCT/US2003/031890 WO2004034569A2 (fr) 2002-10-08 2003-10-08 Appareil, procedes et articles pour le traitement de signaux multibande
US416901P 2010-11-24

Publications (1)

Publication Number Publication Date
EP1550207A2 true EP1550207A2 (fr) 2005-07-06

Family

ID=32096826

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03759768A Withdrawn EP1550207A2 (fr) 2002-10-08 2003-10-08 Appareil, procedes et articles pour le traitement de signaux multibande

Country Status (4)

Country Link
EP (1) EP1550207A2 (fr)
JP (1) JP2006515723A (fr)
AU (1) AU2003275490A1 (fr)
WO (1) WO2004034569A2 (fr)

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US7053701B2 (en) * 2003-11-04 2006-05-30 Vice Michael W Power amplifier output stage with multiple power states and improved efficiency
EP1987318B1 (fr) 2006-02-24 2015-08-12 The General Hospital Corporation Procédés et systèmes destinés à réaliser une tomographie par cohérence optique dans le domaine de fourier avec résolution angulaire
JP2008154201A (ja) * 2006-07-07 2008-07-03 Murata Mfg Co Ltd 送信装置
JP2009010484A (ja) * 2007-06-26 2009-01-15 Mitsubishi Electric Corp マルチバンド増幅器
JP5440498B2 (ja) * 2008-06-13 2014-03-12 日本電気株式会社 電力増幅器及びその増幅方法、それを用いた電波送信機
US8170505B2 (en) 2008-07-30 2012-05-01 Qualcomm Incorporated Driver amplifier having a programmable output impedance adjustment circuit
US9143172B2 (en) 2009-06-03 2015-09-22 Qualcomm Incorporated Tunable matching circuits for power amplifiers
US8963611B2 (en) 2009-06-19 2015-02-24 Qualcomm Incorporated Power and impedance measurement circuits for a wireless communication device
JP5257719B2 (ja) * 2009-07-02 2013-08-07 株式会社村田製作所 無線通信用高周波回路及び無線通信機
US8750810B2 (en) * 2009-07-24 2014-06-10 Qualcomm Incorporated Power amplifier with switched output matching for multi-mode operation
US9559639B2 (en) 2009-08-19 2017-01-31 Qualcomm Incorporated Protection circuit for power amplifier
US8072272B2 (en) 2009-08-19 2011-12-06 Qualcomm, Incorporated Digital tunable inter-stage matching circuit

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Also Published As

Publication number Publication date
WO2004034569A2 (fr) 2004-04-22
AU2003275490A1 (en) 2004-05-04
JP2006515723A (ja) 2006-06-01
AU2003275490A8 (en) 2004-05-04
WO2004034569A3 (fr) 2004-06-17

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