Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
  • G09G3/3611—Control of matrices with row and column drivers
  • G09G3/3685—Details of drivers for data electrodes
  • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
• • G—PHYSICS
  • G02—OPTICS
  • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
  • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
  • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
  • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
  • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2320/00—Control of display operating conditions
  • G09G2320/02—Improving the quality of display appearance
  • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2320/00—Control of display operating conditions
  • G09G2320/02—Improving the quality of display appearance
  • G09G2320/0261—Improving the quality of display appearance in the context of movement of objects on the screen or movement of the observer relative to the screen

Definitions

• the present invention relates in general to a method for driving liquid crystal pixels in a liquid crystal display.
• Liquid crystal display panels are commonly known. With reference to Fig. 1, they comprise a matrix of liquid crystal display elements or pixels 10, one of which is illustrated in Fig. 1. Each pixel 10 comprises a liquid crystal cell 11, having one terminal connected to a common back electrode 12, common to aplurality of (usually all) pixels of the liquid crystal display panel, and having another terminal connected to a drain terminal of a pixel drive transistor 13.
• the pixels are arranged according to a matrix of horizontal rows and vertical columns. All of the source electrodes of the drive transistors 13 in one column are connected to a common column electrode or data line 14. All data lines are coupled to corresponding outputs 21 of a data driver or column driver 20.
• All of the gate electrodes of all drive transistors 13 in one row are connected to one common row electrode or gate line 15. All gate lines are connected to corresponding outputs 81 of a gate driver or row driver 80.
• the row driver 80 receives gate pulses PQ from a gate pulse source 90, and provides these gate pulses consecutively to the gate lines in a predetermined order.
• the rows of the display panel are driven successively by applying an appropriate gate pulse to only one of the gate lines at a time. This effectively constitutes a selection of one row of the matrix. As long as this row is selected (duration of gate pulse), the voltages at the data lines 14 as provided by the data driver 20 will determine the amount of light outputted from the corresponding pixel elements 10 in this specific row.
• the row is maintained (driven) during a predetermined line time, as determined by the length of the above-mentioned gate pulse applied to the gate line 15. Subsequently, the next row is selected, and so on, until all rows in the matrix have been selected, after which the sequence continues from- the first row in the matrix. All rows together define one image frame; the time necessary for driving all successive rows such as to display one complete frame will be indicated as the frame period.
• Liquid crystal display panels suffer from problems such as motion blur and kickback.
• Motion blur is the phenomenon of a displayed object becoming blurred to a certain extent when this object is moved across the screen. This phenomenon is due to several causes, including the intrinsic low LC response time and the fact that the pixel capacitance depends on the voltage applied to the cell.
• Kickback is the phenomenon of an undesirable voltage drop occurring across the cell when the gate pulse is removed. This phenomenon is essentially due to parasitic elements present in the Liquid Crystal cell, and its magnitude (in terms of voltage drop) is not constant but depends on the capacity of the cell, which in turn is related to the voltage applied to the cell itself.
• the correction value V corr depends, on the one hand, on the current data source signal V D s as currently provided by the data source 20 and, on the other hand, on the data source signal V DS provided by the data source 20 on the same data line with respect to the same pixel in the previous frame.
• the correction value V COrr (n) in an n-th frame can be written as a function of Vos(n) and V D s(n-l) in accordance with the following formula
• V C orr(n) f(V DS (n); V DS (n-l))
• the function f is a predetermined function of the two variables Vos(n) and V DS ( ⁇ -1).
• the function f may be expressed as an analytical function, or as a table, or in any other suitable manner.
• the function f may depend on specific characteristics of the individual liquid crystal display, as will be clear to a person skilled in the art. In any case, the concept of using such a correction function f is known per se, and, as such, is not the subject of the present invention. Therefore, a more detailed explanation of this function is omitted here.
• Com frame memory 30 is used to store the pixel source signals Vos(n-l) of the previous frame, as functionally illustrated in Fig. 1.
• a frame memory needs to have a memory capacity corresponding to the number of pixels in the liquid crystal display, and is relatively expensive.
• the correction procedure is executed on the basis of a column driver signal V DS ⁇ I-I), which is only an estimation of the data drive voltage actually presented to the liquid crystal cell 11 at the previous frame.
• Fig. 1 illustrates the correction procedure as if it were performed after the column driver; in practice the correction procedure is executed directly in the digital domain, on the data provided to the column driver, as will be clear to a person skilled in the art.
• the invention is defined by independent claims. The dependent claims define advantageous embodiments.
• the present invention uses the intrinsic capacitance C LC of each liquid crystal cell 11 as a pixel memory. In this way, an. additional frame memory is no longer necessary, while furthermore the residual voltage remaining in said intrinsic capacitance C LC after the previous frame is measured for calculating the correction value V corr (n).
• a method for driving a liquid crystal cell comprises the steps of firstly measuring the voltage level remaining in the cell, and secondly driving the cell with a corrected drive signal on the basis of a data source signal Vos(n) from a data source, on the one hand, and the measured cell voltage V d (n-1), on the other hand.
• a liquid crystal display driver circuit comprises sense means for sensing a cell voltage V d (n-1), drive voltage generating means for generating a data drive signal V d (n) on the basis of a current data source signal V ⁇ s(n) supplied by a data source, on the one hand, and the measured cell voltage V d (n-1), on the other hand, drive signal application means for applying the thus generated data drive signal V d (n) to the liquid crystal cell, and control means for controlling the timing of the sense means and the drive signal application means.
• Fig. 1 schematically illustrates a prior-art driver circuit
• Fig. 2 schematically illustrates a liquid crystal display driver circuit according to the present invention
• Fig. 3 is a graph illustrating the timing of drive pulses in an embodiment of a liquid crystal display driver circuit according to the present invention.
• Fig. 4 schematically illustrates an embodiment of a switch controller. DESCRIPTION OF PREFERRED EMBODIMENTS
• Fig. 2 schematically illustrates a circuit 50 for implementing the present invention for one data line 14, i.e. for one pixel 10 in a row. It will, however, be understood that, in a display device, a plurality of circuits 50 as illustrated in Fig. 2 will be provided, one for each data line.
• the circuit 50 has a data signal input 41, a gate signal input 43, and an output 42.
• the data signal input 41 is coupled to an output 21 of the data source 20, providing the current data source signal V ⁇ s(n).
• the output 42 is coupled to the data line 14.
• the data signal input 41 is coupled to a first input of an adder 51 and to a first input of a function calculator unit 52.
• An output of the function calculator unit 52 is coupled to another input of said adder 51, the output of which is coupled to a first switch terminal of a first controllable switch 53.
• a second switch terminal of said first controllable switch 53 is coupled to a data line 14.
• the first controllable switch 53 has two operative states: in a first operative state, the switch 53 is conductive between two terminals, whereas in a second operative state, the switch 53 is non-conductive between two terminals.
• the switch 53 is implemented as a MOSFET.
• the first operative state will hereinafter be indicated as CLOSED and the second operative state will be indicated as OPEN. Selecting one of said two operative states, or switching, takes place under the control of a first switch control signal SCI received at a control terminal.
• a second controllable switch 54 preferably a MOSFET, has one terminal also connected to said data line 14, and has another switch terminal connected to an input of a latch 55, an output of which is connected to a second input of said function calculator unit 52.
• the second controllable switch 54 has a first operative state CLOSED and a second operative state OPEN, switching taking place under the control of a second switch control signal SC2 received at a control terminal.
• a switch controller 60 has two outputs 61, 62 providing the respective switch control signals SCI, SC2 for said two controllable switches 53, 54.
• the switch controller 60 has an input 63 coupled to the gate signal input 43 to receive the gate pulses PQ from the gate pulse source 90.
• the gate pulses are also supplied to gate driver 80.
• An output of the gate driver 80 is connected to the corresponding gate line 15.
• the switch controller 60 is adapted to generate switch control signals SCI, SC2 on the basis of the gate signals received at its input 63, as follows.
• the switch controller 60 first generates at its second output 62 a sense pulse Ps as the second control signal SC2, having a duration of less than the gate pulse PQ.
• the switch controller 60 generates at its first output 61 a drive pulse P D as the first control signal SCI, the drive pulse P D starting substantially when the sense pulse P s ends and ending substantially when the gate pulse P G ends.
• the timing of said three signals is illustrated in Fig. 3, showing the gate pulse PQ, the second control signal SC2 and the first control signal SCI, respectively, as a function of time t.
• Fig. 4 shows a possible implementation of the switch controller 60, in an example where presence of a pulse corresponds to a logical HIGH and absence of a pulse corresponds to a logical LOW.
• a monopulse generator 70 is adapted to generate one pulse having a predetermined duration of less than a predetermined duration of the gate pulse P G , which is known in advance.
• the pulse generator 70 has a first output 72 which is normally LOW and provides a HIGH pulse.
• the pulse generator 70 further has a second output 73 which is normally HIGH and provides a LOW pulse, coupled to a first input of an AND gate 74.
• the second output signal at the second output 73 of the pulse generator 70 is the inverted signal with respect to the first output signal at its first output 72. Therefore, alternatively, the first output 72 of the pulse generator 70 can be coupled to said first input of said AND gate 74 through an inverter.
• the pulse generator 70 is adapted to generate its pulses when a positive edge is received at a trigger input 71 of the pulse generator 70.
• This trigger input 71 is coupled to said input 63 of the switch controller 60 so as to receive the gate signal P G .
• a second input of said AND gate 94 is coupled to said input 63 of the switch controller 60 so as to receive the gate signal PQ.
• the first output 72 of the pulse generator 70 is coupled to said second output 62 of the switch controller 60, and the output of the AND gate 74 is coupled to the first output 61 of the switch controller 60.
• the output of the AND gate 74 is initially LOW, because the gate signal P G is initially LOW.
• the pulse generator 70 will generate at its first output 72 a HIGH pulse, which will be provided as sense pulse Ps at the second output 62 of the switch controller 60.
• the output of the AND gate 74 will remain LOW.
• the output of the AND gate 74 will be HIGH during the remainder of the duration of the gate pulse P G , and this will be supplied as output pulse, i.e. drive pulse PQ, at the first output 61 of the switch controller 60.
• the addressing phase as determined by the length of the gate pulse PQ has effectively been divided into two parts by the switch controller 60, the two parts hereinafter being indicated as “sense phase” and “drive phase".
• the length of the sense phase is determined by the length of the pulse generated by the pulse generator 70
• the length of the drive phase is determined by the length of the output pulse at the first output 61 of the switch controller 60, i.e. the difference of the lengths of the gate pulse PQ and the sense pulse Ps.
• the duration of the sense phase will be less than the duration of the drive phase.
• the first controllable switch 53 is OPEN and the second controllable switch 54 is CLOSED under the control of the sense pulse Ps.
• the voltage remaining in the liquid crystal cell 11 is coupled to the input of the latch 55.
• the function calculating unit 52 now receives at its first input the current data source signal V DS ( ⁇ ) of the current frame, and receives at its second input the residual cell voltage V d (n-1) measured during the sense phase.
• the function calculating unit 52 determines, in a manner known per se, the current correction signal V corr (n), which is added to the current data source signal V DS (H) to provide the current cell drive signal V d (n).
• this current cell drive signal V d (n) is not applied to the cell 11 during the sense phase, because during the sense phase the first controllable switch 53 is OPEN.
• the first controllable switch is CLOSED under the control of the drive pulse P D , so that the current cell drive signal V d (n) is applied to the data line 14, and is thus applied to the liquid crystal cell 11 "selected" by the gate pulses PQ, without being disturbed by the presence of a sense circuit because the second controllable switch 54 is now OPEN.
• the measured residual cell voltage V d (n-1) will be "remembered” by virtue of the latch 55.
• function calculating unit 52 is not essential to the present invention.
• function calculating units are known which receive at their second input a signal which is indicative of the previous cell drive signal Vos(n-l) of the previous frame as an estimation of the current residual cell voltage, this signal being provided by a frame memory.
• the memory function of such a frame memory may be replaced by the memory function of the cell capacitance giving a more accurate value, as described above.
• the function calculating unit could be any type of calculating unit, for instance a suitably programmed hardware calculating device that could be implemented in an analog and/or digital way, programmed to calculate an output function value on the basis of two input values.
• liquid crystal display driver circuit 50 is described as being a unit separate from the data source or column driver 20, it is also possible that the liquid crystal display driver circuit 50 is implemented as an integral part of the data source or column driver 20.
• integrated data source 120 The combination of data source 20 and liquid crystal display driver circuit 50 will hereinafter also be indicated as "integrated data source 120".
• the gate signal input 43 may be an input of integrated data source 120; the output 21 and data signal input 41 will be an internal node of such an integrated data source 120, and output 42 will be an output of such an integrated data source 120.
• the sense means provide a sense means output signal substantially equal to the remaining cell voltage as measured.
• the sense means provide a sense means output signal which differs from the actual cell voltage by a predetermined factor, while the calculating means may be designed to take such a factor into account when calculating the correction value. This is expressed as a sense means output signal representing the remaining cell voltage.

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• Optics & Photonics (AREA)
• Computer Hardware Design (AREA)
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• Control Of Indicators Other Than Cathode Ray Tubes (AREA)
• Liquid Crystal Display Device Control (AREA)

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• 2003
  • 2003-07-10 EP EP03741005A patent/EP1527435A1/en not_active Withdrawn
  • 2003-07-10 AU AU2003281791A patent/AU2003281791A1/en not_active Abandoned
  • 2003-07-10 CN CNA038182238A patent/CN1672188A/zh active Pending
  • 2003-07-10 WO PCT/IB2003/003148 patent/WO2004013835A1/en not_active Ceased
  • 2003-07-10 JP JP2004525659A patent/JP2005534970A/ja not_active Withdrawn
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