EP1518322A1 - Fast cascaded class ab output stage with fet devices - Google Patents

Fast cascaded class ab output stage with fet devices

Info

Publication number
EP1518322A1
EP1518322A1 EP03715264A EP03715264A EP1518322A1 EP 1518322 A1 EP1518322 A1 EP 1518322A1 EP 03715264 A EP03715264 A EP 03715264A EP 03715264 A EP03715264 A EP 03715264A EP 1518322 A1 EP1518322 A1 EP 1518322A1
Authority
EP
European Patent Office
Prior art keywords
fets
output stage
gates
fet devices
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP03715264A
Other languages
German (de)
French (fr)
Other versions
EP1518322B1 (en
Inventor
Alok Govil
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of EP1518322A1 publication Critical patent/EP1518322A1/en
Application granted granted Critical
Publication of EP1518322B1 publication Critical patent/EP1518322B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/34—DC amplifiers in which all stages are DC-coupled
    • H03F3/343—DC amplifiers in which all stages are DC-coupled with semiconductor devices only
    • H03F3/345—DC amplifiers in which all stages are DC-coupled with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H03F3/16—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3217—Modifications of amplifiers to reduce non-linear distortion in single ended push-pull amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
    • H03F3/3001—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor with field-effect transistors
    • H03F3/301—CMOS common drain output SEPP amplifiers
    • H03F3/3011—CMOS common drain output SEPP amplifiers with asymmetrical driving of the end stage

Definitions

  • This invention relates to high voltage and power output circuits, and more particularly, to an improved cascaded configuration for a class AB MOS output stage.
  • High voltage and high power output circuits may be manufactured from bipolar output stages or MOS structures.
  • a typical class AB output stage utilizing MOS structures is shown in Fig. 1.
  • Fig. 1 depicts a cascaded class AB buffer utilizing bipolar transistors and several diodes as shown. Notably, there are four static current paths 201-204, leading to increased power consumption. As stated above, minimization of power consumption is a goal in class AB output stages. Thus, the arrangement of Fig. 1 is suboptimal.
  • Fig. 2 shows a class C Darlington output stage with biasing resistors utilizing
  • Fig. 2 FET technology.
  • the arrangement of Fig. 2 would appear to consume less power than that of Fig. 1 , owing to the fact that there are less current paths.
  • transistors M3 and M4 see the load through biasing resistors Rl and R2.
  • transistors M3 and M4 must be sized properly to prevent slowing down of the circuit. Often, this means utilizing larger transistors, with higher power consumption, than desirable. Thus, the larger transistors can make up for the reduction in current paths, and a relatively high power consuming device still results.
  • crossover distortion In addition to the foregoing power consumption problem, another problem in output stages is that of crossover distortion.
  • a prior art known technique of minimizing crossover distortion is to utilize a feedback loop to cancel such distortion.
  • the implementation of such a feedback loop also results in added power consumption.
  • the present invention includes a circuit having cascaded output stages utilizing three sets of FET devices. Of the three sets of FET devices, in a preferred embodiment, a first set includes four FETs, a second set includes a different four FETs, and a third set includes two FETs. Two of the transistors from the second set and the two transistors from the third set comprise one class AB stage, and the remaining two transistors from the second set and all four transistors from the first set comprise the second class AB stage.
  • the two stages are cascaded in a manner that reduces the required size for the transistors as well as eliminating crossover distortion. The arrangement avoids such crossover distortion without the need for a feedback loop, thereby eliminating the additional components that would otherwise be required and also minimizing power dissipation.
  • the circuit has the further advantage of minimizing current paths, and thus power consumption, while permitting smaller size transistors to be used, even to drive relatively highly capacitive output loads. Further advantages of the present invention will become clear from the following detailed description and drawings.
  • Fig. 1 shows a exemplary prior art arrangement
  • Fig. 2 depicts an additional prior art arrangement having the drawback of relatively high power consumption
  • Fig. 3 shows an exemplary embodiment of the present invention utilizing ten FET devices.
  • Fig. 3 shows an exemplary embodiment of the present invention utilizing ten FET devices. It is understood that the particular transistors utilized are not critical to the present invention, and that other types of active devices may be utilized.
  • the exemplary embodiment of Fig. 3 comprises four FET devices 601-604 connected to the input power source.
  • the source of FET 601 is connected as shown to the gate of FET 605, and the drain of FET 604 is connected to the gate of FET 608 as also shown.
  • FETs 608, 605 and 601-604 constitute the equivalent of a single stage of a class AB output circuit.
  • the remaining FETs 606, 607, 609 and 610 constitute a second output stage.
  • the two output stages are connected at a junction between FET 605 and 606, and are also connected at the junction between FETs 607 and 608.
  • FETs 606,607, 609 and 610 By driving the gates of FETs 606,607, 609 and 610 from a common source as shown, the aforementioned four transistors act as a single output stage. Moreover, since FETs 605 and 608 have their respective gates tied to the gates of FETs 601 and 604 respectively, FETs 605 and 608 are part of the first stage.
  • the power is provided to the system from source 600 through series FET devices 601-604.
  • the signal to be amplified is provided at point 615 as shown.
  • the signal is then amplified through the consecutive AB stages and an output is seen at point 616.
  • Fig. 4 permits smaller transistors utilized in the prior art arrangements or circuits with the same response times. The use of such smaller transistors provides for reduced input capacitance and thus, lower delay.
  • the circuit does not generate significant crossover distortion, thereby eliminating the need for a feedback loop in most applications. This mode of operation thus reduces power consumption. It is also noted that the system has at most three current paths, unlike some prior art arrangements that include at least four such paths.
  • the device may be powered by a voltage source or a current source.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Amplifiers (AREA)

Abstract

A set of class AB output stages are cascaded to provide a class AB device circuit which utilizes relatively small transistors, low power, and virtually eliminates crossover distortion. The input may be powered by a voltage or a current source.

Description

Fast cascaded class AB output stage with FET devices
This invention relates to high voltage and power output circuits, and more particularly, to an improved cascaded configuration for a class AB MOS output stage.
High voltage and high power output circuits may be manufactured from bipolar output stages or MOS structures. A typical class AB output stage utilizing MOS structures is shown in Fig. 1.
Usually, there are several important parameters relevant to the design of a output stage. Crossover distortion should be minimized in order to provide an accurate noise- free output signal. Additionally, it is desirable to reduce static power consumption of the output stage.
Over the years, numerous variations of cascaded class AB configurations have been developed. With respect to the large number of available such configurations, each has its own advantages and/or disadvantages. Several such prior art examples are discussed below.
Fig. 1 depicts a cascaded class AB buffer utilizing bipolar transistors and several diodes as shown. Notably, there are four static current paths 201-204, leading to increased power consumption. As stated above, minimization of power consumption is a goal in class AB output stages. Thus, the arrangement of Fig. 1 is suboptimal. Fig. 2 shows a class C Darlington output stage with biasing resistors utilizing
FET technology. The arrangement of Fig. 2 would appear to consume less power than that of Fig. 1 , owing to the fact that there are less current paths. It is noted however, that in the arrangement of Fig. 2, transistors M3 and M4 see the load through biasing resistors Rl and R2. For purely capacitive loads, transistors M3 and M4 must be sized properly to prevent slowing down of the circuit. Often, this means utilizing larger transistors, with higher power consumption, than desirable. Thus, the larger transistors can make up for the reduction in current paths, and a relatively high power consuming device still results.
In addition to the foregoing power consumption problem, another problem in output stages is that of crossover distortion. A prior art known technique of minimizing crossover distortion is to utilize a feedback loop to cancel such distortion. However, the implementation of such a feedback loop also results in added power consumption.
In view of the above, there exists a need in the art for an improved circuit for minimizing required current and thus power consumption of the Class AB output stage while at the same time eliminating crossover distortion.
The above and other problems with the prior art are overcome in accordance with the present invention. The present invention includes a circuit having cascaded output stages utilizing three sets of FET devices. Of the three sets of FET devices, in a preferred embodiment, a first set includes four FETs, a second set includes a different four FETs, and a third set includes two FETs. Two of the transistors from the second set and the two transistors from the third set comprise one class AB stage, and the remaining two transistors from the second set and all four transistors from the first set comprise the second class AB stage. The two stages are cascaded in a manner that reduces the required size for the transistors as well as eliminating crossover distortion. The arrangement avoids such crossover distortion without the need for a feedback loop, thereby eliminating the additional components that would otherwise be required and also minimizing power dissipation.
The circuit has the further advantage of minimizing current paths, and thus power consumption, while permitting smaller size transistors to be used, even to drive relatively highly capacitive output loads. Further advantages of the present invention will become clear from the following detailed description and drawings.
Fig. 1 shows a exemplary prior art arrangement; Fig. 2 depicts an additional prior art arrangement having the drawback of relatively high power consumption; and
Fig. 3 shows an exemplary embodiment of the present invention utilizing ten FET devices.
Fig. 3 shows an exemplary embodiment of the present invention utilizing ten FET devices. It is understood that the particular transistors utilized are not critical to the present invention, and that other types of active devices may be utilized. The exemplary embodiment of Fig. 3 comprises four FET devices 601-604 connected to the input power source. The source of FET 601 is connected as shown to the gate of FET 605, and the drain of FET 604 is connected to the gate of FET 608 as also shown. FETs 608, 605 and 601-604 constitute the equivalent of a single stage of a class AB output circuit. The remaining FETs 606, 607, 609 and 610 constitute a second output stage. The two output stages are connected at a junction between FET 605 and 606, and are also connected at the junction between FETs 607 and 608.
By driving the gates of FETs 606,607, 609 and 610 from a common source as shown, the aforementioned four transistors act as a single output stage. Moreover, since FETs 605 and 608 have their respective gates tied to the gates of FETs 601 and 604 respectively, FETs 605 and 608 are part of the first stage.
Note also that in the first stage, the gates of FETs 605, 601 and 602 are connected but the gates of the remaining FETs are connected in common to a second point. In the second stage however, the gates of all of the transistors of the stage are tied to a single common point. In summary, of the ten transistors shown, six constitute a first class AB output stage, and the remaining four constitute a second outputs stage connected in a cascaded fashion.
In operation, the power is provided to the system from source 600 through series FET devices 601-604. The signal to be amplified is provided at point 615 as shown. The signal is then amplified through the consecutive AB stages and an output is seen at point 616.
Notably, unlike the prior art arrangement of Fig. 3C, FETs 605 and 608 do not see the output through biasing resistors, since the connection 305 in Fig. 3 is not present in Fig. 4. Accordingly, the arrangement of Fig. 4 permits smaller transistors utilized in the prior art arrangements or circuits with the same response times. The use of such smaller transistors provides for reduced input capacitance and thus, lower delay.
Additionally, the circuit does not generate significant crossover distortion, thereby eliminating the need for a feedback loop in most applications. This mode of operation thus reduces power consumption. It is also noted that the system has at most three current paths, unlike some prior art arrangements that include at least four such paths.
It is understood that the above describes only the preferred embodiments and is for exemplary purposes only. Other types of active devices may be utilized, and the invention is not limited to the embodiments disclosed herein. The device may be powered by a voltage source or a current source.

Claims

CLAIMS:
1. Apparatus comprising at least a first output stage (601-605, 608) and a second output stage (606-607, 609-610), said first output stage comprising plural FET devices (601- 605, 608) having gates, said plural FET devices being divided into first and second subsets, FET devices in said first subset (601, 605) being connected at their gates to a first common point, FET devices in said second subset (604, 608) being connected at their gates to a second common point (615), and all FETs in said second stage (606, 607, 609, 610) being connected at their gates to a single common point.
2. Apparatus of claim 1 wherein said first stage includes more FET devices than said second stage.
3. Apparatus of claim 2 further comprising a voltage source (601) for providing power.
4. Apparatus of claim 2 further comprising a current source (600) for providing power.
5. Apparatus of claim 4 wherein said circuit is driven with a voltage input (615).
6. A method of amplifying a signal through a cascaded output stage comprising the steps of connecting a first set of plural FETs to form a first output stage (601-605, 608), connecting a second set of FETs to form a second output stage (606, 607, 609, 610), connecting said first output stage to said second output stage at least two points, and connecting all gates of said second set of FETs to a common point.
7. The method of claim 6 wherein all gates of said first set of FETs (601-605,
608) are not connected to a common point.
8. The method of claim 7 wherein said gates of said first set are divided into two subsets, and further comprising connecting all gates in each of said subsets to a separate common point.
9. The method of claim 8 wherein said first set includes more FETs than said second set.
10. The method of claim 9 wherein further including connecting the source to the gate for at least two of the FETs (601, 602) in said first set.
11. The method of claim 10 further comprising connecting the gate to the drain for at least two of said FETs in said second set (606, 607).
12. method of claim 11 further comprising connecting the gate to the drain for at least two FETs in said first set (603, 604).
EP03715264A 2002-05-28 2003-04-28 Fast cascaded class ab output stage with fet devices Expired - Lifetime EP1518322B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/156,248 US6727758B2 (en) 2002-05-28 2002-05-28 Fast cascaded class AB bipolar output stage
US156248 2002-05-28
PCT/IB2003/001708 WO2003100967A1 (en) 2002-05-28 2003-04-28 Fast cascaded class ab output stage with fet devices

Publications (2)

Publication Number Publication Date
EP1518322A1 true EP1518322A1 (en) 2005-03-30
EP1518322B1 EP1518322B1 (en) 2010-03-03

Family

ID=29582218

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03715264A Expired - Lifetime EP1518322B1 (en) 2002-05-28 2003-04-28 Fast cascaded class ab output stage with fet devices

Country Status (9)

Country Link
US (1) US6727758B2 (en)
EP (1) EP1518322B1 (en)
JP (1) JP2005528056A (en)
KR (1) KR20050007561A (en)
CN (1) CN1656673B (en)
AT (1) ATE460008T1 (en)
AU (1) AU2003219452A1 (en)
DE (1) DE60331544D1 (en)
WO (1) WO2003100967A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7078973B2 (en) * 2004-10-07 2006-07-18 Texas Instruments Incorporated Bipolar rail-to-rail output stage
US7839994B1 (en) 2005-03-01 2010-11-23 Marvell International Ltd. Class A-B line driver for gigabit Ethernet
KR101163457B1 (en) * 2006-02-24 2012-07-18 삼성전자주식회사 Low Voltage Regulated Cascade Circuits and CMOS Analog Circuits
US7795975B2 (en) * 2008-02-27 2010-09-14 Mediatek Inc. Class AB amplifier
US7902882B2 (en) * 2008-12-29 2011-03-08 Daniele Vimercati Apparatus including a follower output buffer having an output impedance that adapts to a transmission line impedance
JP6320546B2 (en) * 2014-09-29 2018-05-09 三菱電機株式会社 Operational amplifier circuit
WO2016091593A1 (en) 2014-12-09 2016-06-16 Merus Audio Aps A regulated high side gate driver circuit for power transistors

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4267517A (en) * 1977-12-07 1981-05-12 Tokyo Shibaura Denki Kabushiki Kaisha Operational amplifier
JP3508333B2 (en) * 1995-10-16 2004-03-22 セイコーエプソン株式会社 Constant voltage circuit
US6259280B1 (en) * 1997-09-25 2001-07-10 Texas Instruments Incorporated Class AB amplifier for use in semiconductor memory devices
JP3123485B2 (en) 1997-11-06 2001-01-09 日本電気株式会社 Semiconductor power amplifier
US5973563A (en) * 1997-12-10 1999-10-26 National Semiconductor Corporation High power output stage with temperature stable precisely controlled quiescent current and inherent short circuit protection
CN1074610C (en) * 1998-04-27 2001-11-07 王斌 Power-like amplifier output stage by adopting parallel voltage-stabilizing, quick thermal tracking biased compensation circuit
US6175277B1 (en) * 1999-02-08 2001-01-16 Texas Instruments Incorporated Bias network for CMOS power devices
CN1175559C (en) * 2000-09-09 2004-11-10 王仲季 Power amplifier without cross-over distortion
US6466093B1 (en) * 2000-09-19 2002-10-15 Texas Instruments Incorporated Low voltage low thd CMOS audio (power) amplifier

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO03100967A1 *

Also Published As

Publication number Publication date
EP1518322B1 (en) 2010-03-03
DE60331544D1 (en) 2010-04-15
US20030222718A1 (en) 2003-12-04
US6727758B2 (en) 2004-04-27
ATE460008T1 (en) 2010-03-15
CN1656673A (en) 2005-08-17
CN1656673B (en) 2010-05-26
AU2003219452A1 (en) 2003-12-12
KR20050007561A (en) 2005-01-19
WO2003100967A1 (en) 2003-12-04
JP2005528056A (en) 2005-09-15

Similar Documents

Publication Publication Date Title
US6005439A (en) Unity gain signal amplifier
US7242250B2 (en) Power amplifier
US6844777B2 (en) Audio amplifier
US6727758B2 (en) Fast cascaded class AB bipolar output stage
US7164298B2 (en) Slew rate enhancement circuit via dynamic output stage
US7750689B1 (en) High voltage switch with reduced voltage stress at output stage
JP3818546B2 (en) Current mode analog signal multiplexer
US6664851B1 (en) Selectable single mode or differential mode operation in a single amplifier
JPH03141712A (en) Operation amplifier
WO1983004352A1 (en) Current-driven enfet logic circuits
US6570450B2 (en) Efficient AC coupled CMOS RF amplifier
JPH0318119A (en) Complementary type metallic-oxide semiconductor translator
US6924703B2 (en) Amplifier circuit with a shared current source
US6911866B2 (en) Method and device for switch-on current limiting in push-pull amplifying power stages
US20080129380A1 (en) Constant Current Darlington Circuits for High Power
KR0145857B1 (en) Current consumption optimization circuit in operational amplifier
US6784735B2 (en) High switching speed differential amplifier
US5268650A (en) Amplifier circuit with bipolar and field-effect transistors
US7696825B2 (en) Apparatus for receiving input and bias signals at common node
US6504413B1 (en) Buffer improvement
WO2025216798A1 (en) Bias circuit for cascode fet amplifier with variable drain bias
JP2001085953A (en) Bias current control type amplifier circuit
JP2001298355A (en) Cmos output circuit
KR19980065102A (en) Low voltage low power amplifier
JPH0722874A (en) Amplifier

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20041228

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR

17Q First examination report despatched

Effective date: 20070405

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: NXP B.V.

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REF Corresponds to:

Ref document number: 60331544

Country of ref document: DE

Date of ref document: 20100415

Kind code of ref document: P

REG Reference to a national code

Ref country code: NL

Ref legal event code: VDEP

Effective date: 20100303

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100303

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100303

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100303

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100303

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100303

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100303

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100614

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100303

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100303

Ref country code: BE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100303

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100604

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100303

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100303

Ref country code: MC

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100430

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100603

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100303

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100428

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100705

26N No opposition filed

Effective date: 20101206

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100430

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100430

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100303

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100904

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100428

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100303

REG Reference to a national code

Ref country code: DE

Ref legal event code: R084

Ref document number: 60331544

Country of ref document: DE

REG Reference to a national code

Ref country code: DE

Ref legal event code: R084

Ref document number: 60331544

Country of ref document: DE

Effective date: 20141015

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 13

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 14

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 15

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 16

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20200323

Year of fee payment: 18

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20200319

Year of fee payment: 18

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20200319

Year of fee payment: 18

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 60331544

Country of ref document: DE

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20210428

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210430

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210428

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20211103