EP1510000A1 - Operational amplifier with independent input offset trim for high and low common mode input voltages - Google Patents

Operational amplifier with independent input offset trim for high and low common mode input voltages

Info

Publication number
EP1510000A1
EP1510000A1 EP03760203A EP03760203A EP1510000A1 EP 1510000 A1 EP1510000 A1 EP 1510000A1 EP 03760203 A EP03760203 A EP 03760203A EP 03760203 A EP03760203 A EP 03760203A EP 1510000 A1 EP1510000 A1 EP 1510000A1
Authority
EP
European Patent Office
Prior art keywords
current
trim
input
differential
common mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP03760203A
Other languages
German (de)
French (fr)
Other versions
EP1510000B1 (en
Inventor
Yuhong Huang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Analog Devices Inc
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Publication of EP1510000A1 publication Critical patent/EP1510000A1/en
Application granted granted Critical
Publication of EP1510000B1 publication Critical patent/EP1510000B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
    • H03F3/45766—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using balancing means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45376—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using junction FET transistors as the active amplifying circuit
    • H03F3/45408—Complementary long tailed pairs having parallel inputs and being supplied in parallel
    • H03F3/45417—Folded cascode stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45028—Indexing scheme relating to differential amplifiers the differential amplifier amplifying transistors are folded cascode coupled transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45048—Calibrating and standardising a dif amp
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45308—Indexing scheme relating to differential amplifiers the common gate stage of a cascode dif amp being implemented as one mirror circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45466—Indexing scheme relating to differential amplifiers the CSC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit

Definitions

  • This invention relates to the field of trim circuits, and particularly to trim circuits for operational amplifiers which employ complementary input pairs to achieve a rail-to-rail common mode input range.
  • Operational amplifiers have an associated parameter, referred to as input offset voltage (V os ) , which specifies the op amp's differential input voltage applied to the amplifier's input terminals when the output voltage or current is zero. V os is zero for an ideal amplifier. To reduce V os - some op amps provide one or more "trim" inputs; applying appropriate currents or voltages to the trim inputs reduces V os .
  • V os input offset voltage
  • FIG. 1 One example of an op amp with a trimmable V os is shown in FIG. 1; this approach is described in U.S. Patent No. 6,194,962 to Chen.
  • the op amp's input consists of a first differential transistor pair MN1 and MN2 , and a complementary differential transistor pair MPl and MP2 ; both input pairs are connected to receive a differential input signal applied to input terminals V+ and V- .
  • MN1 and MN2 are biased with " a tail current source 10 and MPl and MP2 receive a tail current from a source 12.
  • each input pair In responding to the differential input voltage, each input pair produces a differential current that feeds in to a folded cascode stage 14, which produces an output current I OUt that varies with the differential currents received from the input pairs.
  • a pair of trim inputs TRIMl and TRIM2 are connected to respective nodes of the folded cascode stage 14.
  • the PMOS input pair MPl, MP2 is active when the input common mode voltage (V c ) is low (below a pre-set threshold voltage)
  • the NMOS input pair is active when V cm is high (above the pre-set threshold voltage) .
  • a first correction current ⁇ I1 is applied to TRIMl or TRIM2 to reduce V os to zero.
  • the correction provided by ⁇ Il is given by ⁇ ll/gmp, where gmp is the transconductance of PMOS transistors MPl and MP2; correction current ⁇ I1 is applied throughout the entire common mode input range.
  • a high V cm is applied to the op amp, and a second correction current ⁇ I2 is applied to TRIMl or TRIM2
  • the trim range for a high V cm offset has to be larger than the untrimmed offset range, due to the effect of the low V cm correction current ⁇ I1.
  • the trim range for low V cm can the be set at ⁇ 2.5mV, but the trim range for a high V cm has to be set at ⁇ 5mV.
  • any supply voltage or V cm dependent mismatch of ⁇ I1 and ⁇ I2 leads to a supply/V cm dependence for the post- trim V os at high V cm .
  • This approach also places a constraint on the procedure used to calibrate the op amp, requiring that the calibration be done in a prescribed sequence.
  • the present op amp provides independent trimming of V os for both high and low common mode input voltages.
  • the amplifier includes complementary input pairs, and employs a steering circuit which provides a tail , current I a ii to one input pair when V cm is less than a threshold voltage V h - and provides Itail to the other input pair when V cm is greater than V t h •
  • the input pairs produces an output current I out through a load stage; I out varies with the pairs' differential output currents.
  • the load stage which is preferably a folded cascode stage, includes one or more trim inputs which enable V os to be varied with one or more trim signals applied to the trim inputs.
  • a first trim signal generating circuit provides a first trim signal to a trim input only when V cm is less V th and a second trim signal generating circuit provides a second trim signal to a trim input only when V cm is greater than V - This allows the input offset voltages at high and low V cm to be adjusted independently, thereby avoiding the problems identified above .
  • the steering circuit includes a steering transistor which steers tail current to a PMOS input pair when V cm is less than a threshold voltage V t h, and to a NMOS input pair via a current mirror circuit when V cm > V th .
  • a first trim signal generating circuit generates a first trim signal, suitable for trimming V og at low V cm (PMOS pair active) , by mirroring a fixed bias current to a first digital-to-analog converter (DAC) which produces the first trim signal in response.
  • a second trim signal generating circuit generates a second trim signal suitable for trimming V os at high V cm (NMOS pair active) when tail current is steered to the NMOS input pair.
  • a diverting circuit is connected to divert the fixed bias current when tail current is steered to the NMOS input pair, such that the first trim signal is reduced to zero.
  • the first trim signal can be tailored to trim V O ⁇ at low V cm
  • the second trim signal trims V os at high V cm
  • each trim signal can be independently varied without affecting the other.
  • FIG. 1 is a schematic diagram of a known op amp with
  • FIG. 2 is a block/schematic diagram which illustrates the basic principles of an op amp with independent input offset trim for high and low common mode input voltages per the present invention.
  • FIG. 3 is a schematic diagram of a preferred embodiment of an op amp with independent input offset trim for high and low common mode input voltages per the present invention.
  • the op amp includes complementary input pairs: an NMOS pair MNl, MN2, and a PMOS pair MPl, MP2 ; each is connected to receive a differential input signal at input terminals V+ and V- .
  • the PMOS ' sources are connected together at a common mode node 20, and the NMOS' sources are connected together at a common mode node 22.
  • Each input pair produces a differential current that is fed to a load stage 18 - preferably implemented as a folded cascode stage - which produces an output current I out that varies with the input voltage applied to the input pairs.
  • Load stage 18 includes at least one trim input (two trim inputs, TRIMl and TRIM2 , are shown in the exemplary embodiment shown in FIG. 2), and is arranged such that the op amp's input offset voltage V os can be varied by applying one or more trim signals to the trim inputs.
  • the op amp includes a steering circuit 24, which is arranged to provide tail current to one or the other of the input pairs depending on the relationship between the differential input signal's common mode input voltage V cm and a threshold voltage V th - Steering circuit 24 provides a tail current I a -. ⁇ to common mode node 20 when V cm is less than V th , and provides I ta -. ⁇ to common mode node 22 when V cm is greater than V th .
  • the op amp also includes a first trim signal generating circuit 26 and a second trim signal generating circuit 28.
  • Circuit 26 is arranged to provide a first trim signal ⁇ I1 to at least one of the op amp's trim inputs only when V cm is less than V th .
  • circuit 28 is arranged to provide a second trim signal ⁇ I2 to at least one of the op amp's trim inputs only when V cm is greater than V th -
  • the trim signal generating circuits are arranged such that first trim signal ⁇ I1 is set to trim V os for a low V cm , and second trim signal ⁇ I2 is set to trim V oa for a high V cm -
  • the present op amp is arranged such that trim signals ⁇ I1 and ⁇ I2 can be independently varied without affecting the other. This provides several advantages over the prior art approach described above.
  • the trim range for a high V cm offset is no longer required to be widened because of the adverse effect of the low V cm trim signal - the trim ranges can be set solely by the untrimmed offset voltage range for both high and low common mode input voltages.
  • the independent trim signal generating circuits eliminate problems caused by supply voltage or V cm dependent mismatch of ⁇ I1 and ⁇ I2, and remove constraints that were previously imposed on the amplifier's calibration procedure.
  • steering circuit 24 is made from a fixed current source 30 which outputs tail current Itaii- steering transistor MP3 , and a current mirror made from an input transistor MN3 and an output transistor MN4.
  • Steering transistor MP3 has its source-drain circuit connected between common mode node 20 and current mirror input transistor MN3 , and its gate connected to a bias voltage V th - When so arranged, when V cm ⁇ V th , steering transistor MP3 is off and Itan s provided to common mode node 20 and the PMOS input pair. When V cm > V th , steering transistor MP3 is on and conducts Itaii to the current mirror, which mirrors the tail current to common mode node 22 and the NMOS input pair .
  • Trim signal generating circuit 26 is preferably made from a fixed current source 32 which outputs a bias current II, a current mirror made from an input transistor MN5 and an output transistor MN6 , and a DAC 34.
  • the MN5/MN6 current mirror mirrors II to the reference current input of DAC 34.
  • DAC 34 produces correction current ⁇ I1, which is connected to one of the trim inputs of load stage 18.
  • Trim signal generating circuit 28 is preferably made from a transistor MN7 connected to conduct a current 12 when steering transistor MP3 steers I ta ii to the MN3/MN4 current mirror, and a DAC 36.
  • the operational amplifier also includes a diverting circuit 38, which is arranged to divert bias current II from the MN5/MN6 current mirror when steering ⁇ transistor MP3 steers I Ca ii to the MN3/MN4 current mirror, which serves to reduce or eliminate correction current ⁇ I1.
  • Diverting circuit 38 preferably comprises a diverting transistor MN8 which is connected to the output of fixed current source 32 and in parallel with MN7. MN8 diverts current II away from the MN5/MN6 current mirror when steering transistor MP3 steers I ta ii to the MN3/MN4 current mirror; i.e, when V cm > V th - In this way, the drive current to DAC 34 is reduced or eliminated, as is correction current ⁇ I1. Diverting transistor MN8 is preferably sized to reduce current II (and thus correction current ⁇ I1) to zero.
  • V cm > V th MP3 steers 180 ⁇ A to current mirror transistor MN3.
  • * MN8 needs to conduct at least 10 ⁇ A.
  • MN8 and MN3 need to form a current mirror having a ratio of at least 1:18.
  • the op amp is preferably arranged with trim input TRIMl as a "positive" trim input, such that the application of a positive trim signal ⁇ I1 or ⁇ I2 reduces a positive V os - and with TRIM2 as a "negative" trim input which reduces a negative V os with the application of a positive trim signal ⁇ I1 or ⁇ I2.
  • trim input TRIMl as a "positive" trim input, such that the application of a positive trim signal ⁇ I1 or ⁇ I2 reduces a positive V os - and with TRIM2 as a "negative” trim input which reduces a negative V os with the application of a positive trim signal ⁇ I1 or ⁇ I2.
  • DACs 34 and 36 ⁇ could each be designed to output positive or negative trim signals. In this case, only one trim input would be needed, to which both ⁇ I1 and ⁇ I2 would be connected.
  • FIG. 3 is merely one possible way of implementing the invention.
  • a number of mechanisms could be employed to ensure that ⁇ I1 is generated only when V cm ⁇ , and that ⁇ I2 is generated only when V cm > V t h-
  • the invention can be used with other load topologies: the implementation of load stage 18 shown in FIGs . 1-3 is merely exemplary.
  • the implementation shown in FIG. 3 can be a single- stage operational amplifier, or the first stage of a multistage operational amplifier.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

An operational amplifier provides independent trimming of Vos for both high and low common mode input voltages. The amplifier includes complementary input pairs (MP1/MP2, MN1/MN2), and employs a steering circuit (24) which provides a tail current Itail to one pair when Vcm is less than a threshold voltage Vth, and provides Itail to the other pair when Vcm > Vth. The input pairs drive a load stage (14) which includes one or more trim inputs (TRIM1, TRIM2) that enable Vos to be varied with one or more trim signals applied to the trim inputs. A first trim signal generating circuit (26) provides a first trim signal (ΔI1) only when Vcm < Vth, and a second trim signal generating circuit (28) provides a second trim signal (ΔI2) to a trim input only whenVcm > Vth. This allows the input offset voltages at high and low Vcm to be adjusted independently.

Description

OPERATIONAL AMPLIFIER WITH INDEPENDENT INPUT OFFSET TRIM FOR HIGH AND LOW COMMON MODE INPUT VOLTAGES
This application claims the benefit of provisional patent application number 60/388,288 to Huang, filed June 12, 2002.
BACKGROUND OF THE INVENTION Field of the Invention
This invention relates to the field of trim circuits, and particularly to trim circuits for operational amplifiers which employ complementary input pairs to achieve a rail-to-rail common mode input range.
Description of the Related Art
Operational amplifiers have an associated parameter, referred to as input offset voltage (Vos) , which specifies the op amp's differential input voltage applied to the amplifier's input terminals when the output voltage or current is zero. Vos is zero for an ideal amplifier. To reduce Vos- some op amps provide one or more "trim" inputs; applying appropriate currents or voltages to the trim inputs reduces Vos .
One example of an op amp with a trimmable Vos is shown in FIG. 1; this approach is described in U.S. Patent No. 6,194,962 to Chen. The op amp's input consists of a first differential transistor pair MN1 and MN2 , and a complementary differential transistor pair MPl and MP2 ; both input pairs are connected to receive a differential input signal applied to input terminals V+ and V- . MN1 and MN2 are biased with "a tail current source 10 and MPl and MP2 receive a tail current from a source 12. In responding to the differential input voltage, each input pair produces a differential current that feeds in to a folded cascode stage 14, which produces an output current IOUt that varies with the differential currents received from the input pairs. A pair of trim inputs TRIMl and TRIM2 are connected to respective nodes of the folded cascode stage 14. In operation, the PMOS input pair (MPl, MP2) is active when the input common mode voltage (Vc) is low (below a pre-set threshold voltage) , and the NMOS input pair is active when Vcm is high (above the pre-set threshold voltage) . When a low Vcm is applied to the op amp, a first correction current ΔI1 is applied to TRIMl or TRIM2 to reduce Vos to zero. The correction provided by ΔIl is given by Δll/gmp, where gmp is the transconductance of PMOS transistors MPl and MP2; correction current ΔI1 is applied throughout the entire common mode input range. After ΔI1 has been set, a high Vcm is applied to the op amp, and a second correction current ΔI2 is applied to TRIMl or TRIM2
(with ΔI1 still applied) to reduce Voa. Thus, for a high
Vcm, the correction provided by ΔIl and ΔI2 is given by
(ΔI1+ΔI2) /gmn, where g n is the transconductance of NMOS transistors MNl and MN2, since ΔI1 is present throughout the entire 'common mode input range, while ΔI2 is only present at high Vcm.
This approach has several disadvantages. For example, the trim range for a high Vcm offset has to be larger than the untrimmed offset range, due to the effect of the low Vcm correction current ΔI1. For example, if the untrimmed offset for both high Vcm and low Vcm has a range of ±2.5mV, the trim range for low Vcm can the be set at ±2.5mV, but the trim range for a high Vcm has to be set at ±5mV. In addition, any supply voltage or Vcm dependent mismatch of ΔI1 and ΔI2 leads to a supply/Vcm dependence for the post- trim Vos at high Vcm. This approach also places a constraint on the procedure used to calibrate the op amp, requiring that the calibration be done in a prescribed sequence. SUMMARY OF THE INVENTION
An operational amplifier is presented which overcomes the problems noted above.
The present op amp provides independent trimming of Vos for both high and low common mode input voltages. The amplifier includes complementary input pairs, and employs a steering circuit which provides a tail, current Iaii to one input pair when Vcm is less than a threshold voltage Vh- and provides Itail to the other input pair when Vcm is greater than Vth • The input pairs produces an output current Iout through a load stage; Iout varies with the pairs' differential output currents. The load stage, which is preferably a folded cascode stage, includes one or more trim inputs which enable Vos to be varied with one or more trim signals applied to the trim inputs. A first trim signal generating circuit provides a first trim signal to a trim input only when Vcm is less Vth and a second trim signal generating circuit provides a second trim signal to a trim input only when Vcm is greater than V - This allows the input offset voltages at high and low Vcm to be adjusted independently, thereby avoiding the problems identified above .
In a preferred embodiment, the steering circuit includes a steering transistor which steers tail current to a PMOS input pair when Vcm is less than a threshold voltage Vth, and to a NMOS input pair via a current mirror circuit when Vcm > Vth . A first trim signal generating circuit generates a first trim signal, suitable for trimming Vog at low Vcm (PMOS pair active) , by mirroring a fixed bias current to a first digital-to-analog converter (DAC) which produces the first trim signal in response. A second trim signal generating circuit generates a second trim signal suitable for trimming Vos at high Vcm (NMOS pair active) when tail current is steered to the NMOS input pair. A diverting circuit is connected to divert the fixed bias current when tail current is steered to the NMOS input pair, such that the first trim signal is reduced to zero. In this way, the first trim signal can be tailored to trim VOΞ at low Vcm, the second trim signal trims Vos at high Vcm, and each trim signal can be independently varied without affecting the other.
Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram of a known op amp with
VOΞ trim inputs. FIG. 2 is a block/schematic diagram which illustrates the basic principles of an op amp with independent input offset trim for high and low common mode input voltages per the present invention.
FIG. 3 is a schematic diagram of a preferred embodiment of an op amp with independent input offset trim for high and low common mode input voltages per the present invention.
DETAILED DESCRIPTION OF THE INVENTION The principles of an operational amplifier with independent input offset trim for high and low common mode input voltages are illustrated in FIG. 2. As before, the op amp includes complementary input pairs: an NMOS pair MNl, MN2, and a PMOS pair MPl, MP2 ; each is connected to receive a differential input signal at input terminals V+ and V- . The PMOS ' sources are connected together at a common mode node 20, and the NMOS' sources are connected together at a common mode node 22. Each input pair produces a differential current that is fed to a load stage 18 - preferably implemented as a folded cascode stage - which produces an output current Iout that varies with the input voltage applied to the input pairs. Load stage 18 includes at least one trim input (two trim inputs, TRIMl and TRIM2 , are shown in the exemplary embodiment shown in FIG. 2), and is arranged such that the op amp's input offset voltage Vos can be varied by applying one or more trim signals to the trim inputs.
The op amp includes a steering circuit 24, which is arranged to provide tail current to one or the other of the input pairs depending on the relationship between the differential input signal's common mode input voltage Vcm and a threshold voltage Vth- Steering circuit 24 provides a tail current Ia-.ι to common mode node 20 when Vcm is less than Vth, and provides Ita-.ι to common mode node 22 when Vcm is greater than Vth.
The op amp also includes a first trim signal generating circuit 26 and a second trim signal generating circuit 28. Circuit 26 is arranged to provide a first trim signal ΔI1 to at least one of the op amp's trim inputs only when Vcm is less than Vth. Similarly, circuit 28 is arranged to provide a second trim signal ΔI2 to at least one of the op amp's trim inputs only when Vcm is greater than Vth- The trim signal generating circuits are arranged such that first trim signal ΔI1 is set to trim Vos for a low Vcm, and second trim signal ΔI2 is set to trim Voa for a high Vcm-
The present op amp is arranged such that trim signals ΔI1 and ΔI2 can be independently varied without affecting the other. This provides several advantages over the prior art approach described above. The trim range for a high Vcm offset is no longer required to be widened because of the adverse effect of the low Vcm trim signal - the trim ranges can be set solely by the untrimmed offset voltage range for both high and low common mode input voltages. The independent trim signal generating circuits eliminate problems caused by supply voltage or Vcm dependent mismatch of ΔI1 and ΔI2, and remove constraints that were previously imposed on the amplifier's calibration procedure.
A preferred embodiment of the present invention is shown in FIG. 3. Here, steering circuit 24 is made from a fixed current source 30 which outputs tail current Itaii- steering transistor MP3 , and a current mirror made from an input transistor MN3 and an output transistor MN4. Steering transistor MP3 has its source-drain circuit connected between common mode node 20 and current mirror input transistor MN3 , and its gate connected to a bias voltage Vth- When so arranged, when Vcm < Vth, steering transistor MP3 is off and Itan s provided to common mode node 20 and the PMOS input pair. When Vcm > Vth, steering transistor MP3 is on and conducts Itaii to the current mirror, which mirrors the tail current to common mode node 22 and the NMOS input pair .
Trim signal generating circuit 26 is preferably made from a fixed current source 32 which outputs a bias current II, a current mirror made from an input transistor MN5 and an output transistor MN6 , and a DAC 34. The MN5/MN6 current mirror mirrors II to the reference current input of DAC 34. In response to the mirrored current, DAC 34 produces correction current ΔI1, which is connected to one of the trim inputs of load stage 18. Trim signal generating circuit 28 is preferably made from a transistor MN7 connected to conduct a current 12 when steering transistor MP3 steers Itaii to the MN3/MN4 current mirror, and a DAC 36. Current 12 is applied to the reference current input of DAC 36, which produces correction current ΔI2 in response; ΔI2 is connected to one of the trim inputs of load stage 18. Since 12 is only present when steering transistor MP3 steers Ita-.ι to the MN3/MN4 current mirror (i.e., when Vcm > Vth) , ΔI2 is only generated when Vcm > vth. The operational amplifier also includes a diverting circuit 38, which is arranged to divert bias current II from the MN5/MN6 current mirror when steering ■ transistor MP3 steers ICaii to the MN3/MN4 current mirror, which serves to reduce or eliminate correction current ΔI1. When so arranged, correction current ΔI1 is reduced or eliminated when Vcm > th, such that correction current ΔI1 is only generated when Vcm < Vth. Diverting circuit 38 preferably comprises a diverting transistor MN8 which is connected to the output of fixed current source 32 and in parallel with MN7. MN8 diverts current II away from the MN5/MN6 current mirror when steering transistor MP3 steers Itaii to the MN3/MN4 current mirror; i.e, when Vcm > Vth- In this way, the drive current to DAC 34 is reduced or eliminated, as is correction current ΔI1. Diverting transistor MN8 is preferably sized to reduce current II (and thus correction current ΔI1) to zero. For example, assume that tail current source 30 outputs 180 μA and trim signal generating circuit current source 32 outputs 10 μA (i.e., II = 10 μA) . When Vcm > Vth, MP3 steers 180 μA to current mirror transistor MN3. To reduce II (and ΔI1) to zero,* MN8 needs to conduct at least 10 μA. To achieve this, MN8 and MN3 need to form a current mirror having a ratio of at least 1:18.
The op amp is preferably arranged with trim input TRIMl as a "positive" trim input, such that the application of a positive trim signal ΔI1 or ΔI2 reduces a positive Vos- and with TRIM2 as a "negative" trim input which reduces a negative Vos with the application of a positive trim signal ΔI1 or ΔI2. Alternatively, DACs 34 and 36 ^could each be designed to output positive or negative trim signals. In this case, only one trim input would be needed, to which both ΔI1 and ΔI2 would be connected.
Note that though the present operational amplifier has been illustrated as implemented exclusively with field- effect transistors (FETs) , the invention is equally applicable to an implementation in which some or all of the transistors are bipolar.
Further note that the implementation shown in FIG. 3 is merely one possible way of implementing the invention. A number of mechanisms could be employed to ensure that ΔI1 is generated only when Vcm < , and that ΔI2 is generated only when Vcm > Vth- In addition, the invention can be used with other load topologies: the implementation of load stage 18 shown in FIGs . 1-3 is merely exemplary.
The implementation shown in FIG. 3 can be a single- stage operational amplifier, or the first stage of a multistage operational amplifier.
While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. Accordingly, it is intended that the invention be limited only in terms of the appended claims.

Claims

I CLAIM :
1. An operational amplifier with independent input offset trim for high and low common mode input voltages, comprising : an input stage, comprising: a first differential transistor pair
(MP1,MP2) connected to receive a differential input signal and to produce a first differential output current which varies with said differential input signal, the current circuits of said first differential pair connected together at a first common mode node (20) , a second differential transistor pair (MN1,MN2), complementary to said first pair, connected to receive said differential input signal and to produce a second differential output current which varies with said differential input signal, the current circuits of said second differential pair connected together at a second common mode node (22) , a steering circuit (24) which provides a tail current Itaii to said first differential pair at said first common mode node when the common mode voltage Vcm of said differential input signal is less than a threshold voltage Vth and to provide Itaii to said second differential pair at said second common mode node when Vcm is greater than Vch, a load stage (14) arranged to produce an output current (Iout) which varies with said first and second differential output currents, said load stage including at least one trim input (TRIMl , TRIM2) and further arranged to vary the input offset voltage of said op amp with one or more signals applied to said at least one trim input, a first trim signal generating circuit (26) arranged to provide a first trim signal (ΔI1) to said at least one trim input only when Vcm < Vth, and a second trim signal generating circuit (28) arranged to provide a second trim signal (ΔI2) to said at least one trim input only when Vcm > Vth.
2. The op amp of claim 1, wherein said steering circuit comprises: a current source (30) connected to provide Itaii to said first common mode node, a steering transistor (MP3) having its current circuit connected to said first common mode node and its control input connected to Vth such that said steering transistor is conducts a current in response to said threshold voltage, and a first current mirror (MN3,MN4) connected to mirror the current conducted by said steering transistor to said second common mode node.
3. The op amp of claim 2, wherein said first trim signal generating circuit receives a first bias current
(11) and produces said first trim signal in response to said first bias current, said op amp further comprising a diverting circuit (MN8) which diverts said first bias current from said first trim signal generating circuit when Cm > th such that said first trim signal is reduced to zero .
4. The op amp of claim 2, wherein said second trim signal generating circuit receives a second bias current
(12) and produces said second trim signal in response to said second bias current, said second bias current varying with said mirrored current such that said second trim signal is provided only when Vcm > Vth.
5. The op amp of claim 2, wherein said first trim signal generating circuit comprises: a fixed current source (32) which produces a first bias current (II) , a first digital-to-analog converter (DAC) (34) which produces said first trim signal in response to a current provided at its reference current input, and a second current mirror (MN5,MN6) which receives said first bias current and mirrors it to said DAC ' s reference current input, said second current generating circuit comprises: a second digital-to-analog converter (DAC) (36) which produces said second trim signal in response to a current (12) provided at its reference current input, and a transistor (MN7) connected to mirror said current conducted by said steering transistor to said second DAC, further comprising a diverting transistor (MN8) connected to the output of said fixed current source and arranged to mirror said current conducted by said steering transistor such that said first bias current is diverted from said second current mirror when Vcm is greater than Vt -
6. The op amp of claim 5, wherein said diverting transistor is sized to divert all of said first bias current from said second current mirror such that said first trim signal is reduced to zero when Vcm is greater than Vth.
7. The op amp of claim 1, wherein said load stage is a folded cascode stage.
8. An operational amplifier with independent input offset trim for high and low common mode input voltages, comprising : an input stage, comprising: a first differential transistor pair
(MP1,MP2) connected to receive a differential input signal and to produce a first differential output current which varies with said differential input signal, the current circuits of said first differential pair connected together at a first common mode node (20) , a second differential transistor pair (MN1,MN2), complementary to said first pair, connected to receive said differential input signal and to produce a second differential output current which varies with said differential input signal, the current circuits of said second differential pair connected together at a second common mode node (22) , a steering circuit (24) which provides a tail current Itaii to said first differential pair at said first common mode node when the common mode voltage Vcm of said differential input signal is less than a threshold voltage Vth and to provide Itaii to said second differential pair at said second common mode node when Vcm > Vh, said steering circuit comprising: a current source (30) connected to provide Itaii to said first common mode node, a steering transistor (MP3) having its current circuit connected to said first common mode node and its control input connected to Vth such that said steering transistor conducts a current in response to said threshold voltage, and a first current mirror (MN3,MN4) connected to mirror the current conducted by said steering transistor to said second common mode node, a load stage (14) arranged to produce an output current (Iout) which varies with said first and second differential output currents, said load stage including at least one trim input (TRIMl , TRIM2) and further arranged to vary the input offset voltage Vos of said op amp with one or more signals applied to said at least one trim input, a first current generating circuit (26) comprising : a fixed current source (32) which produces a first bias current (II) , a first digital-to-analog converter (DAC)
(34) which produces a first trim signal (ΔI1) to said at least one trim input in response to a current provided at its reference current input, and a second current mirror (MN5,MN6) which receives said first bias current and mirrors it to said DAC ' s reference current input, a second current generating circuit (28) comprising : a second digital-to-analog converter (DAC) (36) which produces a second trim signal (ΔI2) to said at least one trim input in response to a current provided at its reference current input, and a transistor (MN7) connected to mirror said current conducted by said steering transistor to said second DAC, and a diverting transistor (MN8) connected to the output of said fixed current source and arranged to mirror said current conducted by said steering transistor such that said first bias current is diverted from said second current mirror when Vcm > Vt , said diverting transistor sized to divert said first bias current from said second current mirror such that said first trim signal is reduced to zero when Vcm > Vth.
9. The op amp of claim 8, wherein said load stage is a folded cascode stage.
10. The op amp of claim 8, wherein said load stage's trim inputs comprise a positive trim input and a negative trim input, such that a positive trim signal applied to said positive trim input reduces a positive Vos and a positive trim signal applied to said negative trim input reduces a negative Vos .
EP03760203A 2002-06-12 2003-04-16 Operational amplifier with independent input offset trim for high and low common mode input voltages Expired - Lifetime EP1510000B1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US38828802P 2002-06-12 2002-06-12
US388288P 2002-06-12
US192189 2002-07-08
US10/192,189 US6696894B1 (en) 2002-06-12 2002-07-08 Operational amplifier with independent input offset trim for high and low common mode input voltages
PCT/US2003/011919 WO2003107530A1 (en) 2002-06-01 2003-04-16 Operational amplifier with independent input offset trim for high and low common mode input voltages

Publications (2)

Publication Number Publication Date
EP1510000A1 true EP1510000A1 (en) 2005-03-02
EP1510000B1 EP1510000B1 (en) 2006-01-25

Family

ID=29739034

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03760203A Expired - Lifetime EP1510000B1 (en) 2002-06-12 2003-04-16 Operational amplifier with independent input offset trim for high and low common mode input voltages

Country Status (5)

Country Link
US (1) US6696894B1 (en)
EP (1) EP1510000B1 (en)
JP (1) JP4395067B2 (en)
DE (1) DE60303383T2 (en)
WO (1) WO2003107530A1 (en)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6844781B1 (en) * 2003-07-07 2005-01-18 Ami Semiconductor, Inc. Dual differential-input amplifier having wide input range
US7170347B1 (en) * 2003-11-17 2007-01-30 National Semiconductor Corporation Offset trim circuit and method for a constant-transconductance rail-to-rail CMOS input circuit
US7049889B2 (en) * 2004-03-31 2006-05-23 Analog Devices, Inc. Differential stage voltage offset trim circuitry
US6927714B1 (en) * 2004-03-31 2005-08-09 Maxim Integrated Products, Inc. Current steering digital-to-analog (DAC) converter with improved dynamic performance
JP4826073B2 (en) * 2004-08-05 2011-11-30 日本電気株式会社 Differential amplifier and data driver for display device using the same
KR100564630B1 (en) * 2004-08-06 2006-03-29 삼성전자주식회사 Digital-to-analog converter for outputting analog signal including the fixed offset irrelevant to a change of digital input signal
US7358809B2 (en) * 2004-11-08 2008-04-15 Elder J Scott Method for forming elements with reduced variation
US8502557B2 (en) 2006-06-05 2013-08-06 Analog Devices, Inc. Apparatus and methods for forming electrical networks that approximate desired performance characteristics
US7339430B2 (en) * 2006-07-26 2008-03-04 Aimtron Technology Corp. Rail-to-rail operational amplifier with an enhanced slew rate
US9356568B2 (en) 2007-06-05 2016-05-31 Analog Devices, Inc. Apparatus and methods for chopper amplifiers
US7714651B2 (en) * 2007-11-05 2010-05-11 National Semiconductor Corporation Apparatus and method for low power rail-to-rail operational amplifier
US8289077B2 (en) * 2007-11-12 2012-10-16 Nxp B.V. Signal processor comprising an amplifier
JP2009284050A (en) * 2008-05-20 2009-12-03 Nec Electronics Corp Differential amplifier circuit
JP5278144B2 (en) * 2009-04-28 2013-09-04 セイコーエプソン株式会社 Amplification circuit, integrated circuit device, and electronic apparatus
KR101096198B1 (en) * 2010-06-01 2011-12-22 주식회사 하이닉스반도체 Rail-to-rail amplifier
US8593222B2 (en) * 2011-01-26 2013-11-26 Novatek Microelectronics Corp. Amplifier
RU2449465C1 (en) * 2011-03-24 2012-04-27 Государственное образовательное учреждение высшего профессионального образования "Южно-Российский государственный университет экономики и сервиса" (ГОУ ВПО "ЮРГУЭС") Precision operational amplifier
US10720919B2 (en) 2011-11-16 2020-07-21 Analog Devices, Inc. Apparatus and methods for reducing charge injection mismatch in electronic circuits
US8823454B2 (en) * 2012-03-30 2014-09-02 Freescale Semiconductor, Inc. Fully complementary self-biased differential receiver with startup circuit
US9306509B2 (en) * 2012-07-27 2016-04-05 Xilinx, Inc. Receiver having a wide common mode input range
US8816773B2 (en) 2012-10-04 2014-08-26 Analog Devices, Inc. Offset current trim circuit
JP6217115B2 (en) * 2013-04-04 2017-10-25 富士電機株式会社 Operational amplifier circuit
US9444405B1 (en) * 2015-09-24 2016-09-13 Freescale Semiconductor, Inc. Methods and structures for dynamically reducing DC offset
US9647639B1 (en) * 2015-11-13 2017-05-09 Qualcomm Incorporated Baseband filters and interfaces between a digital-to-analog converter and a baseband filter
JP7187904B2 (en) * 2018-09-06 2022-12-13 株式会社デンソー amplifier
US10924066B2 (en) 2018-10-11 2021-02-16 Semiconductor Components Industries, Llc Offset voltage trimming for operational amplifiers
US11558013B2 (en) 2019-12-03 2023-01-17 Texas Instruments Incorporated Low power operational amplifier trim offset circuitry
FR3115426B1 (en) * 2020-08-31 2023-10-27 St Microelectronics Grenoble 2 Operational amplifier
CN112601159B (en) * 2020-12-10 2022-03-15 深圳市中科蓝讯科技股份有限公司 Audio calibration circuit and audio equipment
US11929769B2 (en) 2021-05-28 2024-03-12 Skyworks Solutions, Inc. Power amplifier trimming based on coefficients for digital pre-distortion
WO2023009387A1 (en) * 2021-07-27 2023-02-02 Microchip Technology Incorporated Op-amp with random offset trim across input range with rail-to-rail input
CN114006587B (en) * 2021-11-02 2023-09-01 中国电子科技集团公司第二十四研究所 Operational amplifier with common-mode input voltage lower than 0V
US11831287B2 (en) * 2021-11-22 2023-11-28 Faraday Technology Corp. Common mode correction using ADC in analog probe based receiver
CN114285426B (en) * 2021-11-25 2023-12-12 深圳市紫光同创电子有限公司 Output swing control device and method for SerDes transmitter

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4555673A (en) * 1984-04-19 1985-11-26 Signetics Corporation Differential amplifier with rail-to-rail input capability and controlled transconductance
US4797631A (en) * 1987-11-24 1989-01-10 Texas Instruments Incorporated Folded cascode amplifier with rail-to-rail common-mode range
JP3038716B2 (en) * 1989-01-12 2000-05-08 株式会社デンソー Offset voltage adjustment circuit in differential amplifier
JP2956491B2 (en) * 1994-09-19 1999-10-04 東洋製罐株式会社 Composite lid of metal and synthetic resin and its manufacturing equipment
JPH08204468A (en) * 1995-01-20 1996-08-09 Seikosha Co Ltd Operational amplifier
US6194962B1 (en) * 1999-04-13 2001-02-27 Analog Devices, Inc. Adaptive operational amplifier offset voltage trimming system
JP2001339257A (en) * 2000-05-25 2001-12-07 Ricoh Co Ltd Operational amplifier
US6396339B1 (en) * 2000-06-28 2002-05-28 Texas Instruments Incorporated Operational amplifier trim method with process and temperature error compensation
US6522200B2 (en) * 2000-12-11 2003-02-18 Texas Instruments Incorporated Process-insensitive, highly-linear constant transconductance circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO03107530A1 *

Also Published As

Publication number Publication date
DE60303383D1 (en) 2006-04-13
US6696894B1 (en) 2004-02-24
WO2003107530A1 (en) 2003-12-24
JP2006508561A (en) 2006-03-09
EP1510000B1 (en) 2006-01-25
JP4395067B2 (en) 2010-01-06
DE60303383T2 (en) 2006-08-03

Similar Documents

Publication Publication Date Title
EP1510000B1 (en) Operational amplifier with independent input offset trim for high and low common mode input voltages
EP1756945B1 (en) Current-mode instrumentation amplifier gain error correction circuitry
JP4638481B2 (en) Differential stage voltage offset trim circuit
JP3549302B2 (en) Offset comparator with common-mode voltage stability
EP0649218B1 (en) Gain enhancement technique for operational amplifiers
KR101742343B1 (en) Driving method for obtaining a gain linear variation of a transconductance amplifier and corresponding driving circuit
EP1908168B1 (en) Temperature-independent amplifier offset trim circuit
KR19990012425A (en) Low-voltage SeaMOS op amp circuit and sample-and-hold circuit
JP3183093B2 (en) Continuous-time common mode feedback amplifier
KR102488324B1 (en) High-linearity input and output rail-to-rail amplifiers
US5789981A (en) High-gain operational transconductance amplifier offering improved bandwidth
JPH09512684A (en) Low voltage CMOS comparator
US6396339B1 (en) Operational amplifier trim method with process and temperature error compensation
US5561396A (en) Rail-to-rail input stages with gm -control by multiple input pairs
US6819170B1 (en) Apparatus for sensing differential voltages with high common-mode levels
US6727757B1 (en) Biasing circuit for transconductors
US5497122A (en) Low power class-AB integrated circuit amplifier
US5994926A (en) Circuit and method for programmably changing the transconductance of a transconductor circuit
US7227420B2 (en) Transimpedance amplifier with a high gain/bandwidth product for conversion of a DAC output current
KR100450776B1 (en) CMOS operational amplifier with class AB differential output
US7411453B1 (en) Tail-current steering circuit and method for rail-to-rail operational amplifier input stage
KR100201774B1 (en) Improved differential type operational amplifier
CN118611607A (en) Output stage circuit and amplifier

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20041111

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

RBV Designated contracting states (corrected)

Designated state(s): DE FR GB

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REF Corresponds to:

Ref document number: 60303383

Country of ref document: DE

Date of ref document: 20060413

Kind code of ref document: P

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20061026

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 14

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 15

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 16

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20210323

Year of fee payment: 19

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20210324

Year of fee payment: 19

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20210323

Year of fee payment: 19

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 60303383

Country of ref document: DE

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20220416

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220416

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220430

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20221103