EP1500508A1 - Ink jet print head identification circuit and method - Google Patents
Ink jet print head identification circuit and method Download PDFInfo
- Publication number
- EP1500508A1 EP1500508A1 EP03016075A EP03016075A EP1500508A1 EP 1500508 A1 EP1500508 A1 EP 1500508A1 EP 03016075 A EP03016075 A EP 03016075A EP 03016075 A EP03016075 A EP 03016075A EP 1500508 A1 EP1500508 A1 EP 1500508A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- ink jet
- print head
- jet print
- counter
- signal line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/015—Ink jet characterised by the jet generation process
- B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
- B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
- B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
- B41J2/04541—Specific driving circuit
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/015—Ink jet characterised by the jet generation process
- B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
- B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
- B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
- B41J2/04586—Control methods or devices therefor, e.g. driver circuits, control circuits controlling heads of a type not covered by groups B41J2/04575 - B41J2/04585, or of an undefined type
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/17—Ink jet characterised by ink handling
- B41J2/175—Ink supply systems ; Circuit parts therefor
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2202/00—Embodiments of or processes related to ink-jet or thermal heads
- B41J2202/01—Embodiments of or processes related to ink-jet heads
- B41J2202/17—Readable information on the head
Definitions
- the present invention generally relates to an ink jet print head, and more particularly, to an identification circuit for the ink jet print head and a method thereof.
- inkjet printers in order to fulfill different printing requirements for users working in different environments, different types of ink jet printers have been developed.
- each ink jet printer has different types of the ink jet print heads that correspond to it, for example, an ink jet print head with a black cartridge or color cartridge, and ink jet print heads with different number of injection nozzles.
- an identification code corresponding to its model or serial number is given to each ink jet print head when it is manufactured, so that the ink jet printer can identify different types of ink jet print heads when they are installed onto the ink jet printer, so as to use different control programs to control the ink jet print heads of different models or serial numbers.
- an identification circuit that reads one or identification codes corresponding to its model or serial number had better be designed into the ink jet print head to provide the ink jet printer to identify different types of the ink jet print heads installed thereon. Since the identification circuit of the ink jet print head is only used at the moment of the inkjet print head being installed in the ink jet printer or before the first printing operation is started, and once the ink jet print head is identified, the identification circuit can be no longer used. Therefore, it is common that the identification circuit of the ink jet print head reads the identification code stored in the ink jet print head by using the address lines of the print head array.
- FIG. 1 schematically shows a block diagram of an ink jet printer identification system.
- the ink jet printer identification system 100 comprises printer electronics 110 and print head electronics 120, wherein the printer electronics 110 and the print head electronics 120 are connected with each other via a plurality of address lines 131 and a temperature sensing output line 132.
- the printer electronics 110 comprise a controller 111 and a driving circuit 112
- the print head electronics 120 comprise a print head array 121, an identification circuit 122, and a temperature sensing circuit 123.
- the controller 111 transmits the data being printed to the driving circuit 112, and the driving circuit 112 drives the address lines 131, so as to control the print head array 121 to print out the required patterns.
- the temperature sensing circuit 123 senses the temperature of the print head, and transmits it to the controller 111 via the temperature sensing output line 132.
- the identification circuit 122 connected to part of the address lines 131 and is used to have the controller 111 send out a control signal for reading out the stored identification code, and to output the stored identification code via the temperature sensing output line 132.
- the identification circuit 200 comprises a plurality of programmable fuses F1 ⁇ F13 and a plurality of transistors Q1 ⁇ Q13. One end of each of the fuses F1 ⁇ F13 is coupled to a corresponding gate of the transistors Q1 ⁇ Q13, so as to control the "ON" or "OFF" of the transistors Q1 ⁇ Q13.
- the identification code corresponding to the type of the ink jet print head using this identification circuit 200 is stored via the programmable fuses F1 ⁇ F13. Whether each of the fuses F1 ⁇ F13 is fused or not represents a bit data of the identification code, respectively.
- a high level reading control signal is sent out via the address lines 131.
- the high level reading control signal is sent out from A13.
- the fuse F13 is reserved, the transistor Q13 is ON, therefore, the temperature sensing output line 132 is dropped down to a low level for reading an identification code of "0".
- the fuse F 13 is fused when it is programmed, the transistor Q13 is OFF, and the temperature sensing output line 132 is pulled up to a high level by the pull-up resistor (not shown) of the printer electronics 110 in FIG. 1. Therefore, an identification code of "1" is read out, and the method mentioned above can be used to sequentially read out other bits of the identification code.
- Each address line of such type of the identification circuit 200 can only read out one corresponding bit of the identification code. Therefore, the quantity of the bits in the identification code that can be stored in the print head is limited by the number of the address lines, so it is hard to expand.
- FIG. 3 shows the other identification circuit disclosed by U.S. Patent No. 5,940,095.
- the identification circuit 300 mainly comprises a plurality of one-bit shift registers 320a, 320b, 320c, and 320d for achieving the object of implementing a parallel in, serial out identification circuit. That is, when the printer electronics 110 in FIG. 1 transmits a loading control signal "Load" via the address line 325, the stored identification code is loaded in parallel to the plurality of one-bit shift registers 320a, 320b, 320c, and 320d.
- the bit data stored in the one-bit shift register 320d is shifted out via the output line 328.
- the bit data stored in the one-bit shift register 320c is shifted into the one-bit shift register 320d
- the bit data stored in the one-bit shift register 320b is shifted into the one-bit shift register 320c
- the bit data stored in the one-bit shift register 320a is shifted into the one-bit shift register 320b.
- the printer electronics 110 transmits the loading control signal "Load", and sequentially transmits the required first clock signal clk1 and the required second clock signal clk2 via the address line 326 and 327, respectively
- the identification code stored in the plurality of one-bit shift registers 320a, 320b, 320c, and 320d is output sequentially. Therefore, such parallel in, serial out identification circuit 300 is able to expand the bit number of the identification code based on the requirements with only small number of the address lines, such as 325, 326, and 327, so that it is not limited by the number of the address lines.
- the identification circuit that is able to expand the bit number of the identification code and not be limited by the number of the address lines, is not limited in implementation to the parallel in, serial out identification circuit by using the shift register mentioned above.
- the present invention provides an identification circuit for identifying the ink jet print head and a method thereof.
- the bit number of the identification code can be expanded based on the requirements, and it is not limited by the number of the address lines.
- the present invention provides an identification circuit for identifying the ink jet print head, wherein the identification circuit is suitable for use in an ink jet printer that comprises a reset signal line, at least one clock signal line, and an identification code signal line, so as to identify the type of the installed ink jet print head.
- the identification circuit comprises a counter, a logic unit, and a programming unit.
- the counter is coupled to the reset signal line and at least one clock signal line.
- the counter is reset when the reset signal is received by the reset signal line, and the count value is counted to the next value when a corresponding clock signal is received by at least one clock signal line, so as to output it from a plurality of output terminals of the counter.
- the logic unit comprises a plurality of input terminals and an output terminal.
- the output terminal is coupled to an identification code signal line, so as to output the identification code that represents the type of the ink jet print head.
- the programming unit is coupled to the output terminals of the counter and the input terminals of the logic unit. The programming unit is used for programming a corresponding connection between each output terminal of the counter and the input terminals of the logic unit.
- the counter is counted in a sequence of 1, 2, 4, 8, 16, ..., to count its count value.
- the logic unit may be an OR gate
- the OR gate may comprise an enabling control terminal for accepting the control of the clock signal of the clock signal line.
- the programming unit is programmed in a mask programmed way when the identification circuit of the ink jet print head is being manufactured, so as to store the required identification code.
- the programming unit uses fuses to provide the programmable programming unit, so as to store the required identification code.
- the present invention further provides an identification circuit for identifying the ink jet print head, wherein the identification circuit is suitable for use in an ink jet printer that comprises a reset signal line, at least one clock signal line, and an identification code signal line, so as to identify the type of the installed ink jet print head.
- the identification circuit comprises a counter, a plurality of switches, and a programming unit.
- the counter is coupled to the reset signal line and at least one clock signal line.
- the counter is reset when the reset signal is received by the reset signal line, and the count value is counted to next value when a corresponding clock signal is received by the at least one clock signal line, so as to output it from a plurality of output terminals of the counter.
- Each of the plurality of switches comprises an input terminal, an output terminal, and a control terminal.
- the output terminals of all switches are coupled to the identification code signal line, so as to output the identification code that represents the type of the ink jet print head.
- the control terminal of each switch is coupled to the corresponding output terminal of the counter, so as to accept the control from the output terminal of the counter.
- the programming unit coupled to the input terminal of the switch mentioned above is used for programming the input value that is input to the input terminal of the switch according to the identification code to be stored.
- the counter is counted in a sequence of 1, 2, 4, 8, 16, ..., to count its count value.
- the switch is made of a NMOS transistor or a CMOS transistor.
- the programming unit is programmed in a mask programmed way when the identification circuit of the ink jet print head is being manufactured, so as to store the required identification code.
- the programming unit uses fuses to provide the programmable programming unit, so as to store the required identification code.
- the present invention provides an identification method of the ink jet print head.
- the method is suitable for identifying the ink jet print head and comprises the steps of: providing a reset signal, and at least one clock signal; resetting a count value when the reset signal is received; counting a count value of the counter to next value when the at least one clock signal is received, and programming a logic circuit according to an identification code that represents the type of the ink jet print head and the count value mentioned above, so as to sequentially output the required identification code of the ink jet print head.
- FIG. 1 schematically shows a block diagram of an ink jet printer identification system.
- FIG. 2 schematically shows a diagram of an identification circuit disclosed by U.S. Patent No. 5,363,134.
- FIG. 3 schematically shows a diagram of another identification circuit disclosed by U.S. Patent No. 5,940,095.
- FIG. 4 schematically shows a diagram of an ink jet print head identification circuit of the first embodiment according to the present invention.
- FIG. 5 schematically shows an operation timing diagram of an ink jet print head identification circuit of the first and second embodiments according to the present invention.
- FIG. 6 schematically shows a diagram of an ink jet print head identification circuit of the second embodiment according to the present invention.
- FIG. 4 schematically shows a diagram of an ink jet print head identification circuit of the first embodiment according to the present invention.
- the identification circuit 400 comprises a counter 410; an OR logic unit 430 that is, for example, constituted by an OR gate; and a programming unit 420 that is, for example, constituted by a plurality of fuses.
- fuses are used as the programming unit 420 in the drawing, it will be apparent to one of the ordinary skill in the art that the programming unit 420 also can be programmed in a mask programmed way when the identification circuit 400 of the ink jet print head is being manufactured, optionally, other methods also can be applied, such as laser trimming or fusing.
- electrical connectors or conductors can be used in the programming unit 420 instead of using fuses.
- the identification circuit 400 of the ink jet print head only use three address lines of the ink jet printer (not shown): the reset signal line 401 for transmitting the reset signal "Reset", the first clock signal line 402 for transmitting the first clock signal Clk1, and the second clock signal line 403 for transmitting the second clock signal Clk2, to perform the function of identifying the type of the installed ink jet print head. Therefore, the bit number of the identification code can be expanded based on its requirement, and is not limited by the number of the address lines.
- the counter 410 is coupled to the reset signal line 401, the first clock signal line 402, and the second clock signal line 403.
- an 8-bit counter having 8 output terminals b0 ⁇ b7 is used for the required bit number of the identification code.
- Each of the output terminals b0 ⁇ b7 is coupled to one input terminal of the OR logic unit 430 via a fuse of the programming unit 420, respectively.
- Each of the input terminals of the OR logic unit 430 is grounded via a fuse of the programming unit 420, respectively, so that the required identification code can be stored by the programming.
- the OR gate that constitutes the OR logic unit 430 can further comprise an enabling control terminal EN to accept the control of the second clock signal Clk2 from the second clock signal line 403.
- the programming unit 420 can be programmed to store the required identification code. Its operation principle is described hereinafter referring to the operation timing diagram in FIG. 5.
- the counter 410 When the counter 410 receives the reset signal "Reset" from the reset signal line 401, the count value of the counter 410 is reset to 0.
- the counter 410 sequentially receives a first clock signal Clk1 and a second clock signal Clk2 from the first clock signal line 402 and the second clock signal line 403, respectively, the counter 410 counts its count value in a certain sequence, such as 1, 2, 4, 8, 16, ..., etc.
- the output terminals b0 ⁇ b7 of the counter 410 are sequentially set as a high level "1" when a first clock signal Clk1 and a second clock signal Clk2 are sequentially received from the first clock signal line 402 and the second clock signal line 403, its operation timing is like b0 ⁇ b7 shown in FIG. 5.
- the output terminal of the OR logic unit 430 When the output terminal b0 of the counter 410 is set to "1", and the output terminals b1 ⁇ b7 are "0", since the fuse F0 is reserved when it is programmed, the output terminal of the OR logic unit 430 outputs the identification code ID of "1". When the output terminal b1 of the counter 410 is "1”, and the output terminals b0 and b2 ⁇ b7 are "0", since the fuse F1 is reserved when it is programmed, the output terminal of the OR logic unit 430 outputs the identification code ID of "1".
- the output terminal of the OR logic unit 430 when the output terminal b2 of the counter 410 is "1", and the output terminals b0 ⁇ b1 and b3 ⁇ b7 are "0", since the fuse F2 is reserved when it is programmed, the output terminal of the OR logic unit 430 outputs the identification code ID of "1".
- the output terminal b3 of the counter 410 is "1"
- the output terminals b0 ⁇ b2 and b4 ⁇ b7 are "0”
- the fuse F3 is fused and F13 is reserved when they are programmed
- the output terminal of the OR logic unit 430 outputs the identification code ID of "0".
- the output terminal of the OR logic unit 430 sequentially outputs the identification code ID of "11101000", which represents the identification code of the installed ink jet print head, and its operation timing is as the ID shown in FIG. 5.
- FIG. 6 schematically shows a diagram of an ink jet print head identification circuit of the second embodiment according to the present invention.
- the identification circuit 600 comprises a counter 610; a programming unit 620 that is, for example, constituted by a plurality of fuses; and a plurality of switches 630, 631, 632, 633, 634, 635, 636, and 637 that are, for example, constituted by a plurality of the NMOS transistors.
- fuses are used as the programming unit 620 in the drawing, it will be apparent to one of the ordinary skill in the art that the programming unit 620 also can be programmed in a mask programmed way when the identification circuit 600 of the ink jet print head is being manufactured, optionally, other methods also can be applied, such as laser trimming or fusing. It should be noted that electrical connectors or conductors can be used in the programming unit 420 instead of using fuses.
- the identification circuit 600 of the ink jet print head only use three address lines of the ink jet printer (not shown): the reset signal line 601 for transmitting the reset signal "Reset", the first clock signal line 602 for transmitting the first clock signal Clk1, and the second clock signal line 603 for transmitting the second clock signal Clk2, to perform the function of identifying the type of the installed ink jet print head. Therefore, the bit number of the identification code can be expanded based on its requirement, and is not limited by the number of the address lines.
- the counter 610 is coupled to the reset signal line 601, the first clock signal line 602, and the second clock signal line 603.
- an 8-bit counter having 8 output terminals b0 ⁇ b7 is used for the required bit number of the identification code.
- Each of the output terminals b0 ⁇ b7 is coupled to one gate of the corresponding switches 630, 631, 632, 633, 634, 635, 636, and 637, respectively, so as to control the "ON” or “OFF” of the switches 630, 631, 632, 633, 634, 635, 636, and 637, respectively.
- a source/drain of each of the switches 630, 631, 632, 633, 634, 635, 636, and 637 is respectively coupled to the power terminal or grounded via the fuse of the programming unit 620, so that the required identification code can be input by the programming. Further, the other source/drain of each of the switches 630, 631, 632, 633, 634, 635, 636, and 637 are coupled together to the identification code signal line 605, so as to output the identification code.
- the programming unit 620 can be programmed to store the required identification code. Its operation principle is described hereinafter referring to the operation timing diagram in FIG. 5.
- the counter 610 When the counter 610 receives the reset signal "Reset" from the reset signal line 601, the count value of the counter 610 is reset to 0.
- the counter 610 sequentially receives a first clock signal Clk1 and a second clock signal Clk2 from the first clock signal line 602 and the second clock signal line 603, respectively, the counter 610 counts its count value in a certain sequence, such as 1, 2, 4, 8, 16, ..., etc.
- the output terminals b0 ⁇ b7 of the counter 610 are sequentially set as a high level "1" when a first clock signal Clk1 and a second clock signal Clk2 are sequentially received from the first clock signal line 602 and the second clock signal line 603, respectively, its operation timing is like b0 ⁇ b7 shown in FIG. 5.
- the switch 630 When the output terminal b0 of the counter 610 is set to "1", the switch 630 is ON, and since the fuse F0 is reserved when it is programmed, the identification code ID of "1" is output.
- the switch 631 When the output terminal b1 of the counter 610 is set to “1”, the switch 631 is ON, and since the fuse F1 is reserved when it is programmed, the identification code ID of "1” is output.
- the switch 632 is ON, and since the fuse F2 is reserved when it is programmed, the identification code ID of "1” is output.
- the identification code signal line 605 sequentially outputs the identification code ID of "11101000", which represents the identification code of the installed ink jet print head, and its operation timing is as the ID shown in FIG. 5.
- the embodiments mentioned above are only some of the embodiments embodied the present invention.
- the reference number 430 in FIG. 4 can be easily replaced with other logic unit (e.g. NAND logic unit) or decoder.
- the OR logic unit e.g. NAND logic unit
- the clock signal lines used in the present invention are not necessarily limited to using two signal lines.
- the switches 631 ⁇ 637 in FIG. 6 are not limited to be implemented by the NMOS transistors.
- an identification method of the ink jet print head is concluded.
- the method is suitable for identifying the ink jet print head and comprises the steps of: providing a reset signal, and at least one clock signal; resetting a count value when the reset signal is received; counting a count value of the counter to next value when the at least one clock signal is received, and programming a logic circuit according to an identification code that represents the type of the ink jet print head and the count value mentioned above, so as to sequentially output the required identification code of the ink jet print head.
- the count value is reset to 0, and the first clock signal and the second clock signal are sequentially received, the count value is counted in a certain sequence, such as 1, 2, 4, 8, 16, ..., etc.
- the logic circuit may be a logic gate or a plurality of NMOS or CMOS transistors.
Landscapes
- Particle Formation And Scattering Control In Inkjet Printers (AREA)
- Ink Jet (AREA)
Abstract
Description
- The present invention generally relates to an ink jet print head, and more particularly, to an identification circuit for the ink jet print head and a method thereof.
- Different types of computer peripheral products have been developed and are now widely accepted. For inkjet printers, in order to fulfill different printing requirements for users working in different environments, different types of ink jet printers have been developed. However, each ink jet printer has different types of the ink jet print heads that correspond to it, for example, an ink jet print head with a black cartridge or color cartridge, and ink jet print heads with different number of injection nozzles.
- In order to identify the types of the ink jet print head, an identification code corresponding to its model or serial number is given to each ink jet print head when it is manufactured, so that the ink jet printer can identify different types of ink jet print heads when they are installed onto the ink jet printer, so as to use different control programs to control the ink jet print heads of different models or serial numbers.
- As described above, since there are many types of the ink jet print heads, an identification circuit that reads one or identification codes corresponding to its model or serial number had better be designed into the ink jet print head to provide the ink jet printer to identify different types of the ink jet print heads installed thereon. Since the identification circuit of the ink jet print head is only used at the moment of the inkjet print head being installed in the ink jet printer or before the first printing operation is started, and once the ink jet print head is identified, the identification circuit can be no longer used. Therefore, it is common that the identification circuit of the ink jet print head reads the identification code stored in the ink jet print head by using the address lines of the print head array.
- FIG. 1 schematically shows a block diagram of an ink jet printer identification system. As shown in the drawing, the ink jet
printer identification system 100 comprisesprinter electronics 110 andprint head electronics 120, wherein theprinter electronics 110 and theprint head electronics 120 are connected with each other via a plurality ofaddress lines 131 and a temperaturesensing output line 132. Theprinter electronics 110 comprise acontroller 111 and adriving circuit 112, and theprint head electronics 120 comprise aprint head array 121, anidentification circuit 122, and atemperature sensing circuit 123. - When it is printing, the
controller 111 transmits the data being printed to thedriving circuit 112, and thedriving circuit 112 drives theaddress lines 131, so as to control theprint head array 121 to print out the required patterns. Thetemperature sensing circuit 123 senses the temperature of the print head, and transmits it to thecontroller 111 via the temperaturesensing output line 132. Theidentification circuit 122 connected to part of theaddress lines 131 and is used to have thecontroller 111 send out a control signal for reading out the stored identification code, and to output the stored identification code via the temperaturesensing output line 132. - There are several types of the identification circuits in the prior art, the one shown in FIG. 2 is one identification circuit disclosed by U.S. Patent No. 5,363,134. As shown in the drawing, the identification circuit 200 comprises a plurality of programmable fuses F1 ~ F13 and a plurality of transistors Q1 ~ Q13. One end of each of the fuses F1 ~ F13 is coupled to a corresponding gate of the transistors Q1 ~ Q13, so as to control the "ON" or "OFF" of the transistors Q1~Q13. The identification code corresponding to the type of the ink jet print head using this identification circuit 200 is stored via the programmable fuses F1~F13. Whether each of the fuses F1~F13 is fused or not represents a bit data of the identification code, respectively.
- When the printer intends to read the identification code, a high level reading control signal is sent out via the
address lines 131. Here, it is assumed that the high level reading control signal is sent out from A13. If the fuse F13 is reserved, the transistor Q13 is ON, therefore, the temperaturesensing output line 132 is dropped down to a low level for reading an identification code of "0". On the contrary, if the fuse F 13 is fused when it is programmed, the transistor Q13 is OFF, and the temperaturesensing output line 132 is pulled up to a high level by the pull-up resistor (not shown) of theprinter electronics 110 in FIG. 1. Therefore, an identification code of "1" is read out, and the method mentioned above can be used to sequentially read out other bits of the identification code. - Each address line of such type of the identification circuit 200 can only read out one corresponding bit of the identification code. Therefore, the quantity of the bits in the identification code that can be stored in the print head is limited by the number of the address lines, so it is hard to expand.
- FIG. 3 shows the other identification circuit disclosed by U.S. Patent No. 5,940,095. The
identification circuit 300 mainly comprises a plurality of one-bit shift registers printer electronics 110 in FIG. 1 transmits a loading control signal "Load" via theaddress line 325, the stored identification code is loaded in parallel to the plurality of one-bit shift registers address line bit shift register 320d is shifted out via theoutput line 328. Then, the bit data stored in the one-bit shift register 320c is shifted into the one-bit shift register 320d, the bit data stored in the one-bit shift register 320b is shifted into the one-bit shift register 320c, and the bit data stored in the one-bit shift register 320a is shifted into the one-bit shift register 320b. - Therefore, after the
printer electronics 110 transmits the loading control signal "Load", and sequentially transmits the required first clock signal clk1 and the required second clock signal clk2 via theaddress line bit shift registers identification circuit 300 is able to expand the bit number of the identification code based on the requirements with only small number of the address lines, such as 325, 326, and 327, so that it is not limited by the number of the address lines. - However, the identification circuit that is able to expand the bit number of the identification code and not be limited by the number of the address lines, is not limited in implementation to the parallel in, serial out identification circuit by using the shift register mentioned above.
- To solve the problem mentioned above, the present invention provides an identification circuit for identifying the ink jet print head and a method thereof. The bit number of the identification code can be expanded based on the requirements, and it is not limited by the number of the address lines.
- In order to achieve the object mentioned above and others, the present invention provides an identification circuit for identifying the ink jet print head, wherein the identification circuit is suitable for use in an ink jet printer that comprises a reset signal line, at least one clock signal line, and an identification code signal line, so as to identify the type of the installed ink jet print head. The identification circuit comprises a counter, a logic unit, and a programming unit.
- The counter is coupled to the reset signal line and at least one clock signal line. The counter is reset when the reset signal is received by the reset signal line, and the count value is counted to the next value when a corresponding clock signal is received by at least one clock signal line, so as to output it from a plurality of output terminals of the counter.
- The logic unit comprises a plurality of input terminals and an output terminal. The output terminal is coupled to an identification code signal line, so as to output the identification code that represents the type of the ink jet print head. The programming unit is coupled to the output terminals of the counter and the input terminals of the logic unit. The programming unit is used for programming a corresponding connection between each output terminal of the counter and the input terminals of the logic unit.
- In an embodiment, after the counter is reset, the counter is counted in a sequence of 1, 2, 4, 8, 16, ..., to count its count value.
- In an embodiment, the logic unit may be an OR gate, and the OR gate may comprise an enabling control terminal for accepting the control of the clock signal of the clock signal line.
- In an embodiment, the programming unit is programmed in a mask programmed way when the identification circuit of the ink jet print head is being manufactured, so as to store the required identification code.
- In another embodiment, the programming unit uses fuses to provide the programmable programming unit, so as to store the required identification code.
- The present invention further provides an identification circuit for identifying the ink jet print head, wherein the identification circuit is suitable for use in an ink jet printer that comprises a reset signal line, at least one clock signal line, and an identification code signal line, so as to identify the type of the installed ink jet print head. The identification circuit comprises a counter, a plurality of switches, and a programming unit.
- The counter is coupled to the reset signal line and at least one clock signal line. The counter is reset when the reset signal is received by the reset signal line, and the count value is counted to next value when a corresponding clock signal is received by the at least one clock signal line, so as to output it from a plurality of output terminals of the counter.
- Each of the plurality of switches comprises an input terminal, an output terminal, and a control terminal. The output terminals of all switches are coupled to the identification code signal line, so as to output the identification code that represents the type of the ink jet print head. The control terminal of each switch is coupled to the corresponding output terminal of the counter, so as to accept the control from the output terminal of the counter.
- The programming unit coupled to the input terminal of the switch mentioned above is used for programming the input value that is input to the input terminal of the switch according to the identification code to be stored.
- In an embodiment, after the counter is reset, the counter is counted in a sequence of 1, 2, 4, 8, 16, ..., to count its count value.
- In an embodiment, the switch is made of a NMOS transistor or a CMOS transistor.
- In an embodiment, the programming unit is programmed in a mask programmed way when the identification circuit of the ink jet print head is being manufactured, so as to store the required identification code.
- In another embodiment, the programming unit uses fuses to provide the programmable programming unit, so as to store the required identification code.
- Based on the spirit of the present invention, the present invention provides an identification method of the ink jet print head. The method is suitable for identifying the ink jet print head and comprises the steps of: providing a reset signal, and at least one clock signal; resetting a count value when the reset signal is received; counting a count value of the counter to next value when the at least one clock signal is received, and programming a logic circuit according to an identification code that represents the type of the ink jet print head and the count value mentioned above, so as to sequentially output the required identification code of the ink jet print head.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention, and together with the description, serve to explain the principles of the invention. In the drawings,
- FIG. 1 schematically shows a block diagram of an ink jet printer identification system.
- FIG. 2 schematically shows a diagram of an identification circuit disclosed by U.S. Patent No. 5,363,134.
- FIG. 3 schematically shows a diagram of another identification circuit disclosed by U.S. Patent No. 5,940,095.
- FIG. 4 schematically shows a diagram of an ink jet print head identification circuit of the first embodiment according to the present invention.
- FIG. 5 schematically shows an operation timing diagram of an ink jet print head identification circuit of the first and second embodiments according to the present invention.
- FIG. 6 schematically shows a diagram of an ink jet print head identification circuit of the second embodiment according to the present invention.
- FIG. 4 schematically shows a diagram of an ink jet print head identification circuit of the first embodiment according to the present invention. As shown in the drawing, the
identification circuit 400 comprises acounter 410; an ORlogic unit 430 that is, for example, constituted by an OR gate; and aprogramming unit 420 that is, for example, constituted by a plurality of fuses. Although fuses are used as theprogramming unit 420 in the drawing, it will be apparent to one of the ordinary skill in the art that theprogramming unit 420 also can be programmed in a mask programmed way when theidentification circuit 400 of the ink jet print head is being manufactured, optionally, other methods also can be applied, such as laser trimming or fusing. It should be noted that electrical connectors or conductors can be used in theprogramming unit 420 instead of using fuses. - As shown in FIG. 4, the
identification circuit 400 of the ink jet print head only use three address lines of the ink jet printer (not shown): thereset signal line 401 for transmitting the reset signal "Reset", the firstclock signal line 402 for transmitting the first clock signal Clk1, and the secondclock signal line 403 for transmitting the second clock signal Clk2, to perform the function of identifying the type of the installed ink jet print head. Therefore, the bit number of the identification code can be expanded based on its requirement, and is not limited by the number of the address lines. - The
counter 410 is coupled to thereset signal line 401, the firstclock signal line 402, and the secondclock signal line 403. In the present embodiment, since the bit number required for the identification code is 8 bits, an 8-bit counter having 8 output terminals b0 ~ b7 is used for the required bit number of the identification code. Each of the output terminals b0 ~ b7 is coupled to one input terminal of theOR logic unit 430 via a fuse of theprogramming unit 420, respectively. Each of the input terminals of theOR logic unit 430 is grounded via a fuse of theprogramming unit 420, respectively, so that the required identification code can be stored by the programming. Further, the OR gate that constitutes theOR logic unit 430 can further comprise an enabling control terminal EN to accept the control of the second clock signal Clk2 from the secondclock signal line 403. - If it is assumed that the identification code to be stored is 11101000, the fuse F10, F11, F12, F3, F14, F5, F6, and F7 in the drawing should be fused, and the fuse F0, F1, F2, F13, F4, F15, F16 and F 17 in the drawing should be reserved, so that the
programming unit 420 can be programmed to store the required identification code. Its operation principle is described hereinafter referring to the operation timing diagram in FIG. 5. - When the
counter 410 receives the reset signal "Reset" from thereset signal line 401, the count value of thecounter 410 is reset to 0. When thecounter 410 sequentially receives a first clock signal Clk1 and a second clock signal Clk2 from the firstclock signal line 402 and the secondclock signal line 403, respectively, thecounter 410 counts its count value in a certain sequence, such as 1, 2, 4, 8, 16, ..., etc. That is, after the count value of thecounter 410 is reset to 0, the output terminals b0 ~ b7 of thecounter 410 are sequentially set as a high level "1" when a first clock signal Clk1 and a second clock signal Clk2 are sequentially received from the firstclock signal line 402 and the secondclock signal line 403, its operation timing is like b0 ~ b7 shown in FIG. 5. - When the output terminal b0 of the
counter 410 is set to "1", and the output terminals b1 ~ b7 are "0", since the fuse F0 is reserved when it is programmed, the output terminal of theOR logic unit 430 outputs the identification code ID of "1". When the output terminal b1 of thecounter 410 is "1", and the output terminals b0 and b2 ~ b7 are "0", since the fuse F1 is reserved when it is programmed, the output terminal of theOR logic unit 430 outputs the identification code ID of "1". Similarly, when the output terminal b2 of thecounter 410 is "1", and the output terminals b0 ~ b1 and b3 ~ b7 are "0", since the fuse F2 is reserved when it is programmed, the output terminal of theOR logic unit 430 outputs the identification code ID of "1". When the output terminal b3 of thecounter 410 is "1", and the output terminals b0 ~ b2 and b4 ~ b7 are "0", since the fuse F3 is fused and F13 is reserved when they are programmed, the output terminal of theOR logic unit 430 outputs the identification code ID of "0". In the same way, the output terminal of theOR logic unit 430 sequentially outputs the identification code ID of "11101000", which represents the identification code of the installed ink jet print head, and its operation timing is as the ID shown in FIG. 5. - FIG. 6 schematically shows a diagram of an ink jet print head identification circuit of the second embodiment according to the present invention. As shown in the drawing, the
identification circuit 600 comprises acounter 610; aprogramming unit 620 that is, for example, constituted by a plurality of fuses; and a plurality ofswitches programming unit 620 in the drawing, it will be apparent to one of the ordinary skill in the art that theprogramming unit 620 also can be programmed in a mask programmed way when theidentification circuit 600 of the ink jet print head is being manufactured, optionally, other methods also can be applied, such as laser trimming or fusing. It should be noted that electrical connectors or conductors can be used in theprogramming unit 420 instead of using fuses. - As shown in FIG. 6, similarly the
identification circuit 600 of the ink jet print head only use three address lines of the ink jet printer (not shown): thereset signal line 601 for transmitting the reset signal "Reset", the firstclock signal line 602 for transmitting the first clock signal Clk1, and the secondclock signal line 603 for transmitting the second clock signal Clk2, to perform the function of identifying the type of the installed ink jet print head. Therefore, the bit number of the identification code can be expanded based on its requirement, and is not limited by the number of the address lines. - The
counter 610 is coupled to thereset signal line 601, the firstclock signal line 602, and the secondclock signal line 603. In the present embodiment, since the bit number required for the identification code is 8 bits, an 8-bit counter having 8 output terminals b0 ~ b7 is used for the required bit number of the identification code. Each of the output terminals b0 ~ b7 is coupled to one gate of the correspondingswitches switches switches programming unit 620, so that the required identification code can be input by the programming. Further, the other source/drain of each of theswitches code signal line 605, so as to output the identification code. - If it is assumed that the identification code to be stored is 11101000, the fuse F10, F11, F12, F3, F14, F5, F6, and F7 in the drawing should be fused, and the fuse F0, F1, F2, F 13, F4, F 15, F16 and F 17 in the drawing should be reserved, so that the
programming unit 620 can be programmed to store the required identification code. Its operation principle is described hereinafter referring to the operation timing diagram in FIG. 5. - When the
counter 610 receives the reset signal "Reset" from thereset signal line 601, the count value of thecounter 610 is reset to 0. When thecounter 610 sequentially receives a first clock signal Clk1 and a second clock signal Clk2 from the firstclock signal line 602 and the secondclock signal line 603, respectively, thecounter 610 counts its count value in a certain sequence, such as 1, 2, 4, 8, 16, ..., etc. That is, after the count value of thecounter 610 is reset to 0, the output terminals b0 ~ b7 of thecounter 610 are sequentially set as a high level "1" when a first clock signal Clk1 and a second clock signal Clk2 are sequentially received from the firstclock signal line 602 and the secondclock signal line 603, respectively, its operation timing is like b0 ~ b7 shown in FIG. 5. - When the output terminal b0 of the
counter 610 is set to "1", theswitch 630 is ON, and since the fuse F0 is reserved when it is programmed, the identification code ID of "1" is output. When the output terminal b1 of thecounter 610 is set to "1", theswitch 631 is ON, and since the fuse F1 is reserved when it is programmed, the identification code ID of "1" is output. Similarly, when the output terminal b2 of thecounter 610 is set to "1", theswitch 632 is ON, and since the fuse F2 is reserved when it is programmed, the identification code ID of "1" is output. When the output terminal b3 of thecounter 610 is set to "1", theswitch 633 is ON, and since the fuse F3 is fused and fuse F13 is reserved when they are programmed, the identification code ID of "0" is output. In the same way, the identificationcode signal line 605 sequentially outputs the identification code ID of "11101000", which represents the identification code of the installed ink jet print head, and its operation timing is as the ID shown in FIG. 5. - It will be apparent to one of the ordinary skill in the art that the embodiments mentioned above are only some of the embodiments embodied the present invention. For example, the
reference number 430 in FIG. 4 can be easily replaced with other logic unit (e.g. NAND logic unit) or decoder. Thus, it is not limited to use the OR logic unit. Similarly, the clock signal lines used in the present invention are not necessarily limited to using two signal lines. Optionally, it is possible to achieve the object and function of the present invention with only one clock signal line. Further, theswitches 631 ~ 637 in FIG. 6 are not limited to be implemented by the NMOS transistors. Optionally, it is also possible to implement the switches by using the CMOS transistors. - Based on the spirit of the embodiments mentioned above, an identification method of the ink jet print head is concluded. The method is suitable for identifying the ink jet print head and comprises the steps of: providing a reset signal, and at least one clock signal; resetting a count value when the reset signal is received; counting a count value of the counter to next value when the at least one clock signal is received, and programming a logic circuit according to an identification code that represents the type of the ink jet print head and the count value mentioned above, so as to sequentially output the required identification code of the ink jet print head.
- Wherein, after the count value is reset to 0, and the first clock signal and the second clock signal are sequentially received, the count value is counted in a certain sequence, such as 1, 2, 4, 8, 16, ..., etc. Further, the logic circuit may be a logic gate or a plurality of NMOS or CMOS transistors.
- Although the invention has been described with reference to a particular embodiment thereof, it will be apparent to one of the ordinary skill in the art that modifications to the described embodiment may be made without departing from the spirit of the invention. Accordingly, the scope of the invention will be defined by the attached claims not by the above detailed description.
Claims (17)
- An inkjet print head identification circuit, suitable for using in an ink jet printer that comprises a reset signal line, at least one clock signal line, and an identification code signal line, for identifying a type of the ink jet print head, comprising:a counter, coupled to the reset signal line and at least one clock signal line, used to reset the counter when a reset signal is received from the reset signal line, and used to count a count value of the counter to next value when a corresponding clock signal is received from the at least one clock signal line, so as to output the count value from a plurality of output terminals of the counter;a logic unit, comprising a plurality of input terminals and an output terminal, wherein the output terminal of the logic unit is coupled to the identification code signal line, so as to output an identification code that represents the type of the ink jet print head; anda programming unit, coupled to the output terminals of the counter and the input terminals of the logic unit, used to program the corresponding connection between each output terminal of the counter and each input terminal of the logic unit.
- The ink jet print head identification circuit of claim 1, wherein, after the counter is reset, the count value of the counter is counted in a sequence of 1, 2, 4, 8, 16, ..., etc.
- The ink jet print head identification circuit of claim 1, wherein the logic unit is an OR gate, a NAND gate, or a decoder.
- The ink jet print head identification circuit of claim 1, wherein the logic unit further comprises an enabling control terminal, and the enabling control terminal is coupled to a clock signal line.
- The ink jet print head identification circuit of claim 1, wherein the programming unit is programmed in a mask programmed way when the identification circuit of the ink jet print head is being manufactured, so as to store the identification code.
- The ink jet print head identification circuit of claim 1, wherein the programmable programming unit is provided by using a plurality of fuses, so as to store the identification code.
- The ink jet print head identification circuit of claim 1, wherein the programmable programming unit is provided by using a plurality of electrical connectors, so as to store the identification code.
- An ink jet print head identification circuit, suitable for use in an ink jet printer that comprises a reset signal line, at least one clock signal line, and an identification code signal line, for identifying a type of the ink jet print head, comprising:a counter, coupled to the reset signal line and at least one clock signal line, used to reset the counter when a reset signal is received from the reset signal line, and used to count a count value of the counter to next value when a corresponding clock signal is received from the at least one clock signal line, so as to output the count value from a plurality of output terminals of the counter;a plurality of switches, wherein each of the plurality of switches comprises an input terminal, an output terminal, and a control terminal, and all output terminals of the switches are coupled to the identification code signal line, so as to output an identification code that represents the type of the ink jet print head, and each control terminal of the switches is coupled to the corresponding output terminal of the counter, respectively; anda programming unit, coupled to the input terminals of the switches, used to program the input value of the input terminal of the switches according to the identification code to be stored.
- The ink jet print head identification circuit of claim 7, wherein, after the counter is reset, the count value of the counter is counted in a sequence of 1, 2, 4, 8, 16, ..., etc.
- The ink jet print head identification circuit of claim 7, wherein the switches are a plurality of NMOS transistors or a plurality of CMOS transistors.
- The ink jet print head identification circuit of claim 7, wherein the programming unit is programmed in a mask programmed way when the identification circuit of the ink jet print head is being manufactured, so as to store the identification code.
- The ink jet print head identification circuit of claim 7, wherein the programmable programming unit is provided by using a plurality of fuses, so as to store the identification code.
- The ink jet print head identification circuit of claim 7, wherein the programmable programming unit is provided by using a plurality of electrical connectors, so as to store the identification code.
- An ink jet print head identification method, suitable for identifying a type of the ink jet print head, comprising:providing a reset signal and at least one clock signal;resetting a count value when the reset signal is received;counting the count value to next value when the at least one clock signal is received; andprogramming a logic unit according to an identification code that represents the type of the ink jet print head and the count value, so that the ink jet print head sequentially outputs the identification code.
- The ink jet print head identification method of claim 12, wherein, after the counter is reset, the count value of the counter is counted in a sequence of 1, 2, 4, 8, 16, ..., etc.
- The ink jet print head identification method of claim 12, wherein the logic unit is an OR gate, a NAND gate, or a decoder.
- The ink jet print head identification method of claim 12, wherein the logic circuit is a plurality of NMOS transistors or a plurality of CMOS transistors.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE60301733T DE60301733T2 (en) | 2003-07-15 | 2003-07-15 | Identification circuit for an inkjet printhead |
EP03016075A EP1500508B1 (en) | 2003-07-15 | 2003-07-15 | Ink jet print head identification circuit and method |
ES03016075T ES2246446T3 (en) | 2003-07-15 | 2003-07-15 | CIRCUIT AND IDENTIFICATION METHOD FOR A PRINT HEAD BY INK JET. |
AT03016075T ATE305387T1 (en) | 2003-07-15 | 2003-07-15 | INKJET PRINT HEAD IDENTIFICATION CIRCUIT AND METHOD |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03016075A EP1500508B1 (en) | 2003-07-15 | 2003-07-15 | Ink jet print head identification circuit and method |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1500508A1 true EP1500508A1 (en) | 2005-01-26 |
EP1500508B1 EP1500508B1 (en) | 2005-09-28 |
Family
ID=33483911
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP03016075A Expired - Lifetime EP1500508B1 (en) | 2003-07-15 | 2003-07-15 | Ink jet print head identification circuit and method |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP1500508B1 (en) |
AT (1) | ATE305387T1 (en) |
DE (1) | DE60301733T2 (en) |
ES (1) | ES2246446T3 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0916503A2 (en) * | 1997-11-14 | 1999-05-19 | Canon Kabushiki Kaisha | Head, recording apparatus having the head, method for identifying the head, and method for giving identification information to the head |
US5940095A (en) * | 1995-09-27 | 1999-08-17 | Lexmark International, Inc. | Ink jet print head identification circuit with serial out, dynamic shift registers |
-
2003
- 2003-07-15 AT AT03016075T patent/ATE305387T1/en not_active IP Right Cessation
- 2003-07-15 DE DE60301733T patent/DE60301733T2/en not_active Expired - Lifetime
- 2003-07-15 EP EP03016075A patent/EP1500508B1/en not_active Expired - Lifetime
- 2003-07-15 ES ES03016075T patent/ES2246446T3/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5940095A (en) * | 1995-09-27 | 1999-08-17 | Lexmark International, Inc. | Ink jet print head identification circuit with serial out, dynamic shift registers |
EP0916503A2 (en) * | 1997-11-14 | 1999-05-19 | Canon Kabushiki Kaisha | Head, recording apparatus having the head, method for identifying the head, and method for giving identification information to the head |
Also Published As
Publication number | Publication date |
---|---|
DE60301733T2 (en) | 2006-03-16 |
ES2246446T3 (en) | 2006-02-16 |
EP1500508B1 (en) | 2005-09-28 |
DE60301733D1 (en) | 2006-02-09 |
ATE305387T1 (en) | 2005-10-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9046822B2 (en) | Systems and methods for universal imaging components | |
US8335978B2 (en) | Liquid container | |
US6871933B2 (en) | Ink jet print head identification circuit and method | |
US7738137B2 (en) | Inkjet print head synchronous serial output for data integrity | |
MX2007001482A (en) | Systems and methods for universal imaging components. | |
US8033626B2 (en) | Ink jet printhead module and ink jet printer | |
US6719397B1 (en) | Ink jet printhead identification circuit and method | |
US7036903B2 (en) | Inkjet printer checking nozzle and providing abnormal nozzle information and method thereof | |
US20150042457A1 (en) | Systems and Methods for Verifying a Chip | |
US7198348B2 (en) | Inkjet printer identification circuit | |
EP1500508B1 (en) | Ink jet print head identification circuit and method | |
JP2008224360A (en) | Semiconductor device | |
TWI437432B (en) | Toner cartridge and printer using the same and related protection management method | |
US20040095409A1 (en) | Apparatus and method for determining status of inkjet print head identification circuit | |
EP1533128A2 (en) | Ink jet printhead identification circuit and method | |
US6712438B2 (en) | Ink-jet printer and method of driving head thereof | |
US20050140703A1 (en) | Ink jet print head identification circuit and method | |
EP1529645A1 (en) | Apparatus and method for determining status of inkjet print head identification circuit | |
JP2002258691A (en) | Image forming apparatus | |
EP1561587B1 (en) | Inkjet printer identification circuit | |
US20110205590A1 (en) | Storage device, substrate, liquid container, host device, and system | |
US7992952B2 (en) | Enhanced communications protocol for improved modularity in a micro-fluid ejection device | |
TW580432B (en) | Apparatus and method for determining an identification circuit state of ink jet print head | |
US12046309B2 (en) | Element substrate | |
TWI473723B (en) | An identification circuit for an inkjet printhead |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20040102 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR |
|
AX | Request for extension of the european patent |
Extension state: AL LT LV MK |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: BE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20050928 Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED. Effective date: 20050928 Ref country code: FI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20050928 Ref country code: SK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20050928 Ref country code: SI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20050928 Ref country code: RO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20050928 Ref country code: CH Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20050928 Ref country code: CZ Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20050928 Ref country code: AT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20050928 Ref country code: LI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20050928 |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: EP |
|
AKX | Designation fees paid |
Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: FG4D |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20051228 Ref country code: DK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20051228 Ref country code: SE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20051228 Ref country code: BG Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20051228 |
|
REF | Corresponds to: |
Ref document number: 60301733 Country of ref document: DE Date of ref document: 20060209 Kind code of ref document: P |
|
REG | Reference to a national code |
Ref country code: ES Ref legal event code: FG2A Ref document number: 2246446 Country of ref document: ES Kind code of ref document: T3 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: PT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20060228 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: HU Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20060329 |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: PL |
|
ET | Fr: translation filed | ||
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20060717 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MC Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20060731 |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed |
Effective date: 20060629 |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: MM4A |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: EE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20050928 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20060715 Ref country code: TR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20050928 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: CY Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20050928 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 13 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 14 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 15 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 16 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: NL Payment date: 20190712 Year of fee payment: 17 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: ES Payment date: 20190814 Year of fee payment: 17 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20200723 Year of fee payment: 18 Ref country code: FR Payment date: 20200728 Year of fee payment: 18 Ref country code: GB Payment date: 20200722 Year of fee payment: 18 |
|
REG | Reference to a national code |
Ref country code: NL Ref legal event code: MM Effective date: 20200801 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: NL Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20200801 |
|
REG | Reference to a national code |
Ref country code: ES Ref legal event code: FD2A Effective date: 20211202 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: ES Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20200716 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R119 Ref document number: 60301733 Country of ref document: DE |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20210715 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210715 Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20220201 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210731 |