EP1488315A2 - Systeme de stockage de donnees - Google Patents

Systeme de stockage de donnees

Info

Publication number
EP1488315A2
EP1488315A2 EP03714385A EP03714385A EP1488315A2 EP 1488315 A2 EP1488315 A2 EP 1488315A2 EP 03714385 A EP03714385 A EP 03714385A EP 03714385 A EP03714385 A EP 03714385A EP 1488315 A2 EP1488315 A2 EP 1488315A2
Authority
EP
European Patent Office
Prior art keywords
directors
director
memory
boards
pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03714385A
Other languages
German (de)
English (en)
Inventor
Robert A. Thibault
Daniel Castel
Brian Gallagher
Paul C. Wilson
John K. Walton
Christopher S. Maclellan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EMC Corp
Original Assignee
EMC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/112,598 external-priority patent/US6877061B2/en
Priority claimed from US10/109,583 external-priority patent/US6907483B1/en
Application filed by EMC Corp filed Critical EMC Corp
Publication of EP1488315A2 publication Critical patent/EP1488315A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache

Definitions

  • This invention relates generally to data storage systems, and more particularly to data storage systems having redundancy arrangements to protect against total system failure in the event of a failure in a component or subassembly of the storage system.
  • host computer/servers As is known in the art, large host computers and servers (collectively referred to herein as “host computer/servers”) require large capacity data storage systems. These large computer/servers generally includes data processors, which perform many operations on data introduced to the host computer/server through peripherals including the data storage system. The results of these operations are output to peripherals, including the storage system.
  • One type of data storage system is a magnetic disk storage system.
  • a bank of disk drives and the host computer/server are coupled together through an interface.
  • the interface includes "front end” or host computer/server controllers (or directors) and “back- end” or disk controllers (or directors).
  • the interface operates the controllers (or directors) in such a way that they are transparent to the host computer/server. That is, data is stored in, and retrieved from, the bank of disk drives in such a way that the host computer/server merely thinks it is operating with its own local disk drive.
  • One such system is described in U.S.
  • Patent 5,206,939 entitled “System and Method for Disk Mapping and Data Retrieval", inventors Moshe Yanai, Natan Vishlitzky, Bruno Alterescu and Daniel Castel, issued April 27, 1993, and assigned to the same assignee as the present invention.
  • the interface may also include, in addition to the host computer/server controllers (or directors) and disk controllers (or directors), addressable cache memories.
  • the cache memory is a semiconductor memory and is provided to rapidly store data from the host computer/server before storage in the disk drives, and, on the other hand, store data from the disk drives prior to being sent to the host computer/server.
  • the cache memory being a semiconductor memory, as distinguished from a magnetic memory as in the case of the disk drives, is much faster than the disk drives in reading and writing data.
  • the host computer/server controllers, disk controllers and cache memory are interconnected through a backplane printed circuit board. More particularly, disk controllers are mounted on disk controller printed circuit boards.
  • the host computer/server controllers are mounted on host computer/server controller printed circuit boards.
  • cache memories are mounted on cache memory printed circuit boards.
  • the disk directors, host computer/server directors, and cache memory printed circuit boards plug into the backplane printed circuit board.
  • the backplane printed circuit board has a pair of buses. One set the disk directors is connected to one bus and another set of the disk directors is connected to the other bus.
  • one set the host computer/server directors is connected to one bus and another set of the host computer/server directors is directors connected to the other bus.
  • the cache memories are connected to both buses. Each one of the buses provides data, address and control information.
  • the use of two buses Bl, B2 provides a degree of redundancy to protect against a total system failure in the event that the controllers or disk drives connected to one bus, fail. Further, the use of two buses increases the data transfer bandwidth of the system compared to a system having a single bus.
  • the host computer/server 12 issues a write request to one of the front-end directors 14 (i.e., host computer/server directors) to perform a write command.
  • One of the front-end directors 14 replies to the request and asks the host computer 12 for the data.
  • the director 14 determines the size of the data and reserves space in the cache memory 18 to store the request.
  • the front- end director 14 then produces control signals on one of the address memory busses Bl, B2 connected to such front-end director 14 to enable the transfer to the cache memory 18.
  • the host computer/server 12 then transfers the data to the front-end director 14.
  • the front-end director 14 advises the host computer/server 12 that the transfer is complete.
  • the front-end director 14 looks up in a Table, not shown, stored in the cache memory 18 to determine which one of the back-end directors 20 (i.e., disk directors) is to handle this request.
  • the Table maps the host computer/server 12 addresses into an address in the bank 14 of disk drives.
  • the front-end director 14 then puts a notification in a "mail box" (not shown and stored in the cache memory 18) for the back-end director 20, which is to handle the request, the amount of the data and the disk address for the data.
  • Other back-end directors 20 poll the cache memory 18 when they are idle to check their "mail boxes”. If the polled "mail box" indicates a transfer is to be made, the back-end director 20 processes the request, addresses the disk drive in the bank 22, reads the data from the cache memory 18 and writes it into the addresses of a disk drive in the bank 22.
  • a read request is instituted by the host computer/server 12 for data at specified memory locations (i.e., a requested data block).
  • One of the front-end directors 14 receives the read request and examines the cache memory 18 to determine whether the requested data block is stored in the cache memory 18. If the requested data block is in the cache memory 18, the requested data block is read from the cache memory 18 and is sent to the host computer/server 12.
  • the front-end director 14 determines that the requested data block is not in the cache memory 18 (i.e., a so-called "cache miss") and the director 14 writes a note in the cache memory 18 (i.e., the "mail box") that it needs to receive the requested data block.
  • the back-end directors 20 poll the cache memory 18 to determine whether there is an action to be taken (i.e., a read operation of the requested block of data).
  • the one of the back-end directors 20 which poll the cache memory 18 mail box and detects a read operation reads the requested data block and initiates storage of such requested data block stored in the cache memory 18. When the storage is completely written into the cache memory 18, a read complete indication is placed in the "mail box" in the cache memory 18.
  • front-end directors 14 are polling the cache memory 18 for read complete indications. When one of the polling front-end directors 14 detects a read complete indication, such front-end director 14 completes the transfer of the requested data which is now stored in the cache memory 18 to the host computer/server 12.
  • a method for producing a data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface.
  • the system interface has a plurality of first directors, a plurality of second directors, and a global memory.
  • the method includes: providing a backplane having slots adapted to have plugged therein a plurality of printed circuit board.
  • the printed circuit boards include: a plurality of first director boards having the first directors; a plurality of second printed circuit boards having the second directors; a plurality of memory printed circuit boards providing the global memory; a plurality of dummy first director boards having first jumpers; a plurality of dummy second director boards having second jumpers; a plurality of dummy memory boards having third jumpers.
  • the method includes wiring the backplane to effect a connection among the first, second and third jumpers to interconnect the first plurality of director to the host computer/server, the plurality of second plurality of directors to the bank of disk drives and the global memory to the first plurality of directors and to the second plurality of director.
  • a data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface.
  • the system interface has a plurality of first directors, a plurality of second directors, and a global memory.
  • the interface comprises: a backplane having slots adapted to have plugged therein a plurality of printed circuit board.
  • the printed circuit boards comprise: a plurality of first director boards having the first directors; a plurality of second printed circuit boards having the second directors; a plurality of memory printed circuit boards providing the global memory; a plurality of dummy first director boards having first jumpers; a plurality of dummy second director boards having second jumpers; a plurality of dummy memory boards having third jumpers.
  • the backplane is wired to effect a connection among the first, second and third jumpers to interconnect the first plurality of director to the host computer/server, the plurality of second plurality of directors to the bank of disk drives and the plurality of memories to the first plurality of directors and to the second plurality of director.
  • a data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface.
  • the system interface includes: a plurality of first directors coupled to the host computer/server; a plurality of second directors coupled to the bank of disk drives; and, a cache memory.
  • the cache memory includes: a common memory array having a pair of redundant data/control ports; and, a pair of logic networks each one coupled to a corresponding one of the pair of data/control ports. There are separate point- to-point data paths between each one of the directors and the cache memory.
  • a pair of the first directors are adapted for coupling to the pair of logic networks of the cache memory.
  • each one of the first directors is on a different printed circuit board.
  • a data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface.
  • the system interface includes: a plurality of first directors coupled to the host computer/server; a plurality of second directors coupled to the bank of disk drives; and a cache memory.
  • the cache memory has: a common memory array having a pair of redundant data/control ports; and a pair of logic networks each one coupled to a corresponding one of the pair of data/control ports.
  • a pair of the second directors are adapted for coupling to the pair of logic networks.
  • each one of the pair of second directors is on a different printed circuit board.
  • a data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface.
  • the interface includes: a plurality of first directors coupled to the host computer/server; a plurality of second directors coupled to the bank of disk drives; and a cache memory.
  • the cache memory has a pair of memory boards, each memory board having a memory array. There are separate point-to-point data paths between each one of the directors and the global cache memory.
  • One of the first directors is adapted for coupling to the memory arrays of the pair of memory boards.
  • one of the second directors is adapted for coupling to the memory arrays of the pair of memory boards.
  • each one of the memory boards has: a common memory array having a pair of redundant data/control ports; and, a pair of logic networks each one coupled to a corresponding one of the pair of data/control ports.
  • the printed circuit board is wired to effect a connection with jumpers to enable a pair of the first directors to be coupled to the pair of logic networks and a pair of the second directors to be coupled to the pair of logic networks.
  • the printed circuit board is wired to effect a connection with the jumpers to connect one of the first directors the memory arrays of a pair of the memory boards.
  • the method includes providing each one of the directors on a different printed circuit board.
  • the backplane is wired and connected to the jumpers to connect each one of the pair of logic networks to one of the first directors and one of the second directors.
  • FIG. 1 is a block diagram of a data storage system according to the PRIOR ART
  • FIG. 2 is a block diagram of a data storage system according to the invention.
  • FIG. 3 is a sketch of an electrical cabinet storing a system interface used in the data storage system of FIG. 2;
  • FIG. 4 is a diagramatical, isometric sketch showing printed circuit boards providing the system interface of the data storage system of FIG. 2;
  • FIG. 5 is a block diagram of the system interface used in the data storage system of FIG. 2;
  • FIG. 6 is a diagram of an exemplary global cache memory board used in the system interface of FIG. 2;
  • FIG. 6 A is a diagram showing an exemplary one of the memory printed circuit boards used in the system of FIG. 2;
  • FIG. 7 is a diagram showing a pair of front-end director boards coupled between a pair of host processors and global cache memory boards and a pair of front-end director boards coupled between a pair of disk drives and global cache memory boards used in the system interface of the system of FIG. 2;
  • FIG. 8 is an elevation view of a backplane used in the system of FIG. 2, such backplane having slots adapted to receive front-end director printed circuit boards, back- end director printed circuit boards and memory boards;
  • FIG. 9 is an elevation view of a backplane used in the system of FIG. 2, such backplane having slots adapted to receive front-end director printed circuit boards, back- end director printed circuit boards, memory boards and dummy front-end director printed circuit boards, dummy back-end director printed circuit boards, dummy memory boards, such dummy printed circuit boards having jumpers to enable the same backplane to be used with a fully populated system having all of the memory boards and directors in FIG. 2 and a de-populated system having only a portion of the all of the memory boards and directors in FIG. 2;
  • FIG. 10 shows the dummy memory boards used in the de-populated system
  • FIG. 11 shows the dummy director boards used in the de-populated system
  • FIG. 12 A is a diagram showing an exemplary one of the memory printed circuit boards used in the de-populated system
  • FIG. 13 is a diagram showing a pair of front-end director boards coupled between a pair of host processors and global cache memory boards and a pair of front-end director boards coupled between a pair of disk drives and global cache memory boards used in the system interface of the de-populated system;
  • FIG. 14 is a universal director board adapted for use in the system interface of the de-populated system of FIG. 13.
  • the system interface 160 includes: a plurality of, here 32 front-end directors I8O1-I8O32 coupled to the host computer/server 120 via ports 123 ⁇ -123 32 ; a plurality of back-end directors 200 ⁇ -200 32 coupled to the bank of disk drives 140 via ports 123 3 -123 6 ; a data transfer section 240, having a global cache memory 220, coupled to the plurality of front-end directors 180 ⁇ -180 ⁇ 6 and the back-end directors 200 ⁇ -200 ⁇ 6 ; and a messaging network 260, operative independently of the data transfer section 240, coupled to the plurality of front-end directors 180 ⁇ -180 32 and the plurality of back-end directors 200 ⁇ - 200 2 , as shown .
  • the front-end and back-end directors 180 ⁇ -180 2 , 200 ⁇ -200 32 are functionally similar and include a microprocessor ( ⁇ P) 299 (i.e., a central processing unit (CPU) and RAM), a message engine/ CPU controller 314 and a data pipe 316, described in detail in the following co-pending patent applications:
  • ⁇ P microprocessor
  • CPU central processing unit
  • RAM random access memory
  • the front-end and back-end directors 180 ⁇ - 180 32 , 200i-200 32 control data transfer between the host computer/server 120 and the bank of disk drives 140 in response to messages passing between the directors 18O1-180 3 , 2OO1-2OO32 through the messaging network 260.
  • the messages facilitate the data transfer between host computer/server 120 and the bank of disk drives 140 with such data passing through the global cache memory 220 via the data transfer section 240.
  • the data passes between the host computer to the global cache memory 220 through the data pipe 316 in the front-end directors 180 1 - 180 32 and the messages pass through the message engine/CPU controller 314 in such front-end directors 18O1-I8O 3 2.
  • the data passes between the back-end directors 200 ⁇ -200 32 and the bank of disk drives 140 and the global cache memory 220 through the data pipe 316 in the back-end directors 200 ⁇ -200 32 and again the messages pass through the message engine/CPU controller 314 in such back-end director 200 ⁇ -200 32 .
  • the cache memory 220 in the data transfer section 240 is not burdened with the task of transferring the director messaging. Rather the messaging network 260 operates independent of the data transfer section 240 thereby increasing the operating bandwidth of the system interface 160.
  • the request is passed from one of a plurality of, here 32, host computer processors 1211-121 3 in the host computer 120 to one or more of the pair of the front-end directors 180 ⁇ -180 32 connected to such host computer processor 121 1 - 121 32 .
  • each one of the host computer processors 121 1 -121 32 is coupled to here a pair (but not limited to a pair) of the front-end directors 180 ⁇ -180 32 , to provide redundancy in the event of a failure in one of the front end-directors 181 1 -181 32 coupled thereto.
  • the bank of disk drives 140 has a plurality of, here 32, disk drives 1411-141 32 , each disk drive 1411-141 32 being coupled to here a pair (but not limited to a pair) of the back-end directors 200 ⁇ -200 32j to provide redundancy in the event of a failure in one of the back-end directors 200 ⁇ -200 32 coupled thereto).
  • front-end director pairs 180 ⁇ ,180 2 ; ... I8O 3 1, 18O32 are coupled to processor pairs 1211, 121 2 ; ... 121 3 ⁇ , 121 32 , respectively, as shown.
  • back-end director pairs 200 ⁇ , 200 2 ; ...200 3 ⁇ , 200 32 are coupled to disk drive pairs 141 ⁇ , 141 2 ; ...
  • Each front-end director 180 ⁇ -180 32 includes a microprocessor ( ⁇ P) 299 (i.e., a central processing unit (CPU) and RAM) described in detail in the referenced patent application. Suffice it to say here, however, that the microprocessor 299 makes a request for the data from the global cache memory 220.
  • the global cache memory 220 has a resident cache management table, not shown.
  • DMA Direct Memory Access
  • the front-end director 180 ⁇ -180 32 receiving the data request determines that the requested data is not in the global cache memory 220 (i.e., a "miss") as a result of a query of the cache management table in the global cache memory 220, such front-end director 180 ⁇ -180 32 concludes that the requested data is in the bank of disk drives 140.
  • the front-end director 180 ⁇ -180 32 that received the request for the data must make a request for the data from one of the back-end directors 200 ⁇ -200 32 in order for such back-end director 200 ⁇ -200 32 to request the data from the bank of disk drives 140.
  • the mapping of which back-end directors 200 ⁇ -200 3 control which disk drives 141 ⁇ -141 32 in the bank of disk drives 140 is determined during a power-up initialization phase.
  • the map is stored in the global cache memory 220.
  • the front-end director 180 ⁇ -180 32 makes a request for data from the global cache memory 220 and determines that the requested data is not in the global cache memory 220 (i.e., a "miss")
  • the front-end director I8O1-I8O32 is also advised by the map in the global cache memory 220 of the back-end director 200 ⁇ -200 32 responsible for the requested data in the bank of disk drives 140.
  • the requesting front-end director I8O1-180 32 then must make a request for the data in the bank of disk drives 140 from the map designated back-end director 200 ⁇ -200 32 .
  • This request between the front-end director 180 ⁇ -180 32 and the appropriate one of the back-end directors 200 ⁇ -200 32 is by a message which passes from the front-end director I8O1-I8O 32 through the message network 260 to the appropriate back-end director 200 ⁇ -200 32 . It is noted then that the message does not pass through the global cache memory 220 (i.e., does not pass through the data transfer section 240) but rather passes through the separate, independent message network 260.
  • the back-end director 200 ⁇ -200 32 advises the requesting front-end director 180 ⁇ -180 32 that the transfer is accomplished by a message, which passes from the back-end director 200 ⁇ -200 32 to the front-end director 180 ⁇ -180 32 through the message network 260.
  • the front-end director I8O1-I8O 3 2 is thereby advised that such front-end director I8O1-180 32 can transfer the data from the global cache memory 220 to the requesting host computer processor 121 1 -121 32 as described above when there is a cache "read hit".
  • the requesting front-end director 180 ⁇ -180 32 sends a uni- cast message via the message network 260 to only that specific one of the back-end directors 200 ⁇ -200 32 .
  • a multi-cast message (here implemented as a series of uni-cast messages) is sent by the requesting one of the front-end directors I8O 1 - I8O32 to all of the back-end directors 200 ⁇ -200 32 having responsibility for the requested data.
  • a uni-cast or multi-cast message such message is passed through the message network 260 and not through the data transfer section 240 (i.e., not through the global cache memory 220).
  • the acknowledgement signal may be sent to the requesting host computer processor 1211 or one or more other host computer processors 121 ⁇ -121 32 via a multi-cast (i.e., sequence of uni-cast) messages through the message network 260 to complete the data read operation.
  • a multi-cast i.e., sequence of uni-cast
  • the host computer 120 wishes to write data into storage (i.e., into the bank of disk drives 140).
  • One of the front-end directors 180 ⁇ -180 32 receives the data from the host computer 120 and writes it into the global cache memory 220.
  • the front-end director 180 ⁇ -180 32 requests the transfer of such data after some period of time when the back-end director 200r-20 ⁇ 32 determines that the data can be removed from such cache memory 220 and stored in the bank of disk drives 140.
  • the data in the cache memory 220 is tagged with a bit as "fresh data" (i.e., data which has not been transferred to the bank of disk drives 140, that is data which is "write pending").
  • the data is overwritten in the cache memory 220 with the most recent data.
  • the front-end director 180 ⁇ -180 32 controlling the transfer also informs the host computer 120 that the transfer is complete to thereby free-up the host computer 120 for other data transfers.
  • the back-end director 200 1 - 200 32 transfers the data from the global cache memory 220 to the bank of disk drives 140 and resets the tag associated with data in the global cache memory 220 (i.e., un-tags the data) to indicate that the data in the global cache memory 220 has been transferred to the bank of disk drives 140. It is noted that the un-tagged data in the global cache memory 220 remains there until overwritten with new data.
  • the system interface 160 is shown to include an electrical cabinet 300 having stored therein: a plurality of, here eight front-end director boards 190 ⁇ -190 8 , each one having here four of the front-end directors I8O 1 -I8O 32 ; a plurality of, here eight back-end director boards 210 ⁇ -210 8 , each one having here four of the back-end directors 200 ⁇ -200 3 2; and a plurality of, here eight, memory boards MO- M7 which together make up the global cache memory 220.
  • These boards plug into the front side of a backplane 302. (It is noted that the backplane 302 is a mid-plane printed circuit board).
  • Plugged into the backside of the backplane 302 are message network boards which together make up the message network 260 as described in the co-pending patent applications referred to above.
  • the backside of the backplane 302 has plugged into it adapter boards, not shown in FIGS. 2-4, which couple the boards plugged into the backside of the backplane 302 with the computer 120 and the bank of disk drives 140 as shown in FIG. 2.
  • each one of the director boards 190 ⁇ -210 8 includes, as noted above four of the directors I8O1-I8O32, 200 ⁇ -200 32 (FIG. 2).
  • director boards 190 ⁇ -190 8 having four front-end directors per board, I8O 1 -I8O 32 are referred to as front-end directors and the director boards 2101 -210 8 having four back-end directors per board, 200 ⁇ -200 32 are referred to as back-end directors.
  • Each one of the directors I8O 1 - I8O 32 , 200 ⁇ -20 ⁇ 32 includes the microprocessor 299 referred to above), the message engine/CPU controller 314, and the data pipe 316 shown in FIG. 2.
  • the front-end director boards have ports 123 ⁇ -123 3 2, as shown in FIG. 2, coupled to the processors 1211-I2I32, as shown.
  • the back-end director boards have ports 123 3 3-123 64 , as shown in FIG. 2, coupled to the disk drives 1411 - 141 3 2, as shown.
  • Each one of the director boards 190 ⁇ -210 8 includes a crossbar switch 318 as shown in FIG. 5.
  • the crossbar switch 318 has four input/output ports C ⁇ -C , each one being coupled to the data pipe 316 (FIG, 2) of a corresponding one of the four directors I8O1-I8O32, 200 ⁇ -200 32 on the director board 190 ⁇ -210 8 .
  • the crossbar switch 318 has eight output/input ports collectively identified in FIG. 5 by numerical designation 321 (which plug into the backplane 302).
  • the crossbar switch 318 on the front-end director boards 1911-191 8 is used for coupling the data pipe 316 of a selected one of the four front-end directors 180 ⁇ -180 32 on the front-end director board 190 ⁇ -190 8 to the global cache memory 220 via the backplane 302 and I/O adapter, not shown.
  • the crossbar switch 318 on the back-end director boards 210 ⁇ -210 8 is used for coupling the data pipe 316 of a selected one of the four back-end directors 200 ⁇ -200 32 on the back-end director board 210 ⁇ -210 8 to the global cache memory 220 via the backplane 302 and I/O adapter, not shown.
  • the data pipe 316 in the front-end directors 180 ⁇ -180 32 couples data between the host computer 120 and the global cache memory 220 while the data pipe 316 in the back-end directors 200 ⁇ -200 32 couples data between the bank of disk drives 140 and the global cache memory 220.
  • the backplane 302 is a passive backplane because it is made up of only etched conductors on one or more layers of a printed circuit board. That is, the backplane 302 does not have any active components.
  • crossbar switch 320 plugs into the backplane 302 and is used for coupling to the directors to the message network 260 (FIG. 2) through the backplane.
  • the crossbar switch 318 includes a pair of crossbar switches 406X, 406 Y.
  • Each one of the switches 406X, 406Y includes four input/output director-side ports C ⁇ -C 4 and the four input/output memory-side ports collectively designated in FIG. 5 by numerical designation 321.
  • the director-side ports C ⁇ -C 4 of switch 406X are connected to the four directors on the director board, as indicated, and as described in more detail in the co-pending patent applications referred to above.
  • director-side ports C ⁇ -C 4 of switch 406Y are also connected to the dual-ported directors on such board, as indicated.
  • each director is a dual-ported directors.
  • Each one of the ports C ⁇ -C 4 may be coupled to a selected one of the four ports collectively designated by 321 in accordance with control words provided to the switch 406X by the directors on such board, respectively, as described in the above-referenced patent application. Suffice it to say here, that port 402A of any one of the directors I8O1, I8O 3 , I8O5, I8O 7 may be coupled to any one of the ports 321 of switch 406X, selectively in accordance with the control words.
  • the coupling between the director boards 190 ⁇ -190 8 , 210 ⁇ -210 8 and the global cache memory 220 is shown in FIG. 8.
  • switch 406Y More particularly, and referring also to FIG.
  • each one of the host computer processors 121 1 -121 32 in the host computer 120 is coupled to a pair of the front- end directors I8O1-I8O 3 2, to provide redundancy in the event of a failure in one of the front end-directors I8I1-I8I32 coupled thereto.
  • the bank of disk drives 140 has a plurality of, here 32, disk drives 1411-141 32 , each disk drive 141 ⁇ -141 32 being coupled to a pair of the back-end directors 200 ⁇ -200 32 , to provide redundancy in the event of a failure in one of the back-end directors 2OO1-2OO 3 2 coupled thereto).
  • Such processor 121 1 is coupled to a pair of front-end directors I8O1, I8O2.
  • director I8O1 fails, the host computer processor 1211 can still access the system interface 160, albeit by the other front-end director 18O 2 .
  • directors I8O1 and I8O 2 are considered redundancy pairs of directors.
  • other redundancy pairs of front-end directors are: front-end directors I8O 3 , 180 4 ; 180 5 , 180 6> 180 7 , 180 8, 180 9> I8O10; 180 ⁇ , I8O12; I8O.3, 180, 4 , 180 15 , 180 ⁇ 6 .
  • disk drive 141 1 is coupled to a pair of back-end directors 200 ⁇ , 200 2 .
  • director 200 ⁇ fails, the disk drive 141 1 can still access the system interface 160, albeit by the other back-end director 180 2 .
  • directors 200 ⁇ and 200 2 are considered redundancy pairs of directors.
  • FIGS. 2 and 5 there are four directors on each one of the director boards.
  • the physical position of the director boards along with a positional designation, are shown in FIG. 8 (e.g., director board 190] also has the designation D2). Further, referring to FIGS. 2 and 5:
  • Front-end boards are paired to enable achievement of the above-described redundancy:
  • the global cache memory 220 includes a plurality of, here eight, cache memory boards M0-M7, as shown. Still further, referring to FIG. 6, an exemplary one of the cache memory boards is shown. Here, each cache memory board includes four memory array regions 1-4, an exemplary one thereof being shown and described in connection with FIG. 6 of U. S. Patent No. 5,943,287 entitled "Fault Tolerant Memory System", John K. Walton, inventor, issued August 24, 1999 and assigned to the same assignee as the present invention, the entire subject matter therein being incorporated herein by reference. Further detail of the exemplary one of the cache memory boards is described in the co-pending patent applications referred to above.
  • the exemplary memory board includes a plurality of, here four RAM memory array regions 1-4, each one of the array regions has a pair of redundant data/control ports, i.e., an A port and a B port, for receiving data to, or from, the memory array region as well as for receiving memory control signals.
  • the memory board itself has sixteen ports; a set of eight domain A ports P0-P7 and a set of eight domain B ports P 8 -P ⁇ 5 .
  • each memory board has four logic networks (here crossbar switches).
  • logic networks 221 , A , 2212A, 221 ,B, 221 2B are here cross bar switches.
  • Logic networks 221 , A, 221 2 A, and logic networks 221 ,B, 2212B are in two independent domains, i.e., domain A and domain B.
  • logic networks 221 , A , 221 2A are in domain A
  • logic networks 221 , B , 221 2B are in domain B, respectively.
  • logic networks 22 LA, 221 2A , in domain A are designated as Al and A2 respectively
  • logic networks 221 , B , 22l2 ⁇ in domain B are designated as Bl and B2, respectively.
  • These connections between memory boards M0 through M7 and directors DO through DF are in the following Tables I and II, respectively: TABLE I
  • each one of the switches i.e., logic networks Al, A2, Bl and B2 in each domain is connected to a pair of front end director boards a pair of back-end director boards.
  • A i.e., logic network Al
  • two of its port Po andP 2 are connected to one of the front-end director boards while the other two of its ports Pi and P 3 are connected to one of the back-end director boards.
  • FIG. 6A This arrangement balances the loading on any one of the logic networks and thus increases the bandwidth of the system.
  • the four switches are in two independent domains, i.e., domain A and domain B, as shown in FIG. 6.
  • each one of the four A ports P0-P 3 can be coupled to the A port of any one of the memory array regions 1-4 through the logic network 221, A (i.e., Al).
  • A i.e., Al
  • port Po can be coupled to the A port of the four memory array regions 1-4.
  • each one of the four A ports P 4 -P 7 can be coupled to the A port of any one of the memory array regions 1-4 through the logic network 221 2A .
  • each one of the four B ports P 8 -P, ⁇ of logic network 221 IB can be coupled to the B port of any one of the memory array regions 1-4 through logic network 221 , B
  • each one of the four B ports P, 2 -P, 5 can be coupled to the B port of any one of the memory arrays through the logic network 221 2B -
  • port P,2 such port can be coupled to the B port of the four memory array regions 1-4.
  • each one of the directors has a pair of redundant ports, i.e. a 402A port and a 402 B port (FIG. 5). More particularly, referring to FIG. 7, an exemplary pair of redundant directors is shown, here, for example, front-end director 180, and front end-director 180 2 .
  • directors 180 ⁇ , I8O 2 in each redundant pair of directors must be on different director boards, here boards 190, (D2), 190 2 (DD), respectively.
  • front-end director boards 190,-190 8 have thereon: front-end directors 180, , I8O 3 , I8O 5 and 180 7 ; front-end directors 180 2, 180 4 , 180 6 and 180 8 ; front end directors I8O9, 180, ,, 180, 3 and 180, 5 ; front end directors 180, 0, 180, 2 , 180, 4 and 180, 6 ; front-end directors 180 ⁇ , 180, 9 , 180 2 , and 180 23 ; front-end directors 180, 8 , 180 20 , I8O 22 and 180 24 ; front-end directors 18O 2 5, 18O 27 , I8O 2 9 and I8O3,; front-end directors
  • back-end director boards 210,-210 8 have thereon: back-end directors 200,, 200 3 , 200 5 and 200 7 ; back-end directors 200 2 , 200 4 , 200 6 and 200 8 ; back-end directors 200 9 , 200, ,, 200, 3 and 200, 5 ; back-end directors 200, o , 200, 2 , 200, 4 and 200, 6 ; back-end directors 200, 7 , 200, 9 , 200 2 ⁇ and 200 23 ; back-end directors 200, 8> 200 2 o, 2OO 22 and 200 2 ; back-end directors 200 25 , 200 27 , 200 29 and 200 3 ,; back-end directors 200 , 8 , 2OO 2 0, 200 22 and 20 ⁇ 24 as discussed the two tables above.
  • front-end director 180 is on front-end director board 190, (D2) and its redundant, or paired, front-end director I8O 2 , shown in FIG. 7, is on another front-end director board, here for example, front-end director board 190 2 (DD).
  • each director has a pair of ports 402A, 402B, as shown in FIG. 6.
  • Port 402A of the director is connected to switch 406X of crossbar switch 318 and the port 402B of the director is connected to switch 406Y of crossbar switch 318, as shown for director I8O 1 .
  • redundant director I8O2 for redundant director I8O2.
  • the crossbar switch 318 has, as noted above, eight ports collectively referred to by numerical designation 321. These port ports plug into the backplane in the arrangement shown in FIG. 8.
  • the eight ports for each one of the director boards are designated as 0, 1, 2, 3, 4, 5, 6 and 7, as shown.
  • Ports 0, 1, 2 and 3 are ports of the X crossbar switch 406X and ports 4, 5, 6 and 7 are ports of the Y crossbar switch 406Y.
  • the logic in domain A (Al or A2) is connected to one of the redundant pair of director boards while the logic in the domain B (Bl or B2) is connected to the other one of the redundant pair of director boards.
  • logic A2 is connected to director 180, of board D2 while logic Bl of memory board MO is connected to director I8O2 of director board DD.
  • each director can be coupled to different domains of a pair of memory boards.
  • director 180 may be coupled to domain A (here logic A2) of memory board MO through switch 406X and if such switch fails, to domain B (here logic B2) via switch 406Y on such director board DD.
  • each memory is accessible, via one of its domains, to one of a pair of directors and is also accessible, via its other domain, to the other one of the pair of directors.
  • each director is able to access a pair of memory boards. This later arrangement enables a dual write capability. That is, the data in a director may be written into memory boards. That is, with the arrangement shown, a director is able to write the same data into two different memories.
  • director 180, on board D2 can write data into memory M0 via switch 406X on board D2 and can write the same data into its paired memory Ml via switch 406Y on board D2.
  • each one of the paired host computer processors 121,, 121 2 can access the same memory through either one of the paired directors D2, DD.
  • host computer processor 121 can access memory M0 through its paired director board DD.
  • this arrangement applies to the back-end directors as shown in FIG,. 7 for paired back- end directors DO and DF.
  • the slots in the wired backplane for the director printed circuit boards and memory printed circuit boards are shown in FIG. 8.
  • dummy memory boards and dummy directors are inserted into slots of the backplane otherwise occupied.
  • These dummy boards do not have directors or memory arrays but rather have jumpers connected pair of ports of the dummy director board or dummy memory board, as the case may be, to be described.
  • the use of these jumpers achieves the desired redundancy and dual write features described above.
  • the slots in the backplane 302 are shown for a system having only 4 memory boards and eight director boards.
  • memory boards M2, M3, M4 and M 5 are replaced with dummy memory boards used in place of here memory boards M2, M3, M4 and M 5, as shown in FIG. 10.
  • the jumpers are indicated by J, here eight jumpers J1-J8, being used to connect pairs of the memory board ports for each of the dummy memory boards used in place of memory boards M2, M3, M4 and M 5, as shown in FIG. 9.
  • the connections provided by the jumpers for dummy memory boards M2, M3, M4 and M5 are:
  • the slots in the backplane 302 occupied by director boards D9, D6, D8, D7, DB, D4, DA and D5 in a fully populated system are replaced with dummy director boards shown in FIG. 11.
  • the jumpers are indicated by J, here eight jumpers J1-J8, being used to connect pairs of the director board ports for each of the dummy director boards used in place of director boards D9, D6, D8, D7, DB, D4, DA AND D5, as shown in FIG. 12.
  • connections provided by the jumpers for directors boards D9, D6, DB and D4 are: PORT 0 TO PORT 7; PORT 1 TO PORT 6; PORT 2 TO PORT 5; and PORT 3 TO PORT 4 while connections provided by the jumpers for directors boards D8, DA, D7 and D5 are PORT 0 TO PORT 5; PORT 1 TO PORT 4; PORT 2 TO PORT 7; and PORT 3 TO PORT 6. as shown in FIG. 11.
  • each logic network on the memory board is coupled to a pair of front end directors and a pair of back end directors as shown from the TABLES III and IV above.
  • each one of the directors has a pair of redundant ports, i.e., 402A port and 402 B port (FIG. 5).
  • FIG. 13 for the 4 memory/8 director system (referred to as the de-populated system)
  • an exemplary pair of redundant directors is shown, here, for example, front-end director 180, and front end- director I8O 2 .
  • the directors 180,, I8O 2 in each redundant pair of directors are again on different director boards, here boards 190, (D2), 190 2 (DD), respectively.
  • front-end director 180, shown in FIG. 15 is on front-end director board 190, (D2) and its redundant front-end director I8O 2 , shown in FIG.
  • each director has a pair of ports 402A, 402B, as shown in FIG. 15. Port 402A of the director is connected to switch 406X of crossbar switch 318 and the port 402B of the director is connected to switch 406Y of crossbar switch 318, as shown for director 180,. Likewise, for redundant director I8O2.
  • the crossbar switch 318 has, as noted above, eight ports collectively referred to by numerical designation 321. These port ports plug into the backplane in the arrangement shown in FIG.9.
  • the eight ports for each one of the director boards are designated as 0, 1, 2, 3, 4, 5, 6 and 7, as shown.
  • Ports 0, 1, 2 and 3 are ports of the X crossbar switch 406X and ports 4, 5, 6 and 7 are ports of the Y crossbar switch 406Y.
  • director board D2 and paired director board DD are each connected only four memory boards, here memory boards MO, Ml, M6 and M7, as shown.
  • each director can be coupled to different domains of a pair of memory boards.
  • director 180, on director board D2 may be coupled to domain A (here logic A2) of memory board MO through switch 406X and if such switch fails, to domain B (here logic B2) of memory board MO through switch 406 Y on such director board D2.
  • each memory is accessible, via one of its domains, to one of a pair of directors and is also accessible, via its other domain, to the other one of the pair of directors.
  • each director is able to access a pair of memory boards. This later arrangement enables a dual write capability. That is, the data in a director may be written into memory boards. That is, with the arrangement shown, a director is able to write the same data into two different memories.
  • director 180, on board D2 can write data into memory M0 via switch 406X on board D2 and can write the same data into its paired memory Ml via switch 406Y on board D2.
  • each one of the paired host computer processors 121,, 12b can access the same memory through either one of the paired directors D2, DD.
  • host computer processor 121 1 can access memory M0 through its paired director board DD.
  • FIG. 14 a universal dummy (jumper) director board UD is shown.
  • all of the slots in the backplane for the director boards and the memory boards have a unique slot designation. More particularly, the slot designations from left to right are slot 0 through slot 23, as indicated. (This same slot designation applies to the fully populated backplane shown FIG. 8).
  • the backplane has pins, not shown, hardwired to a 5-bit code representative of the slot designation.
  • director DO plugs into slot 0 of the backplane
  • such director receives a binary code 00000.
  • memory board M0 is plugged into slot 8 of the backplane provides the code 01000 to the memory board. And so forth for the other director boards and the memory boards.
  • the universal dummy director i.e., jumper board
  • the universal board has three switches SI, S2, S3, S4 controlled and a decoder.
  • the decoder thereon detects a code indicating that it is plugged into any of the slots: 17 (i.e., a D9 slot); 19 (i.e., a DB slot); slot 6 (i.e., a D6 slot); or slot 4 (i.e., a D4 slot)
  • a logic 1 is produced by the decoder thereby placing the switches SI, S2, S3 and S4, in a type "A" configuration.
  • a logic 0 is produced by the decoder placing the switches SI, S2, S3 and S4 in a type "B" configuration.
  • the switches SI, S2, S3 and S4 connect: port 0 to port 7; port 1 to port 6, port 2 to port 5; and port 3 to port 4, respectively.
  • the switches SI, S2, S3 and S4 connect: port 0 to port 5; port 1 to port 4, port 2 to port 7; and port 3 to port 6, respectively.
  • same universal board UD may be used for any director having jumpers.
  • a universal director board UD may be inserted into slots 4, 5, 6, 7, 16, 17, 18 and 19 and the decoders thereon will automatically active the switches SI, S2, S3, S4 to configure the universal boards to those shown in FIG. 11, described above.
  • the signals passing through the director boards are here positive emitter coupled logic (PECL) signals.
  • PCL positive emitter coupled logic
  • the switches SI, S2 and S3 are also used rebufer these signals.
  • the switches SI, S2 and S3 are model VCS-830 switches by Vitesse Semiconductor Corporation, 741 Calle Piano, Camarillo, CA 93012.

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Abstract

La présente invention porte sur un système de stockage de données servant à transférer des données entre un ordinateur/serveur hôte et une banque de lecteurs de disques. Ce système comprend une face arrière comportant des rainures conçues pour recevoir une pluralité de cartes de circuits imprimés enfichées dans ces rainures. Ces cartes de circuits imprimés comprennent : une pluralité de premières cartes de contrôleurs ; une pluralité de deuxièmes cartes de circuits imprimés ; une pluralité de cartes de circuits imprimés de mémoire ; une pluralité de premières cartes de contrôleurs fictives comprenant des premiers cavaliers ; une pluralité de deuxièmes cartes de contrôleurs fictives comprenant des deuxièmes cavaliers ; ainsi qu'une pluralité de cartes mémoire fictives comprenant des troisièmes cavaliers. Le câblage de la face arrière constitue une connexion entre les premier, deuxième et troisième cavaliers pour interconnecter une première pluralité de contrôleurs à un ordinateur/serveur hôte, la deuxième pluralité de contrôleurs à une banque de lecteurs de disques et une mémoire globale à la première pluralité de contrôleurs et à la deuxième pluralité de contrôleurs.
EP03714385A 2002-03-28 2003-03-25 Systeme de stockage de donnees Withdrawn EP1488315A2 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US10/112,598 US6877061B2 (en) 2000-03-31 2002-03-28 Data storage system having dummy printed circuit boards
US10/109,583 US6907483B1 (en) 2002-03-28 2002-03-28 Data storage system having dummy printed circuit boards with jumpers
US112598 2002-03-28
US109583 2002-03-28
PCT/US2003/009112 WO2003083638A2 (fr) 2002-03-28 2003-03-25 Systeme de stockage de donnees

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JP (1) JP4364650B2 (fr)
WO (1) WO2003083638A2 (fr)

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IL156055A0 (en) 2000-11-30 2003-12-23 Teva Pharma Novel crystal forms of atorvastatin hemi calcium and processes for their preparation as well as novel processes for preparing other forms
GB2412205B (en) * 2004-02-10 2006-02-15 Hitachi Ltd Storage system
WO2008149459A1 (fr) * 2007-06-08 2008-12-11 Fujitsu Limited Dispositif de stockage et procédé de commande
US20140149785A1 (en) * 2011-10-25 2014-05-29 M. Scott Bunker Distributed management

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DE1130482B (de) * 1961-03-07 1962-05-30 Standard Elektrik Lorenz Ag Zwischenleitungsanordnung fuer die Koppelblocks zweier oder mehrerer Koppelstufen inFernmelde-, insbesondere Fernsprechvermittlungsanlagen
US4575780A (en) * 1984-04-03 1986-03-11 Northern Telecom Limited Backpanel assemblies
GB9117745D0 (en) * 1991-08-15 1991-10-02 Bicc Plc Circuit board connector
US7010575B1 (en) * 2000-03-31 2006-03-07 Emc Corporation Data storage system having separate data transfer section and message network having bus arbitration

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JP4364650B2 (ja) 2009-11-18
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