EP1449245A2

EP1449245A2 - Capacitor and a method for producing a capacitor

Info

Publication number: EP1449245A2
Application number: EP02803774A
Authority: EP
Inventors: Carsten Ahrens; Wolfgang Hartung; Christian Herzum; Reinhard Losehand; Angelika Geiselbrechtinger
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2001-11-30
Filing date: 2002-11-14
Publication date: 2004-08-25
Also published as: AU2002356602A1; WO2003046974A2; US20050013090A1; CN100423211C; DE10158798A1; WO2003046974A3; US7030457B2; CN1596463A

Abstract

The invention relates to a capacitor comprising a semiconductor substrate (114), in which a trench (112a, 112b), which is used to dope the substrate, is formed. A dielectric layer (118) covers the surface of the trench (112a, 112b) and an electrically conductive material (120a, 120b) is also located in the trench. In addition, a first contact structure (126) for electrically contacting the electrically conductive material (126) in the trench (112a, 112b) and a second contact structure (130) for electrically contacting the doped semiconductor substrate (114) are formed in the capacitor. The electrodes of the latter exhibit a low series resistance and said capacitor can be produced in a simple manner.

Description

description

Capacitor and method of making a capacitor

The present invention relates to capacitors, and more particularly to capacitors integrated into a semiconductor substrate.

Integrated capacitors are an important part of many semiconductor devices or integrated circuits. For example, integrated capacitors are used in PIN switches or microphone filters. In addition, integrated capacitors in memory cells are used in conjunction with a transistor to store digital information in the memory cell.

To have a high area capacity, i.e. Trench capacitors in which the capacitor is accommodated in a trench of the substrate are used for a small consumption of a chip area per delivered capacity to maintain the capacitors on the chip. By using trenches, the depth of the substrate is used to provide areas for forming the capacitors, which results in a high area capacity.

For example, EP-0 479 143 AI describes a trench capacitor DRAM memory with voltage field isolation. The trench capacitor has a plurality of capacitor plates that are separated by a dielectric in the trench that is formed in a substrate. Both capacitor plates, which are formed from doped semiconductor material, are accommodated in the trench and extend as thin layers from the trench. Another layer located closest to the side wall of the trench acts as a field shielding layer. A plurality of sacrificial layers are used and are formed over the structure. The other plate of the trench capacitor is also over a connection layer is connected to a source / drain region of a transistor.

The known trench capacitor described above has capacitor plates which are designed as thin layers, since both the first and the second capacitor plate are located in the trench. This is disadvantageous in that very high doping levels are required to achieve low series resistances for the capacitor plates formed as thin semiconductor layers. Furthermore, the application of the layers is associated with a high outlay. In addition to the capacitor dielectric, electrical insulation is applied to the side walls of the trench.

The object of the present invention is to create a simple and inexpensive capacitor.

This object is achieved by a capacitor according to claim 1 and a method according to claim 17.

The present invention is based on the finding that a capacitor with low area consumption and low series resistance is obtained in a semiconductor substrate by providing a trench in the semiconductor substrate, the surface of which is covered with a dielectric layer, and an electrically conductive material in the trench, so that a first electrode of the capacitor is formed by the electrically conductive material and is electrically conductively contacted via a first contact structure and a second electrode of the capacitor is formed by the semiconductor substrate and is electrically conductively contacted by means of a second contact structure. The semiconductor substrate is a doped starting substrate with low ohmic resistance or preferably an undoped semiconductor substrate which has been doped by the trenches. An advantage of the present invention is that only one layer, ie the dielectric layer, has to be applied in the trench. In particular, by using the semiconductor substrate as an electrode, an insulating layer in addition to the dielectric layer for insulating the trench is not necessary according to the invention. This leads to a simple manufacturing process.

Furthermore, the capacitor according to the invention has a low value due to the arrangement of the capacitor in a trench

Consumption of one chip area per delivered capacity.

A further advantage of the invention consists in a low series resistance of the capacitor, since the doped semiconductor substrate is used as a capacitor electrode and a trench filling, which is used as another capacitor electrode, can be made wide, since only the trench filling and the dielectric layer are in the trench is arranged.

Furthermore, with the capacitor according to the invention, there is the possibility that both electrode contacts extend on one side of the substrate. This avoids costly rear-side contact.

A further advantage is the possibility of using a high-resistance substrate which can be doped locally with the trench, the use of a high-resistance substrate to produce isolation from adjacent circuit parts which are arranged on the substrate, is not necessary. Furthermore, ohmic losses due to electromagnetic coupling are minimized.

A preferred exemplary embodiment of the present invention has, in addition to the trench which is provided for supplying a capacitance, at least one dummy trench, in the vicinity of which the second contact structure for electrically Conductive contacting the doped semiconductor substrate is arranged. The “capacitor trench” and the additional dummy trench are preferably used to dope an undoped semiconductor substrate in one production step.

Due to the doping of the semiconductor substrate by means of the at least one dummy trench, which is also filled like the capacitor trench with electrically conductive material, the doping of the semiconductor substrate in the vicinity of the trench is particularly good. Providing the capacitor trench in the vicinity of the dummy trench ensures that a particularly low-resistance region of the semiconductor substrate can be reached, which results in a low series resistance of the capacitor.

In a first preferred exemplary embodiment, the first and the second contact structure are designed as conductive plugs, which extend on the same side of the substrate, wherein they are connected to a first and second conductor structure, which are designed as fingers, and are arranged interdigitally in one layer are. This has the advantage that no rear contact is required.

In a further preferred exemplary embodiment, the first contact structure is connected to a first conductor structure which is arranged in a first plane. In this exemplary embodiment, the second contact structure is also connected via an intermediate conductor structure to a second conductor structure, the intermediate conductor structure being arranged in the plane of the first conductor structure and being located between the second conductor structure and the substrate. This offers the advantage that rear-side contacting is not required, and the capacitor can also be easily integrated into known circuit designs when designing a circuit structure. Preferred exemplary embodiments of the present invention are explained in more detail below with reference to the accompanying drawings. Show it:

1 shows a cross-sectional illustration of a first preferred exemplary embodiment along a sectional area A-B;

Fig. 2 is a top view of the embodiment of Fig. 1;

3 shows a cross-sectional illustration of a second preferred exemplary embodiment along a sectional area A-B; and

FIG. 4 is a top view of the embodiment of FIG. 3.

1 shows, as a first preferred exemplary embodiment, a lateral capacitor 110 which has two trenches 112a and 112b in a substrate 114. The figure shows a section, the substrate extending further in the horizontal direction over the section shown in FIG. 1, as is explained in more detail in FIG.

Two dummy trenches 116a and 116b are also formed in the substrate 114. A dielectric layer 118 is formed on the surface of the trenches 112a, 112b and 116a, 116b. Furthermore, a dielectric layer 118a extends between the trenches 112a and 112b on a surface of the substrate 114. The substrate 114 preferably has a monocrystalline semiconductor material which, via the trenches 112a, 112b, 116a, 116b, has a dopant concentration of greater than 10 ¹⁸ cm ^" ³ and preferably greater than 10 ²⁰ cm ^{-3 was} highly doped in order to obtain high electrical conductivity in an area of the trenches. Preferably, a silicon um-substrate Si0 ₂ , silicon nitride, or ONO (oxide-nitride-oxide stack) as a dielectric layer, since it is easy to produce and has good adhesion to silicon. The trenches 112a and 112b have a filling material 120a and 12b in their interior, a layer 120c of the same filling material extending beyond the surface of the substrate 114, so that the two filling material regions 120a and 120b are conductively connected to one another via the layer 120c. Likewise, filler layers 122a and 122b are formed from the same filler material in trenches 116a and 116b. The filler material preferably consists of polycrystalline silicon, since it has a high electrical conductivity and good adhesion to a dielectric layer made of SiO ₂ and is also easy to apply using known silicon technology, although any other electrically conductive material can be used as the filler material.

The trenches 112a, 112b, 116a, 116b are preferably formed in a cylindrical shape, since this can be easily achieved using known etching methods, although they can have different shapes in other exemplary embodiments. The trenches 112a, 112b, 116a, 116b are preferably arranged in a regular pattern, as will be explained in more detail with reference to FIG. 2.

A layer 124a of metal silicide is formed on the filler material layer 120c by a process of self-assembly of silicide (Seif Aligned Silicide Process). Likewise, layers 124b and 124c of metal silicide are formed on the surface of the substrate 114 on the filler material regions 122a and 122b of the dummy trenches 116a and 116b. Furthermore, a layer of metal silicide 124d is formed on the surface of the substrate between layers 124b and 124c. Layer 124a of metal silicide serves to provide good electrical contact for filler layer 120c, which is with filler regions 120a and 120b, which is a first Form electrode of the capacitor, is electrically conductively connected. For this purpose, the silicide layer 124a is electrically conductively connected to a conductor structure 128c via a conductive plug 126, which is arranged above the silicide layer 124.

Furthermore, the silicide layer 124d serves to provide good electrical contact for the semiconductor substrate, which serves as a second electrode, the silicide layer 124d being connected to a second conductor structure 132c via a plug 130. The first conductor structure 128c and the second conductor structure 132c are arranged in one plane, the same being electrically insulated from one another by insulating regions 133 made of SiO ₂ . Furthermore, the plugs 126 and 130 are preferably cylindrical and made of tungsten and are located in a layer 134 of oxide material which is formed between the plane of the first 128c and second 132c conductor structure and the layer 124 or the surface of the substrate 114. As a result, the layer 124 has a step shape due to the elevated position of the layer 124a.

Furthermore, a spacer 136 is formed on the step formed by the filler material layer 120c and the layer 124a, which is preferably made of TEOS material (TEOS = tetraethyl orthosilicate). The spacer 136 serves to electrically isolate the layer 124a in the critical region of the step formed from the substrate 114 and to prevent electrical breakdown. In this exemplary embodiment, the conductor structures 128 and 132 are preferably finger-shaped and arranged interdigitally in order to obtain a low series resistance, as will be explained in more detail below with reference to FIG. 2.

The mode of operation of the present capacitor will now be explained in more detail with reference to FIG. 1. The semiconductor substrate, which is connected to the conductor structures via the plugs 130, has a high doping, wherein the Doping is produced in a manufacturing step via the trenches 112 and 116, as will be explained in more detail below. Consequently, the semiconductor substrate serves as a first electrode of the capacitor according to the invention, a low series resistance being achieved due to the fact that the semiconductor substrate is highly doped over the trenches. Furthermore, the series resistance is further minimized and the inductance is low because the plug 130 is directly connected to the conductor structure 132 with a short length.

The conductive filler regions 120a and 120b, which are electrically insulated from the semiconductor substrate via the dielectric layer 118, act as a counter electrode to the semiconductor substrate. The counter electrode formed in this way likewise has a low series resistance and a low inductance, since it is connected to the conductor structure 128 via a short path. Since the trenches 112a and 112b only comprise the filler material regions 112a and 112b and the dielectric layer 118, which is typically thin, the filler material regions 112a and 112b can extend approximately over the entire width of the trench, which results in a large conductor cross section and together with the fact that the filler material has a high conductivity material such as polysilicon also contributes to a low electrical resistance of the filler material regions 112a and 112b, respectively.

By positioning the plug 130 close to the trenches 112a, 112b, which act as capacitor trenches, an electrical path in the substrate from the plug 130 to the trenches 112a, 112b is reduced, this having a favorable effect on the electrical resistance.

Consequently, the capacitor has low electrical series resistances of the electrodes, so it is suitable for use in integrated filter circuits. It should be mentioned at this point that the dummy trenches 116a and 116b in the exemplary embodiment shown are only used to dope the substrate in a doping step and have no function for supplying a capacitance. This makes it possible to use a high-resistance substrate which is selectively doped over the trenches in a doping step, as a result of which it is not necessary to produce isolations, as is necessary in the case of a doped output substrate to isolate adjacent circuit parts.

FIG. 2 shows a top view of the exemplary embodiment from FIG. 1, the sectional plane A-B, which corresponds to the representation from FIG. 1, being represented by a line with the reference symbol 137. Fig. 2 shows a plan view taken from the plane in which the conductor structures are arranged. FIG. 2 shows four conductor structures 128a, 128b, 128c and 128d which are designed as fingers and are arranged interdigitally with conductor structures 132a, 132b and 132c, the same being insulated from one another by insulating regions 133. Furthermore, the trenches 112 and 116, which are each shown in a circle, are arranged in a regular pattern. The trenches 116, which are designed as dummy trenches, are each arranged in arrangements 138a, 138b, 138c, 138d, 138e and 138f, each arrangement comprising three dummy trenches 116. In the arrangements 138a-f, the trenches 116 are each arranged approximately in the shape of an equilateral triangle, a plug 130 being located in the middle thereof. The plug 130 provides the electrical connection of the conductor structures 132a, 132b and

132c with the substrate 140 as explained with reference to FIG. 1 above. The arrangements 138a-f are preferably evenly distributed over the surface, so that the conductor paths in the substrate from the respective plugs 130 to the "capacitor trenches" 112 are kept small. This is advantageous in order to achieve a low electrical resistance since the substrate, although it is highly doped, and therefore has good conductivity, has lower conductivity compared to metallic conductor tracks and therefore makes a significant contribution to electrical resistance.

Other arrangements and patterns of the trenches or conductor structures can also be used to achieve low series resistances. The arrangement shown in FIG. 2 offers the advantage of a simple design and manufacture of the capacitor.

Furthermore, those trenches 112 which are arranged below the conductor structures 128a, 128b, 128c and 128d have the plugs 126 in order to be electrically conductive around the conductor structures 128a-128d with the filler material layers of the trenches 112, for example the filler material layer 120c according to FIG. 1 connect to. It should be noted at this point that, although trenches 112 are disposed above the conductor structures 132a-132c, they have no electrical connection to the conductor structures 132a-132c. Rather, these trenches 112 are connected to the plugs 126 and therefore to the conductor structures 128a-128d via filler material layers, such as the filler material layer 120c according to FIG. 1.

Consequently, the conductor structures 132a, 132b and 132c represent conductor structures which have an electrical connection to the substrate via plugs 132. The conductor structures 128a-128d likewise represent connection lines which are electrically connected to the conductive filler material regions of the trenches 112.

A second preferred embodiment of the present invention will now be explained with reference to FIG. 3. Corresponding to the exemplary embodiment according to FIG. 1, a capacitor 310 has two trenches 312a and 312b and two dummy trenches 316a and 316b. There are also filler areas

320a and 320b or 322a and 322b each electrically via a dielectric layer 318 from a semiconductor substrate 314 isolated. The filler material regions 320a and 320b are electrically connected to one another via a filler material layer 320c. A layer 324a of metal silicide is also formed on the filler material layer 320c in accordance with the exemplary embodiment according to FIG. 1. Furthermore, layers 324b and 324c made of metal silicide are formed on the filling material regions 322a and 322b. Another layer 324d of metal silicide is formed on the surface of the substrate 314 between layers 324b and 324c.

In contrast to the exemplary embodiment according to FIG. 1, this exemplary embodiment has a design with a two-layer metallization. The filler material layer 320c is connected to a conductor structure 328 via plugs 326a and 326b. Furthermore, the doped semiconductor substrate 314 is connected to an intermediate conductor structure 331 via the silicide layer 324d and a plug 330. The intermediate conductor structure 331 is arranged in the same plane as the conductor structure 328 and is electrically insulated from the same over a region made of SiO ₂ . On the conductor structure 328 and the intermediate conductor structure 331, a layer of insulating material, such as SiO ₂ , is formed, which electrically insulates a conductor structure 332 arranged above it from the conductor structure 328. According to FIG. 3, the conductor structure 332 has a first region 332a and a second region 332b which are electrically insulated from one another by an insulation region which is formed, for example, from SiO ₂ . The conductor structure region 332b is electrically conductively connected to the intermediate conductor structure 331 via through holes 340a and 340b.

1 shows a layer 334 between the plane of the conductor structures 328, 331 and the substrate or the filler material layer 320c, a layer 334 with a step. Layer 334 is preferably formed from an oxide material. The exemplary embodiment also shows corresponding to the exemplary embodiment according to FIG. 1, a spacer 336, which is arranged at a step which is formed by the filler material layer 320c. According to the exemplary embodiment in FIG. 1, a first electrode is formed by the semiconductor substrate, while a second electrode is formed by the filler material regions 322a and 322b. Corresponding to the exemplary embodiment of FIG. 1, the dummy trenches 316a and 316b are only used to dope the high-resistance substrate in a doping step and have no function for supplying a capacitance.

A plan view of the exemplary embodiment according to FIG. 3 will now be explained with reference to FIG. 4. The upper layer, which includes the conductor structure, is drawn transparently in order to be able to represent the underlying structures. The section surface along which the side view of FIG. 3 is taken is represented by a line with the reference symbol 337 from point A to point B.

4 shows three conductor structures 332a, 332b and 332c, which are arranged in the uppermost metallization level. According to the exemplary embodiment in FIG. 2, the trenches 312 and 316 are arranged in a regular pattern. A through hole 340 is assigned to each of the dummy trenches 316. The intermediate conductor structure 331 has six intermediate conductor structure regions which are insulated from one another and arranged in an island-like manner, the through holes 340 connecting the conductor structures 332a-c to a region of the intermediate conductor structure 331 in each case. In each case three of the dummy trenches 316 are combined to form arrangements 338a-338f, each of the arrangements 338a-f being associated with an intermediate conductor structure 331 which is electrically insulated from the conductor structure 328 in the plane of the first metallization. The three dummy trenches 316 of an arrangement are arranged approximately in the form of an equilateral triangle, with intermediate conductor structure regions 331a-f, the same in each case are assigned, have a triangular shape. Each of the intermediate conductor structure regions 331a-f is electrically connected to the semiconductor substrate via a conductive plug, which is arranged in the middle of the three dummy trenches of an arrangement. Consequently, each of the conductor structures 332a-332c is connected via the intermediate conductor structure regions 331a-f in the first metallization level to the semiconductor substrate, which acts as an electrode of the capacitor. The conductor structures of the first and second metallization levels are preferably formed from copper.

Furthermore, in this exemplary embodiment, each filler material region of a trench 312 is connected to the conductor structure 328 in the first metallization level via a conductive plug 326. As can be seen in Fig. 4, the first

Metallization level, the conductor structure 328 is electrically insulated from the intermediate conductor structure regions, which are in the form of a triangle, via insulation regions 242. The arrangement of the conductor structures 328 and the conductor structure 332 on different metallization levels makes it possible in this exemplary embodiment that the conductor structures 328 and 332 can each be formed over a large area, as a result of which an electrical series resistance is reduced. It should be noted again at this point that the illustration in FIG. 4 is kept transparent, so that the structures of the trenches 312, 316 as well as the levels of the first metallization level and the second metallization level can be seen.

The regular grouping of the arrangements 338a-f shown so that they are surrounded by trenches 312 has the advantage that the connection paths in the substrate to a respective capacitor trench are kept short, so that a low series resistance is achieved. Furthermore, the arrangement of the trenches 316 into trench groups has the advantage that a high doping step in the area thereof he doping can be achieved, so that this also reduces the series resistance.

Since correspondingly long current paths through the substrate result from arranging the connection paths on the same side of the substrate, which current paths are determined by the distance of the plugs 330 from the capacitor trenches 312, a high doping of the substrate is necessary in order to achieve a low resistance , This is achieved by doping over the trenches.

Although six arrangements, each comprising 3 dummy trenches, are shown in the exemplary embodiments shown, the number of arrangements 338a-f and the number of dummy trenches in an arrangement 338a-f are not limited to a specific number. Rather, in other exemplary embodiments, more or fewer than six arrangements 338a-f can be provided with a certain number of dummy trenches. The arrangements 338a-f are preferably arranged in a regular pattern, which makes it easier to design and produce them, although non-regular arranged arrangements are also provided in other exemplary embodiments. Likewise, the trenches 112 and 116 can also be arranged in a non-regular shape.

Furthermore, in an alternative exemplary embodiment, instead of grouping dummy trenches 316 into arrangements, the trenches 312 can be grouped adjacent to one another in island-like arrangements.

A preferred method for producing a capacitor will now be explained in more detail with reference to FIG. 1 again.

In a first manufacturing step, the trenches 112a, 112b, 116a and 116b are formed in the undoped semiconductor substrate, which is preferably formed from monocrystalline silicon an etching step according to known techniques. Phosphorus doping of the semiconductor substrate 114 is then carried out through the surface of the trenches 112a, 112b, 116a and 116b into the substrate. For this purpose, a phosphor-doped layer is produced on the surface of the trenches 112a, 112b, 116a and 116b in a first step using PC1 ₃ . In a subsequent step, the chip is heated in order to cause diffusion of phosphorus as doping material into the substrate. In a next step, the phosphorus-doped layer on the surface of the trenches 112a, 112b, 116a and 116b is removed by etching with HF. The removal of the phosphorus-doped layer is carried out because it has poor dielectric properties compared to other known dielectrics. A typical doping that is achieved in this doping step comprises a range greater than 10 ¹⁸ cm ^"3 and preferably greater than 10 ²⁰ cm ^{" 3} . Using the trenches for doping ensures that high doping can be achieved in order to minimize the series electrode resistance of the capacitor to be produced, which is formed by the substrate. Furthermore, the doping of an undoped semiconductor substrate offers the advantage that additional production steps, as are required in the case of a doped output semiconductor substrate in order to achieve isolation of adjacent circuit parts, are not required.

In a next step, the dielectric layer 118 is deposited on the surface of the trenches 112a, 112b, 116a and 116b formed and in a region between the trenches 112a and 112b on the surface of the substrate. The filler material is then deposited into the trenches 112a, 112b, 116a and 116b by deposition, the deposited filler material also being deposited as a layer on the surface of the substrate 114. The filler material can be a material that is already conductive in the deposition step or a non-conductive material that is made conductive only after the deposition. Preferably a filler layer made of polysilicon is used to obtain a high electrical conductivity. Other fillers, such as tungsten, can also be used.

The filler layer on the surface of the substrate and the dielectric layer on the surface of the substrate are then partially, i.e. in the areas of the dummy trenches 116a and 116b, using known photolithography and etching methods, until the substrate is etched, so that in the area of the dummy trenches 116a and 116b and in the area between the dummy trench 116a and the adjacent one Trench 112b the layer of filler material and the dielectric layer is removed.

The etching of the filler material and the dielectric up to the doped substrate in the region of the dummy trenches enables the electrode contacts to be pulled across the semiconductor substrate with a low resistance to the same side as the contacting of the filler material of the capacitor trench 112.

In a subsequent step, a silicide-forming metal is deposited in order to produce a good contact layer and is brought to a silicide reaction with the silicon underneath, so that a metal silicide is thereby formed. This step preferably comprises forming TiSi ₂ .

The next step is to remove the spacer 136 by depositing TEOS material (TEOS = tetraethyl ortho

Silicate) and a subsequent anisotropic etch so that at the step formed on layer 120c, spacer 136 is formed in the shape of a triangle.

An intermediate oxide layer (ZOX layer) is then deposited and, in a subsequent step, a planarian Sation subjected so that the surface of the intermediate oxide layer has a flat structure and is parallel to the 0- surface of the substrate.

In a subsequent step, the contact holes 126 and 130, which form the connection structure, are etched into the ZOX layer, the etching being carried out using known methods in such a way that a selective etching stop takes place on the silicide layer. The contact holes 126 and 130 are then filled with an electrically conductive material, which preferably comprises tungsten.

In a next step, chemical mechanical polishing is carried out in order to obtain a planarization of step discontinuities for the subsequent metallization steps. In a subsequent metallization step, the conductor structures 128c and 132c are applied in accordance with known methods.

It should be noted that in this preferred method, the introduced dummy trenches 116 only serve to provide a surface for the diffusion of the dopant material, the materials applied therein, ie the filler material and the dielectric layer, in the dummy trenches no useful function Have capacitor element.

LIST OF REFERENCE NUMBERS

110 capacitor

112 trench

112a trench

112b trench

114 substrate 116 dummy trench

116a dummy trench

116b dummy trench

118 dielectric layer

120a filler area 120b filler area

120c filler layer

122a filler area

122b filler area

124a-d layer 126 plugs

128 ladder structure

130 plugs

132 ladder structure

134 layer 136 spacers

137 line

138 arrangement 310 capacitor 312 trench 312a trench

312b trench

314 substrate

316 dummy trench

316a dummy trench 316b dummy trench

318 dielectric layer

320a filler area 320b filler area 320c filler layer 322a filler area 322b filler area 324a-d layer

328 ladder structure

330 plugs

331 intermediate conductor structure 331a-f intermediate conductor structure 332 conductor structure 334 layer

336 spacers

337 line

338 arrangement 340 through hole 340a through hole 340b through hole 342 isolation area

Claims

claims

1. Capacitor with the following features:

a doped semiconductor substrate (114; 314);

a trench (112, 112a, 112b; 312, 312a, 312b) in the semiconductor substrate (114; 314);

a dielectric layer (118; 318) covering a surface of the trench (112, 112a, 112b; 312, 312a, 312b);

an electrically conductive material (120a, 120b; 320a, 320b) in the trench (112, 112a, 112b; 312, 312a, 312b);

a first contact structure (126; 326) for electrically conductive contacting of the electrically conductive material (120a, 120b; 320a, 320b) in the trench (112, 112a, 112b; 312, 312a, 312b); and

a second contact structure (130; 330) for electrically conductive contacting of the doped semiconductor substrate (114; 314).

2. The capacitor of claim 1, wherein the semiconductor substrate (114, 314) is a high impedance semiconductor substrate doped around the trench.

3. Capacitor according to one of claims 1 or 2, in which, in addition to the one trench (112, 112a, 112b; 312, 312a, 312b), further trenches (112, 112a, 112b; 312, 312a, 312b) are formed.

4. Capacitor according to one of claims 1 to 3, in which, in addition to the one trench (112, 112a, 112b; 312, 312a, 312b), a dummy trench (116, 116a, 116b; 316, 316a, 316b) is formed, wherein the second contact structure (130; 330) contacts the substrate (114; 314) in the vicinity of the dummy trench (116, 116a, 116b; 316, 316a, 316b) in an electrically conductive manner.

5. The capacitor as claimed in claim 4, in which, in addition to the one dummy trench (116, 116a, 116b; 316, 316a, 316b), a further dummy trench (116, 116a, 116b; 316, 316a, 316b) is formed, wherein the second contact structure (130; 330) the substrate (114; 314) between the one dummy trench (116, 116a, 116b; 316, 316a, 316b) and the further dummy trench (116, 116a, 116b; 316, 316a, 316b) electrically conductively contacted.

6. A capacitor according to any one of claims 1 to 5, wherein an electrically insulating spacer (136; 336) is formed on the surface of the substrate (114; 314) to increase a dielectric strength.

7. A capacitor according to any one of claims 1 to 6, wherein the first (126; 326) and second (130; 330) contact structure extend on the same side of the substrate (114; 314).

8. The capacitor according to any one of claims 1 to 7, wherein the first contact structure (126; 326) has conductive plugs which are formed in an insulating layer (134; 334) which extends over the trenches (112, 112a, 112b; 312 , 312a, 312b) and dummy trenches (116, 116a, 116b; 316, 316a, 316b).

9. A capacitor according to any one of claims 1 to 8, wherein the second contact structure (130; 330) has conductive plugs which are formed in an insulating layer (134; 334) which extends over the trenches (112, 112a, 112b; 312 , 312a, 312b) and the dummy trenches (116, 116a, 116b; 316, 316a, 316b).

10. A capacitor according to any one of claims 1 to 9, wherein the first contact structure (126; 326) with a first conductor Structure (128a-d; 328) is electrically conductively connected and the second contact structure (130; 330) is electrically conductively connected to a second conductor structure (132a-c; 332a-c).

11. The capacitor of claim 10, wherein the first (128a-d) and second (132a-c) conductor structure are arranged in a plane that is parallel to a surface of the substrate.

12. The capacitor of claim 11, wherein the first (128a-d) and second (132a-c) conductor structure have a finger structure, the same being arranged interdigitally.

13. The capacitor of claim 10, wherein the first conductor structure (328) in a first plane parallel to one

Surface of the substrate is arranged, while the second conductor structure (332a-c) is arranged in a second plane which is parallel to a surface of the substrate.

14. The capacitor according to claim 13, wherein a conductive intermediate conductor structure (331), which is electrically insulated from the first conductor structure (328), is formed in the plane of the first conductor structure (328), the second conductor structure (332a -c) is arranged such that the plane of the first conductor structure (328) is arranged between the plane of the second conductor structure (332a-c) and the substrate (314), and wherein the second conductor structure (332a-c) is furthermore via conductive through holes (340a-b) is electrically conductively connected to the intermediate conductor structure.

15. The capacitor according to one of claims 1 to 14, in which, in addition to the one trench (112, 112a, 112b), a plurality of trenches (112, 112a, 112b) and a plurality of dummy trenches (116, 116a, 116b) are formed, wherein the one and the plurality of trenches (112, 112a, 112b) and the plurality of dummy trenches (116, 116a, 116b) are arranged in a regular pattern, and wherein Dummy trenches (116) are combined to form arrangements (138a-f).

16. The capacitor of claim 14, wherein the intermediate conductor structure comprises a plurality of intermediate conductor structure regions

(331a-f), wherein in addition to the one trench (312), a plurality of further trenches (312) and in addition to the one dummy trench (316), a plurality of further dummy trenches (316) are formed, and wherein dummy trenches ( 116) are combined to form arrangements (338a-f), with each of the several intermediate

An arrangement (338a-f) is assigned to the conductor structure areas.

17. A method of manufacturing a capacitor comprising the following steps:

Providing a semiconductor substrate (114; 314);

Creating a trench (112, 112a, 112b; 312, 312a, 312b) in the substrate (114, 314);

Doping the semiconductor substrate (114; 314) over the trench (112, 112a, 112b; 312, 312a, 312b);

Creating a dielectric layer (118; 318) on a surface of the trench (112, 112a, 112b; 312, 312a, 312b);

Introducing a filler material (120a, 120b; 320a, 320b) into the trench (112, 112a, 112b; 312, 312a, 312b), the filler material being electrically conductive before it is introduced or being made electrically conductive after it has been introduced;

Generating a first contact structure (126; 326) for electrically conductive contacting of the electrically conductive material (120a, 120b; 320a, 320b) and a second contact Structure (130; 330) for electrically conductive contacting of the semiconductor substrate (114; 314).

18. The method of claim 17, wherein the step of doping the substrate (114; 314) over the trench (112, 112a,

112b; 312, 312a, 312b) comprises a diffusion of a dopant.

19. The method of claim 18, wherein the step of doping the substrate (114; 314) further comprises the following steps:

Creating a phosphorus-doped silicate layer in the trench; and

Warm to diffuse phosphorus as a dopant from the phosphorus-doped silicate layer into the substrate.

20. The method according to any one of claims 17 to 19, further comprising the step of producing an electrically insulating spacer (136; 336) for increasing a dielectric strength on the surface of the substrate (114; 314).

21. The method of claim 20, wherein the step of producing an electrically insulating spacer (136;

336) comprises anisotropic etching of the electrically insulating spacer (136; 336).

22. The method according to any one of claims 17 to 21, further comprising the following steps:

Creating a dummy trench (116, 116a, 116b; 316, 316a, 316b) in the semiconductor substrate (114, 314);

Doping the substrate (114; 314) over the dummy trench (116, 116a, 116b; 316, 316a, 316b); Creating a dielectric layer (118; 318) on a surface of the dummy trench (116, 116a, 116b; 316, 316a, 316b);

Introducing a filler material (122a, 122b; 322a, 322b) into the dummy trench (116, 116a, 116b; 316, 316a, 316b), the filler material being electrically conductive before it is introduced or being made electrically conductive after it has been introduced;

23. The method according to any one of claims 17 to 22, wherein the step of generating a first contact structure (126; 326) for electrically conductive contacting the electrically conductive material (120a, 120b; 320a, 320b) and a second contact structure (130; 330 ) for electrically conductive contacting of the semiconductor substrate (114; 314) comprises generating a silicide layer (124a-d; 324a-d) on the filling material (120a, 120b; 320a, 320b) and on a surface of the semiconductor substrate (114; 314).

24. The method of claim 23, wherein the step of producing a first contact structure comprises the step of depositing an intermediate oxide layer on a surface of the semiconductor substrate (114; 314) and subsequently etching the intermediate oxide layer so that the intermediate oxide layer is removed in places, wherein the silicide layer acts as a selective etch stop during the etch.

25. The method according to any one of claims 17 to 24, wherein the semiconductor substrate is a high-resistance semiconductor substrate.