EP1446887A1 - Verfahren zum transferieren von daten - Google Patents

Verfahren zum transferieren von daten

Info

Publication number
EP1446887A1
EP1446887A1 EP02804002A EP02804002A EP1446887A1 EP 1446887 A1 EP1446887 A1 EP 1446887A1 EP 02804002 A EP02804002 A EP 02804002A EP 02804002 A EP02804002 A EP 02804002A EP 1446887 A1 EP1446887 A1 EP 1446887A1
Authority
EP
European Patent Office
Prior art keywords
data block
data
bits
nibble
block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP02804002A
Other languages
English (en)
French (fr)
Other versions
EP1446887A4 (de
Inventor
Joseph Gredone
Alfred Stufflet
Timothy A. Axness
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
InterDigital Technology Corp
Original Assignee
InterDigital Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/990,060 external-priority patent/US7069464B2/en
Application filed by InterDigital Technology Corp filed Critical InterDigital Technology Corp
Publication of EP1446887A1 publication Critical patent/EP1446887A1/de
Publication of EP1446887A4 publication Critical patent/EP1446887A4/de
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver

Definitions

  • a hybrid serial/parallel bus interface has a data block demultiplexing device.
  • the data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles.
  • a parallel to serial converter converts the nibble into serial data.
  • a line transfers each nibble's serial data.
  • a serial to parallel converter converts each nibble's serial data to recover that nibble.
  • a data block reconstruction device combines the recovered nibbles into the data block.
  • Figure 13 is a table of an implementation of start bits indicating destinations.
  • Figure 14 is a table of an implementation of start bits indicating de stinations/functions .
  • Figure 17 is a block diagram for a positive and negative clock edge hybrid parallel/serial bus interface.
  • FIG. 7 is a simplified diagram of one implementation of bidirectional switching circuits.
  • the serial output from the node 1 P/S converter 68 is input into a tri-statable buffer 78.
  • the buffer 78 has another input coupled to a voltage representing a high state.
  • the output of the buffer 78 is the serial data which is sent via the line 85 to a Node 2 tri-statable buffer 84.
  • a resistor 86 is coupled between the line 85 and ground.
  • the Node 2 buffer 84 passes the serial data to a Node 2 S/P converter 72.
  • some of the i lines 44 may transfer data in one direction and the other i lines 44 transfer data in another direction.
  • a data block is received for transmission to Node 2 52.
  • j being a value from 1 to i, of the connections are used to transfer the block.
  • the block is broken into j nibbles and converted to j sets of serial data using j of the i P/S converters 68.
  • a corresponding number of j Node 2 S/P converters 72 and the Node 2 data block separation and reconstruction device 76 recovers the data block.
  • up to i-j or k lines are used to transfer block data.
  • the start bits of the data block reconstruction device 48 After receipt of the start bits of the data block reconstruction device 48, the reconstructed block is sent to the corresponding device 88- 92. To increase the number of potential destination devices, additional start bits may be used. For n starting bits over each of i lines, up to i n + x - 1 devices are selected. [0042] As illustrated in the table of Figure 14, the start bits may be used to represent both function and destination device.
  • Figure 14 shows a three connection system having two devices, such as a RX and TX GC. Using the start bit for each line, three functions for two devices is shown. In this example, the start bit for line 3 represents the target device, a "0" for device 1 and a "1" for device 2.
  • the bits for connections 2 and 3 represent the performed function.
  • FIG. 17 An odd P/S device set 102, having i P/S devices, has its clock signal inverted by an invertor 118. As a result, the inverted clock signal is half a clock cycle delayed with respect to the system clock.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
EP02804002A 2001-11-21 2002-11-19 Verfahren zum transferieren von daten Ceased EP1446887A4 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US990060 2001-11-21
US09/990,060 US7069464B2 (en) 2001-11-21 2001-11-21 Hybrid parallel/serial bus interface
US80480 2002-02-22
US10/080,480 US6823468B2 (en) 2001-11-21 2002-02-22 Method employed by a user equipment for transferring data
PCT/US2002/037142 WO2003047113A1 (en) 2001-11-21 2002-11-19 Method of transferring data

Publications (2)

Publication Number Publication Date
EP1446887A1 true EP1446887A1 (de) 2004-08-18
EP1446887A4 EP1446887A4 (de) 2005-05-04

Family

ID=26763576

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02804002A Ceased EP1446887A4 (de) 2001-11-21 2002-11-19 Verfahren zum transferieren von daten

Country Status (9)

Country Link
EP (1) EP1446887A4 (de)
JP (1) JP4027894B2 (de)
CN (1) CN100435487C (de)
AU (1) AU2002365555A1 (de)
CA (1) CA2467847A1 (de)
MX (1) MXPA04004740A (de)
NO (1) NO20042547L (de)
TW (1) TWI239742B (de)
WO (1) WO2003047113A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003046738A1 (en) * 2001-11-21 2003-06-05 Interdigital Technology Corporation Method employed by a base station for transferring data
CN100419686C (zh) * 2006-12-13 2008-09-17 北京中星微电子有限公司 一种实现数据下载的方法、系统及装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5327126A (en) * 1992-06-26 1994-07-05 Hewlett-Packard Company Apparatus for and method of parallel justifying and dejustifying data in accordance with a predetermined mapping
JPH06334537A (ja) * 1993-05-21 1994-12-02 Fujitsu Ltd 不確定性除去機能付きシリアル／パラレル変換回路
CN2254192Y (zh) * 1995-10-27 1997-05-14 姜波 多功能高精度电度表
US5926120A (en) * 1996-03-28 1999-07-20 National Semiconductor Corporation Multi-channel parallel to serial and serial to parallel conversion using a RAM array
CN2276694Y (zh) * 1996-04-27 1998-03-18 厦门科华俐发展有限公司 一种有线电视的加扰和解扰装置
US6040792A (en) * 1997-11-19 2000-03-21 In-System Design, Inc. Universal serial bus to parallel bus signal converter and method of conversion

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
"DS90CR211/DS90CR212 21-Bit Channel Link" July 1997 (1997-07), NATIONAL SEMICONDUCTOR , SANTA CLARA, CALIFORNIA, USA , XP002306540 Retrieved from the Internet: URL:http://www.national.com/ds/DS/DS90CR21 1.pdf> * pages 1-2; figure 13 * *
LOGUE J: "Virtex SelectLink Communications Channel" 15 March 2000 (2000-03-15), XILINX INC. , SAN JOSE, CALIFORNIA, USA , XP002318012 Retrieved from the Internet: URL:http://www.xilinx.com/bvdocs/appnotes/ xapp234.pdf> * page 10; table 8 * *
NOVAK T ET AL: "Channel Link - Moving and Shaping Information In Point-toPoint Applications" May 1996 (1996-05), NATIONAL SEMICONDUCTOR , SANTA CLARA, CALIFORNIA, USA , XP002306541 Retrieved from the Internet: URL:http://www.national.com/an/AN/AN-1041. pdf> * pages 1-2; figures 1-5 * *
See also references of WO03047113A1 *
VON HERZEN B ET AL: "Multi-Channel 622 Mb/s LVDS Data Transfer for Virtex-E Devices" 6 January 2001 (2001-01-06), XILINX INC. , SAN JOSE, CALIFORNIA, USA , XP002306542 Retrieved from the Internet: URL:http://direct.xilinx.com/bvdocs/appnot es/xapp233.pdf> * pages 1-5; figures 1-3,6 * *

Also Published As

Publication number Publication date
EP1446887A4 (de) 2005-05-04
CA2467847A1 (en) 2003-06-05
WO2003047113A1 (en) 2003-06-05
JP4027894B2 (ja) 2007-12-26
CN100435487C (zh) 2008-11-19
JP2005510816A (ja) 2005-04-21
TWI239742B (en) 2005-09-11
MXPA04004740A (es) 2004-08-02
TW200304314A (en) 2003-09-16
CN1589531A (zh) 2005-03-02
AU2002365555A1 (en) 2003-06-10
NO20042547L (no) 2004-07-29

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