EP1417605A4 - Systeme logique insensible aux defaillances et aux problemes de synchronisation et procede associe - Google Patents

Systeme logique insensible aux defaillances et aux problemes de synchronisation et procede associe

Info

Publication number
EP1417605A4
EP1417605A4 EP01967980A EP01967980A EP1417605A4 EP 1417605 A4 EP1417605 A4 EP 1417605A4 EP 01967980 A EP01967980 A EP 01967980A EP 01967980 A EP01967980 A EP 01967980A EP 1417605 A4 EP1417605 A4 EP 1417605A4
Authority
EP
European Patent Office
Prior art keywords
timing
logic system
free logic
glitch
insensitive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01967980A
Other languages
German (de)
English (en)
Other versions
EP1417605A1 (fr
Inventor
Ping-Sheng Tseng
Sharon Sheau-Pyng Lin
Quincy Kun-Hsu Shen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cadence Design Systems Inc
Original Assignee
Verisity Design Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Verisity Design Inc filed Critical Verisity Design Inc
Priority claimed from PCT/US2001/025546 external-priority patent/WO2003017148A1/fr
Publication of EP1417605A1 publication Critical patent/EP1417605A1/fr
Publication of EP1417605A4 publication Critical patent/EP1417605A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Debugging And Monitoring (AREA)
EP01967980A 2001-08-14 2001-08-14 Systeme logique insensible aux defaillances et aux problemes de synchronisation et procede associe Withdrawn EP1417605A4 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2001/025546 WO2003017148A1 (fr) 1997-05-02 2001-08-14 Systeme logique insensible aux defaillances et aux problemes de synchronisation et procede associe

Publications (2)

Publication Number Publication Date
EP1417605A1 EP1417605A1 (fr) 2004-05-12
EP1417605A4 true EP1417605A4 (fr) 2009-07-15

Family

ID=21742774

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01967980A Withdrawn EP1417605A4 (fr) 2001-08-14 2001-08-14 Systeme logique insensible aux defaillances et aux problemes de synchronisation et procede associe

Country Status (6)

Country Link
EP (1) EP1417605A4 (fr)
JP (1) JP4125675B2 (fr)
KR (1) KR20040028599A (fr)
CN (1) CN100578510C (fr)
CA (1) CA2420022A1 (fr)
IL (2) IL154480A0 (fr)

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JP4561459B2 (ja) 2004-04-30 2010-10-13 ヤマハ株式会社 Ｄ級増幅器
KR101282963B1 (ko) * 2006-05-12 2013-07-08 삼성전자주식회사 에뮬레이션 시스템 및 그 방법
CN102057360B (zh) * 2008-11-19 2014-01-22 Lsi股份有限公司 使用自定时的时分复用总线的互连
US8742791B1 (en) * 2009-01-31 2014-06-03 Xilinx, Inc. Method and apparatus for preamble detection for a control signal
US10423740B2 (en) * 2009-04-29 2019-09-24 Synopsys, Inc. Logic simulation and/or emulation which follows hardware semantics
CN102422263B (zh) * 2009-05-07 2016-03-30 赛普拉斯半导体公司 开发、编程和除错环境
US8942628B2 (en) * 2011-11-28 2015-01-27 Qualcomm Incorporated Reducing power consumption for connection establishment in near field communication systems
CN102799709B (zh) * 2012-06-19 2015-04-01 中国电子科技集团公司第二十八研究所 基于xml的系统仿真试验环境构建与配置系统及方法
KR101354007B1 (ko) * 2012-12-12 2014-01-21 국방과학연구소 시뮬레이션 시간을 기반으로 시뮬레이션 시스템과 테스트 시스템의 시간 진행을 동기화하는 시스템 간 연동 구성 및 시뮬레이션 모델 테스트 방법
KR101704600B1 (ko) 2014-10-31 2017-02-08 한국전기연구원 홀센서 글리치 제거 장치
US10289579B2 (en) * 2015-12-10 2019-05-14 Qualcomm Incorporated Digital aggregation of interrupts from peripheral devices
EP3399425B1 (fr) * 2017-05-05 2020-07-29 dSPACE digital signal processing and control engineering GmbH Procédé destiné à la détection d'une topologie de câblage
CN109960593B (zh) * 2017-12-26 2023-02-17 中国船舶重工集团公司七五〇试验场 一种互锁式时序控制仿真方法
CN108537000B (zh) * 2018-03-27 2021-07-27 东南大学 基于分子计算的米利型状态机设计方法
EP3579126A1 (fr) * 2018-06-07 2019-12-11 Kompetenzzentrum - Das virtuelle Fahrzeug Forschungsgesellschaft mbH Procédé et dispositif de co-simulation
KR20210065964A (ko) * 2018-09-25 2021-06-04 시놉시스, 인크. 에뮬레이션 및 프로토타이핑에서 오버레이된 클록 및 데이터 전파의 코히어런트 관찰가능성 및 제어가능성
CN109683512B (zh) * 2018-12-07 2022-04-12 四川航天烽火伺服控制技术有限公司 一种应用于舵系统的转接卡
US10454459B1 (en) 2019-01-14 2019-10-22 Quantum Machines Quantum controller with multiple pulse modes
US11164100B2 (en) 2019-05-02 2021-11-02 Quantum Machines Modular and dynamic digital control in a quantum controller
US10931267B1 (en) 2019-07-31 2021-02-23 Quantum Machines Frequency generation in a quantum controller
US11245390B2 (en) 2019-09-02 2022-02-08 Quantum Machines Software-defined pulse orchestration platform
US10862465B1 (en) 2019-09-02 2020-12-08 Quantum Machines Quantum controller architecture
CN112445743B (zh) * 2019-09-04 2024-03-22 珠海格力电器股份有限公司 一种去除毛刺的方法、装置及状态机
CN111479334B (zh) * 2020-03-20 2023-08-11 深圳赛安特技术服务有限公司 一种网络请求重试方法、装置及终端设备
CN111581149B (zh) * 2020-04-24 2022-08-26 希翼微电子(嘉兴)有限公司 可重构地址重映射低功耗多功能定时器
US11132486B1 (en) * 2020-05-21 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Systems and methods for multi-bit memory with embedded logic
US11043939B1 (en) 2020-08-05 2021-06-22 Quantum Machines Frequency management for quantum control
CN112269728B (zh) * 2020-11-03 2023-08-04 北京百度网讯科技有限公司 一种系统性能评估方法、装置、设备以及存储介质
CN112328701B (zh) * 2020-11-27 2023-11-10 广东睿住智能科技有限公司 数据同步方法、终端设备及计算机可读存储介质
CN113158260B (zh) * 2021-03-30 2023-03-31 西南电子技术研究所（中国电子科技集团公司第十研究所） SoC芯片内部数据分级防护电路
CN112733478B (zh) * 2021-04-01 2021-08-03 芯华章科技股份有限公司 用于对设计进行形式验证的装置
CN113297819B (zh) * 2021-06-22 2023-07-07 海光信息技术股份有限公司 异步时钟的时序检查方法、装置、电子设备、存储介质
JPWO2023281652A1 (fr) * 2021-07-07 2023-01-12
US20230153678A1 (en) * 2021-07-21 2023-05-18 Quantum Machines System and method for clock synchronization and time transfer between quantum orchestration platform elements
CN114841103B (zh) * 2022-07-01 2022-09-27 南昌大学 门级电路的并行仿真方法、系统、存储介质及设备
CN116882336B (zh) * 2023-09-07 2023-12-01 芯动微电子科技(珠海)有限公司 一种基于高级语言模拟rtl的建模方法与装置

Citations (3)

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US5748911A (en) * 1996-07-19 1998-05-05 Compaq Computer Corporation Serial bus system for shadowing registers
US5831866A (en) * 1996-05-31 1998-11-03 Mentor Graphics Corporation Method and apparatus for removing timing hazards in a circuit design
US6134516A (en) * 1997-05-02 2000-10-17 Axis Systems, Inc. Simulation server system and method

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* Cited by examiner, † Cited by third party
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US6009256A (en) * 1997-05-02 1999-12-28 Axis Systems, Inc. Simulation/emulation system and method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5831866A (en) * 1996-05-31 1998-11-03 Mentor Graphics Corporation Method and apparatus for removing timing hazards in a circuit design
US5748911A (en) * 1996-07-19 1998-05-05 Compaq Computer Corporation Serial bus system for shadowing registers
US6134516A (en) * 1997-05-02 2000-10-17 Axis Systems, Inc. Simulation server system and method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO03017148A1 *

Also Published As

Publication number Publication date
CA2420022A1 (fr) 2003-02-27
CN1491394A (zh) 2004-04-21
KR20040028599A (ko) 2004-04-03
JP4125675B2 (ja) 2008-07-30
IL154480A0 (en) 2003-09-17
IL154480A (en) 2008-11-26
CN100578510C (zh) 2010-01-06
JP2005500625A (ja) 2005-01-06
EP1417605A1 (fr) 2004-05-12

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