IL154480A0 - Timing-sensitive glitch-free logic system and method - Google Patents
Timing-sensitive glitch-free logic system and methodInfo
- Publication number
- IL154480A0 IL154480A0 IL15448001A IL15448001A IL154480A0 IL 154480 A0 IL154480 A0 IL 154480A0 IL 15448001 A IL15448001 A IL 15448001A IL 15448001 A IL15448001 A IL 15448001A IL 154480 A0 IL154480 A0 IL 154480A0
- Authority
- IL
- Israel
- Prior art keywords
- glitch
- sensitive
- timing
- logic system
- free logic
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Debugging And Monitoring (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2001/025546 WO2003017148A1 (en) | 1997-05-02 | 2001-08-14 | Timing-insensitive glitch-free logic system and method |
Publications (1)
Publication Number | Publication Date |
---|---|
IL154480A0 true IL154480A0 (en) | 2003-09-17 |
Family
ID=21742774
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IL15448001A IL154480A0 (en) | 2001-08-14 | 2001-08-14 | Timing-sensitive glitch-free logic system and method |
IL154480A IL154480A (en) | 2001-08-14 | 2003-02-16 | Timing-sensitive glitch-free logic system and method |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IL154480A IL154480A (en) | 2001-08-14 | 2003-02-16 | Timing-sensitive glitch-free logic system and method |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP1417605A4 (en) |
JP (1) | JP4125675B2 (en) |
KR (1) | KR20040028599A (en) |
CN (1) | CN100578510C (en) |
CA (1) | CA2420022A1 (en) |
IL (2) | IL154480A0 (en) |
Families Citing this family (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4561459B2 (en) | 2004-04-30 | 2010-10-13 | ヤマハ株式会社 | Class D amplifier |
KR101282963B1 (en) * | 2006-05-12 | 2013-07-08 | 삼성전자주식회사 | Emulation system and method thereof |
JP5731391B2 (en) * | 2008-11-19 | 2015-06-10 | エルエスアイ コーポレーション | Interconnection using self-timed time division multiplexed buses |
US8587337B1 (en) * | 2009-01-31 | 2013-11-19 | Xilinx, Inc. | Method and apparatus for capturing and synchronizing data |
US10423740B2 (en) * | 2009-04-29 | 2019-09-24 | Synopsys, Inc. | Logic simulation and/or emulation which follows hardware semantics |
CN102422263B (en) * | 2009-05-07 | 2016-03-30 | 赛普拉斯半导体公司 | Exploitation, programming and debugging environment |
US8942628B2 (en) * | 2011-11-28 | 2015-01-27 | Qualcomm Incorporated | Reducing power consumption for connection establishment in near field communication systems |
CN102799709B (en) * | 2012-06-19 | 2015-04-01 | 中国电子科技集团公司第二十八研究所 | System simulation test environment building and configuring system and method based on extensive markup language (XML) |
KR101354007B1 (en) * | 2012-12-12 | 2014-01-21 | 국방과학연구소 | Interfacing system synchronizing a time process of a simulation system and a test system based on simulation time and test method for simulation model |
KR101704600B1 (en) | 2014-10-31 | 2017-02-08 | 한국전기연구원 | Glitch removal device for hall-sensor |
US10289579B2 (en) * | 2015-12-10 | 2019-05-14 | Qualcomm Incorporated | Digital aggregation of interrupts from peripheral devices |
EP3399425B1 (en) * | 2017-05-05 | 2020-07-29 | dSPACE digital signal processing and control engineering GmbH | Method for detecting wiring topology |
CN109960593B (en) * | 2017-12-26 | 2023-02-17 | 中国船舶重工集团公司七五〇试验场 | Interlocking type time sequence control simulation method |
CN108537000B (en) * | 2018-03-27 | 2021-07-27 | 东南大学 | Milli-type state machine design method based on molecular calculation |
EP3579126A1 (en) * | 2018-06-07 | 2019-12-11 | Kompetenzzentrum - Das virtuelle Fahrzeug Forschungsgesellschaft mbH | Co-simulation method and device |
CN112753034B (en) * | 2018-09-25 | 2024-03-12 | 美商新思科技有限公司 | Hardware simulation system control block and method for controlling hardware simulation of circuit design |
CN109683512B (en) * | 2018-12-07 | 2022-04-12 | 四川航天烽火伺服控制技术有限公司 | Adapter card applied to rudder system |
US10454459B1 (en) | 2019-01-14 | 2019-10-22 | Quantum Machines | Quantum controller with multiple pulse modes |
US10505524B1 (en) | 2019-03-06 | 2019-12-10 | Quantum Machines | Synchronization in a quantum controller with modular and dynamic pulse generation and routing |
US11164100B2 (en) | 2019-05-02 | 2021-11-02 | Quantum Machines | Modular and dynamic digital control in a quantum controller |
US10931267B1 (en) | 2019-07-31 | 2021-02-23 | Quantum Machines | Frequency generation in a quantum controller |
US11245390B2 (en) | 2019-09-02 | 2022-02-08 | Quantum Machines | Software-defined pulse orchestration platform |
US10862465B1 (en) | 2019-09-02 | 2020-12-08 | Quantum Machines | Quantum controller architecture |
CN112445743B (en) * | 2019-09-04 | 2024-03-22 | 珠海格力电器股份有限公司 | Burr removing method, device and state machine |
CN111479334B (en) * | 2020-03-20 | 2023-08-11 | 深圳赛安特技术服务有限公司 | Network request retry method and device and terminal equipment |
CN111581149B (en) * | 2020-04-24 | 2022-08-26 | 希翼微电子(嘉兴)有限公司 | Reconfigurable address remapping low-power consumption multifunctional timer |
US11132486B1 (en) * | 2020-05-21 | 2021-09-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Systems and methods for multi-bit memory with embedded logic |
US11043939B1 (en) | 2020-08-05 | 2021-06-22 | Quantum Machines | Frequency management for quantum control |
CN112269728B (en) * | 2020-11-03 | 2023-08-04 | 北京百度网讯科技有限公司 | System performance evaluation method, device, equipment and storage medium |
CN112328701B (en) * | 2020-11-27 | 2023-11-10 | 广东睿住智能科技有限公司 | Data synchronization method, terminal device and computer readable storage medium |
CN113158260B (en) * | 2021-03-30 | 2023-03-31 | 西南电子技术研究所(中国电子科技集团公司第十研究所) | Hierarchical protection circuit of SoC chip internal data |
CN112733478B (en) * | 2021-04-01 | 2021-08-03 | 芯华章科技股份有限公司 | Apparatus for formal verification of a design |
CN113297819B (en) * | 2021-06-22 | 2023-07-07 | 海光信息技术股份有限公司 | Timing sequence checking method and device of asynchronous clock, electronic equipment and storage medium |
JPWO2023281652A1 (en) * | 2021-07-07 | 2023-01-12 | ||
US20230153678A1 (en) * | 2021-07-21 | 2023-05-18 | Quantum Machines | System and method for clock synchronization and time transfer between quantum orchestration platform elements |
CN114841103B (en) * | 2022-07-01 | 2022-09-27 | 南昌大学 | Parallel simulation method, system, storage medium and equipment for gate-level circuit |
CN116882336B (en) * | 2023-09-07 | 2023-12-01 | 芯动微电子科技(珠海)有限公司 | Modeling method and device based on high-level language simulation RTL |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5801955A (en) * | 1996-05-31 | 1998-09-01 | Mentor Graphics Corporation | Method and apparatus for removing timing hazards in a circuit design |
US5748911A (en) * | 1996-07-19 | 1998-05-05 | Compaq Computer Corporation | Serial bus system for shadowing registers |
US6009256A (en) * | 1997-05-02 | 1999-12-28 | Axis Systems, Inc. | Simulation/emulation system and method |
US6134516A (en) * | 1997-05-02 | 2000-10-17 | Axis Systems, Inc. | Simulation server system and method |
-
2001
- 2001-08-14 KR KR10-2003-7002219A patent/KR20040028599A/en not_active Application Discontinuation
- 2001-08-14 CN CN01822790A patent/CN100578510C/en not_active Expired - Fee Related
- 2001-08-14 IL IL15448001A patent/IL154480A0/en active IP Right Grant
- 2001-08-14 EP EP01967980A patent/EP1417605A4/en not_active Withdrawn
- 2001-08-14 JP JP2003521985A patent/JP4125675B2/en not_active Expired - Fee Related
- 2001-08-14 CA CA002420022A patent/CA2420022A1/en not_active Abandoned
-
2003
- 2003-02-16 IL IL154480A patent/IL154480A/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CN100578510C (en) | 2010-01-06 |
CN1491394A (en) | 2004-04-21 |
JP4125675B2 (en) | 2008-07-30 |
JP2005500625A (en) | 2005-01-06 |
KR20040028599A (en) | 2004-04-03 |
CA2420022A1 (en) | 2003-02-27 |
EP1417605A1 (en) | 2004-05-12 |
IL154480A (en) | 2008-11-26 |
EP1417605A4 (en) | 2009-07-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FF | Patent granted | ||
KB | Patent renewed |