EP1417605A4 - Timing-insensitive glitch-free logic system and method - Google Patents

Timing-insensitive glitch-free logic system and method

Info

Publication number
EP1417605A4
EP1417605A4 EP01967980A EP01967980A EP1417605A4 EP 1417605 A4 EP1417605 A4 EP 1417605A4 EP 01967980 A EP01967980 A EP 01967980A EP 01967980 A EP01967980 A EP 01967980A EP 1417605 A4 EP1417605 A4 EP 1417605A4
Authority
EP
European Patent Office
Prior art keywords
timing
logic system
free logic
glitch
insensitive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01967980A
Other languages
German (de)
French (fr)
Other versions
EP1417605A1 (en
Inventor
Ping-Sheng Tseng
Sharon Sheau-Pyng Lin
Quincy Kun-Hsu Shen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cadence Design Systems Inc
Original Assignee
Verisity Design Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Verisity Design Inc filed Critical Verisity Design Inc
Priority claimed from PCT/US2001/025546 external-priority patent/WO2003017148A1/en
Publication of EP1417605A1 publication Critical patent/EP1417605A1/en
Publication of EP1417605A4 publication Critical patent/EP1417605A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Debugging And Monitoring (AREA)
EP01967980A 2001-08-14 2001-08-14 Timing-insensitive glitch-free logic system and method Withdrawn EP1417605A4 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2001/025546 WO2003017148A1 (en) 1997-05-02 2001-08-14 Timing-insensitive glitch-free logic system and method

Publications (2)

Publication Number Publication Date
EP1417605A1 EP1417605A1 (en) 2004-05-12
EP1417605A4 true EP1417605A4 (en) 2009-07-15

Family

ID=21742774

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01967980A Withdrawn EP1417605A4 (en) 2001-08-14 2001-08-14 Timing-insensitive glitch-free logic system and method

Country Status (6)

Country Link
EP (1) EP1417605A4 (en)
JP (1) JP4125675B2 (en)
KR (1) KR20040028599A (en)
CN (1) CN100578510C (en)
CA (1) CA2420022A1 (en)
IL (2) IL154480A0 (en)

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JP4561459B2 (en) 2004-04-30 2010-10-13 ヤマハ株式会社 Class D amplifier
KR101282963B1 (en) * 2006-05-12 2013-07-08 삼성전자주식회사 Emulation system and method thereof
US8503482B2 (en) * 2008-11-19 2013-08-06 Lsi Corporation Interconnects using self-timed time-division multiplexed bus
US8742791B1 (en) * 2009-01-31 2014-06-03 Xilinx, Inc. Method and apparatus for preamble detection for a control signal
US10423740B2 (en) * 2009-04-29 2019-09-24 Synopsys, Inc. Logic simulation and/or emulation which follows hardware semantics
CN102422263B (en) * 2009-05-07 2016-03-30 赛普拉斯半导体公司 Exploitation, programming and debugging environment
US8942628B2 (en) * 2011-11-28 2015-01-27 Qualcomm Incorporated Reducing power consumption for connection establishment in near field communication systems
CN102799709B (en) * 2012-06-19 2015-04-01 中国电子科技集团公司第二十八研究所 System simulation test environment building and configuring system and method based on extensive markup language (XML)
KR101354007B1 (en) * 2012-12-12 2014-01-21 국방과학연구소 Interfacing system synchronizing a time process of a simulation system and a test system based on simulation time and test method for simulation model
KR101704600B1 (en) 2014-10-31 2017-02-08 한국전기연구원 Glitch removal device for hall-sensor
US10289579B2 (en) * 2015-12-10 2019-05-14 Qualcomm Incorporated Digital aggregation of interrupts from peripheral devices
EP3399425B1 (en) * 2017-05-05 2020-07-29 dSPACE digital signal processing and control engineering GmbH Method for detecting wiring topology
CN109960593B (en) * 2017-12-26 2023-02-17 中国船舶重工集团公司七五〇试验场 Interlocking type time sequence control simulation method
CN108537000B (en) * 2018-03-27 2021-07-27 东南大学 Milli-type state machine design method based on molecular calculation
EP3579126A1 (en) * 2018-06-07 2019-12-11 Kompetenzzentrum - Das virtuelle Fahrzeug Forschungsgesellschaft mbH Co-simulation method and device
WO2020069009A1 (en) * 2018-09-25 2020-04-02 Synopsys, Inc. Coherent observability and controllability of overlaid clock and data propagation in emulation and prototyping
US10333503B1 (en) 2018-11-26 2019-06-25 Quantum Machines Quantum controller with modular and dynamic pulse generation and routing
CN109683512B (en) * 2018-12-07 2022-04-12 四川航天烽火伺服控制技术有限公司 Adapter card applied to rudder system
US10454459B1 (en) 2019-01-14 2019-10-22 Quantum Machines Quantum controller with multiple pulse modes
US10505524B1 (en) 2019-03-06 2019-12-10 Quantum Machines Synchronization in a quantum controller with modular and dynamic pulse generation and routing
US11164100B2 (en) 2019-05-02 2021-11-02 Quantum Machines Modular and dynamic digital control in a quantum controller
US10931267B1 (en) 2019-07-31 2021-02-23 Quantum Machines Frequency generation in a quantum controller
US10862465B1 (en) 2019-09-02 2020-12-08 Quantum Machines Quantum controller architecture
US11245390B2 (en) 2019-09-02 2022-02-08 Quantum Machines Software-defined pulse orchestration platform
CN112445743B (en) * 2019-09-04 2024-03-22 珠海格力电器股份有限公司 Burr removing method, device and state machine
CN111479334B (en) * 2020-03-20 2023-08-11 深圳赛安特技术服务有限公司 Network request retry method and device and terminal equipment
CN111581149B (en) * 2020-04-24 2022-08-26 希翼微电子(嘉兴)有限公司 Reconfigurable address remapping low-power consumption multifunctional timer
US11132486B1 (en) * 2020-05-21 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Systems and methods for multi-bit memory with embedded logic
US11043939B1 (en) 2020-08-05 2021-06-22 Quantum Machines Frequency management for quantum control
CN112269728B (en) * 2020-11-03 2023-08-04 北京百度网讯科技有限公司 System performance evaluation method, device, equipment and storage medium
CN112328701B (en) * 2020-11-27 2023-11-10 广东睿住智能科技有限公司 Data synchronization method, terminal device and computer readable storage medium
CN113158260B (en) * 2021-03-30 2023-03-31 西南电子技术研究所（中国电子科技集团公司第十研究所） Hierarchical protection circuit of SoC chip internal data
CN112733478B (en) * 2021-04-01 2021-08-03 芯华章科技股份有限公司 Apparatus for formal verification of a design
CN113297819B (en) * 2021-06-22 2023-07-07 海光信息技术股份有限公司 Timing sequence checking method and device of asynchronous clock, electronic equipment and storage medium
WO2023281652A1 (en) * 2021-07-07 2023-01-12 日本電信電話株式会社 Reconfigurable circuit device
US20230153678A1 (en) * 2021-07-21 2023-05-18 Quantum Machines System and method for clock synchronization and time transfer between quantum orchestration platform elements
US12111352B2 (en) 2022-01-24 2024-10-08 Quantum Machines Machine learning for syncing multiple FPGA ports in a quantum system
CN114841103B (en) * 2022-07-01 2022-09-27 南昌大学 Parallel simulation method, system, storage medium and equipment for gate-level circuit
CN116882336B (en) * 2023-09-07 2023-12-01 芯动微电子科技(珠海)有限公司 Modeling method and device based on high-level language simulation RTL

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5748911A (en) * 1996-07-19 1998-05-05 Compaq Computer Corporation Serial bus system for shadowing registers
US5831866A (en) * 1996-05-31 1998-11-03 Mentor Graphics Corporation Method and apparatus for removing timing hazards in a circuit design
US6134516A (en) * 1997-05-02 2000-10-17 Axis Systems, Inc. Simulation server system and method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6009256A (en) * 1997-05-02 1999-12-28 Axis Systems, Inc. Simulation/emulation system and method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5831866A (en) * 1996-05-31 1998-11-03 Mentor Graphics Corporation Method and apparatus for removing timing hazards in a circuit design
US5748911A (en) * 1996-07-19 1998-05-05 Compaq Computer Corporation Serial bus system for shadowing registers
US6134516A (en) * 1997-05-02 2000-10-17 Axis Systems, Inc. Simulation server system and method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO03017148A1 *

Also Published As

Publication number Publication date
CN100578510C (en) 2010-01-06
JP4125675B2 (en) 2008-07-30
CN1491394A (en) 2004-04-21
JP2005500625A (en) 2005-01-06
IL154480A0 (en) 2003-09-17
KR20040028599A (en) 2004-04-03
IL154480A (en) 2008-11-26
EP1417605A1 (en) 2004-05-12
CA2420022A1 (en) 2003-02-27

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