Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/44—Arrangements for executing specific programs
  • G06F9/4401—Bootstrapping

Definitions

• the present invention relates to the field of electronic systems and operation of electronic systems and more particularly to booting of electronic systems and bringing electronic systems into a sleep-mode.
• the software load management process is used in a computer node operating in a distributed computing environment and is used to permit the computer to initialize its software load image when the computer is first booted. After the computer is turned on, the operating system is initialized. Following this, an application initialization module that is part of the loader, proceeds in registering the software entities, such as any software sub-systems as mail domains, etc. in the software load and starting their execution.
• the registration process involves searching a symbol table for a registration trigger that is in the form of a certain registration procedure name.
• Each software subsystem includes a registration procedure, and the name of that procedure is placed in the symbol table.
• the name of the registration procedure includes a generic component to enable the application initialization module to identify the entry from other entries in the symbol table.
• ECU electronice control units
• FLASH memories allow simplified software version upgrade on one hand, and on the other hand allow to download new software, applications and resulting services on demand - a fact becoming gaining importance in the e-business driven world. For these reasons FLASH memory is becoming a major cost factor for embedded systems.
• Fig. 1 shows a block diagram of a prior art smart phone 1.
• the smart phone 1 has a cell phone sub-system 2, a personal digital assistant (PDA) sub-system 3 and a global positioning system (GPS) sub-system 4.
• the cell phone sub-system 2 has a cell phone engine 5 which is based on a digital signal processing unit.
• the cell phone engine 5 can work in multiple modes of operations such as in a GSM, GPRS and / or UMTS - mode.
• the cell phone engine 5 is coupled to FLASH memory 6 and to RAM 7.
• the FLASH memory 6 is a nonvolatile memory device and contains the software code including the operating system for the cell phone sub-system 2.
• the RAM 7 mainly serves to store variables and data generated and to be altered throughout the system runtime. Therefore the RAM 7 typically is a volatile storage device, such as a SDRAM.
• the PDA sub-system 3 has a PDA system processor 8 which is coupled to FLASH memory 9 and RAM 10. Further the PDA system processor 8 is coupled to human-machine interface 11, which comprises a touch screen and to mass storage 12 which can be a smart media, such as a FLASH card, or an IBM micro drive unit.
• human-machine interface 11 which comprises a touch screen
• mass storage 12 which can be a smart media, such as a FLASH card, or an IBM micro drive unit.
• GPS sub-system 4 has a GPS receiver 13 which is coupled to FLASH memory 14 and RAM 15.
• the FLASH memories 9 and 14 serve for storing the software including the operation system of the PDA sub-system 3 and the GPS sub-system 4, respectively.
• the operation of the cell phone sub-system 2 the PDA sub-system 3 and the GPS sub-system 4 is autonomous and independent of each other.
• a data request from one sub-system to another sub-system is handled by the receiving sub-system as an external request.
• Such requests and corresponding data can be interchanged via busses 16 and 17.
• a disadvantage of the prior art smart phone 1 is that the FLASH memories 6 , 9 and 14 need to be of the NOR-type for storage of the executable code. Such NOR-FLASH memories are a major cost factor for such an electronic system.
• the invention allows to store the boot-images of the individual sub-systems of an electronic system in an inexpensive memory device. For starting system operation the individual boot-images are loaded to the sub-system, such that the normal system operation can immediately start without having to start separate boot-programs . This allows to reduce the overall code size and therefore the physical size of the electronic system, which is of particular importance for portable and handheld devices .
• the invention is particularly beneficial for applications in so called loosely coupled multi processing architectures of the kind as depicted in Fig. 1.
• the boot-images are loaded into individual storage sub-system before the start of the normal system operation.
• Usage of the invention for loosely coupled multi processing architecture results in a significant cost advantage and increase of efficiency.
• the invention allows to safe a substantial amount of power, especially in the so called sleep-mode.
• the invention allows to partly or completely disable or stop the operation of the processors of the individual sub-systems .
• even the refreshing of the SDRAMs of the individual sub-systems can be discontinued.
• Fig. 1 is a block diagram of a prior art smart phone
• Fig. 2 is a block diagram of a loosely coupled multi processor system in accordance with the invention
• Fig. 3 is a block diagram of an alternative embodiment
• Fig. 4 is a block diagram of an implementation of a smart phone in accordance with the invention.
• Fig. 5 is illustrative of a zero-delay multiplexer which can be used in the embodiment of Fig. 4,
• Fig. 6 is illustrative of an embodiment of a zero-delay multiplexer which can be used in the embodiment of Fig. 4,
• Fig. 7 is a flow chart being illustrative of a method for generating boot-images for the sub-systems and
• Fig. 8 is illustrative of an embodiment of the method of the invention.
• Fig. 2 shows an electronic system having sub-systems Si, S2 , S3 ...Sn.
• Each of the sub-systems has a RAM 18 and a microprocessor 19 which is coupled to its respective RAM 18.
• Each of the sub-systems SI to Sn is coupled to a controller 20 via bus 21.
• the controller 20 is coupled to nonvolatile memory
• the code SI is the boot-image for the sub-system SI
• the code S2 is the boot-code for the sub-system S2 and so on.
• the codes SI to Sn are stored in the memory portion 23 in sequential order. This allows to utilize an inexpensive memory device for the memory 22 such as an NAND-FLASH memory. Storing the codes SI to Sn in sequential order avoids random memory access operations . As a consequence the access time provided by an inexpensive NAND-FLASH memory device is largely sufficient for sequentially reading the respective codes .
• the controller 20 provides the respective code portions to the ⁇ sub-systems SI to Sn via bus 21. After the boot-images have been loaded into all sub-system SI to Sn the normal system operation can immediately start.
• Fig. 3 is an alternative embodiment of the electronic system of Fig. 2.
• the same reference numbers are used for like elements .
• the electronic system of Fig. 3 has a memory 22 for storing portions of boot-image code for different sub-systems in the same memory line.
• the first line of the memory 22 contains the first code portions Sll, S21, S31, ..., Snl of all the sub-systems Si to Sn.
• the following lines of memory contain the further code portions .
• Flash memory system 22 can be realized to provide a data width representing the summed data width of all respective sub-systems .
• the DRAM loading time for all three sub-systems would be 0,8 seconds, thus resulting in an overall system boot-time of ⁇ 1 seconds in this example.
• the DRAM loading time for all 3 sub-systems would be 0,267 sec, thus resulting in an overall system boot-time of ⁇ 0,3 ns .
• Fig. 4 is another embodiment of an electronic system of the invention.
• the electronic system of Fig. 4 is a smart phone having a cell phone sub-system 24, a PDA sub-system 25 and a GPS sub-system 26.
• the cell phone sub-system 24 has a cell phone engine 27 and a system RAM 28.
• the cell phone engine 27 and the system RAM 28 are coupled by a multiplexer 29.
• the multiplexer 29 and the system RAM 28 each have a control input for receiving boot control information via line 30 from controller 31.
• the multiplexer 29 is coupled to the controller 31 via line 32 for receiving of boot-image data for the cell phone sub-system 24.
• the connection path between the multiplexer 29 to the controller 31 can include an optional code compression coprocessor 33.
• cell phone engine 27 is coupled to the controller 31 via line 34 for the purposes of control and transmission of boot-image data to the cell phone engine 27.
• cell phone engine 27 is coupled to high frequency radio component 35 which is coupled to antenna 36 in order to realize an air interface.
• cell phone engine 27 is coupled to audio I/O system 37 which is coupled to a speaker and a microphone.
• the cell phone sub-system 24 is powered by DC-power sub-system 38.
• the system RAM 28 and the multiplexer 29 receive a power signal from output P5 of the DC-power subsystem 38 whereas the remaining components of the cell phone sub-system 24, including the cell phone engine 27, receive power vie the line P2 of the DC-power sub-system 38.
• the PDA sub-system 25 has a main processor 39 for the performance of typical PDA functions. Analogously to the cell phone sub-system 24 the main processor 39 is coupled to system RAM 40 via multiplexer 41. Again the system RAM 40 and the multiplexer 41 have control inputs for receiving boot control information from the controller 31 via line 42 and the multiplexer 41 is connected to controller 31 via line 43 to receive boot-image data via optional code compression coprocessor 33. Again main processor 39 is also connected to controller 31 by line 44.
• main processor 39 is coupled to output unit 44 including an LCD display and to a mass storage device, such as smart media, via mass storage controller 45.
• the system RAM 40 and the multiplexer 41 receive power via line P5 of the DC-power sub-system 38 and the remaining components of the PDA sub-system 25, including main processor 39, receive power via line P4 of the DC-power sub-system 38.
• the GPS sub-system 26 has a GPS system processor 46 which is coupled to its system RAM 47 via multiplexer 48.
• the system RAM 47 and the multiplexer 48 have control inputs which are coupled to the boot-control output of the controller 31 via line 49.
• GPS system processor 46 is coupled to GPS receiver 50 having an antenna 51.
• the system RAM 47 and the multiplexer 48 receive power from the output P5 of the DC-power sub-system 38 whereas the remaining components of the GPS sub-system 26, including GPS system processor 46, receive power from the output P3 of the DC-power sub-system 38.
• the above described cell phone sub-system 24, PDA sub-system 25 and GPS sub-system 26 are inter-coupled by busses 52 and 53 for loosely coupling the sub-systems .
• the DC-power sub-system 38 is connected to the controller 31 via line 54 for the purposes of power control, in particular with respect to bringing the electronic system into a sleep- mode. Further the controller 31 is coupled to nonvolatile memory 54. Nonvolatile memory 54 corresponds to memory 22 of Fig. 2 and serves to store the boot-image data of the cell phone subsystem 24, the PDA sub-system 25 and the GPS sub-system 26 in consecutive order.
• the optional code compression co-processor 33, the controller 31 and the memory 54 are comprised in a boot control system 55.
• the boot control system 55 receives power from the DC-power sub-system 38 from its output Pi.
• the controller 31 directs the DC- power sub-system 38 to apply power to the components of the cell phone sub-system 24, the PDA sub-system 25 and the GPS sub-system 26.
• the controller 31 performs a read request to the memory 54 in order to read out the boot-image data contained in memory 54 sequentially.
• a single read request is sufficient in order to start the screening of the complete boot-image data out of the memory 54 to the controller 31.
• the controller 31 first receives the boot-image data for the cell phone sub-system 24 and transmits the boot-image data to the cell phone sub-system 24.
• the boot- image data to be stored in system RAM 28 is provided to the multiplexer 29 which receives a control input via line 30 in order to pass the boot-image data to the system RAM 28 for storage.
• the cell phone engine 27 can receive register values via line 24 from the controller 31.
• the register values can be embedded in the boot-image data.
• control data in the boot-image data can be utilized for detection by the controller 31 such that the controller 31 can direct the required portions of the boot-image data to the appropriate components of the cell phone sub-system 24.
• the controller 31 can switch off the clocks of the microprocessors i.e. cell phone engine 27, main processor 39 and GPS system processor 46, while directing the DC- power sub-system 38 to continue to supply power via lines P2 , P3 , P4, respectively. This way the operation of the respective processors is stopped while preserving the contents of the processors register values.
• the refreshing of the system RAMs 28, 40 and 47 is done by the controller 31 in order to preserve the data in those memories. This way a substantial amount of power can be saved. In order to bring the system back to life only the clocks for the processors have to be switched on again and normal system operation can be resumed immediately.
• This option is different from the first one in that both the clocks and the power of the microprocessors are switched off. This has the advantage that even more power can be saved. However for bringing the system back to life the registers of the microprocessors have to be reloaded from the memory 54 which takes some amount of time. 3. This option is different from the first two options in that the power and clocks for the sub-system 24, 25 and 26 are completely switched off. This has the advantage that even more power can be saved; on the other hand the complete boot-images have to be reloaded.
• a significant overall system cost saving can be accomplished by means of the system of Fig. 4 by (i) a reduced size and amount of overall system FLASH memory (ii) application of highly cost effective large scale integrated FLASH memories as the entire boot / program / code of all sub-systems and applications can be concentrated in one common memory and (iii) utilizing highly cost effective large scale SDRAM memories in the core- processing-sub-systems of the overall system.
• code compression and decompression by means of code compression co-processor 33.
• code compression an error correcting code can be used such that a very in-expensive memory device 54 having a high error rate can be utilized.
• programs and applications exercising directly out of the high speed SDRAMs will increase the individual sub-system operation speed - as well as the overall system performance.
• Fig. 5 illustrates a preferable solution.
• the basic element of the switch is a fast, low on resistance, low capacitance, high current capacity MOS-FET switch.
• the combination of low on resistance and low capacitance is provided by a CMOS process allowing a short CMOS channel length.
• the switch shown in Fig. 5 consists of a N-channel MOS transistor driven by a CMOS gate.
• the gate of the N-channel transistor is at Vcc (+5V) and the device is on, with a typical on resistance of ⁇ 5W.
• the switch is off.
• the N-channel is preferably structured causing no direct leakage and to represent very low capacitance across the transistor in the off state.
• the off state leakage of this type of circuits is typically ⁇ 1 nA at room temperature .
• Fig. 6 is illustrative of a block diagram of an integrated implementation of the multiplexers 29, 41 and 48 of Fig. 4 using devices of the type as shown in Fig. 4.
• Fig. 7 is illustrative of a method to obtain the boot-images of the sub-systems of the system of Fig. 4.
• step 60 the sub-systems SI to Sn are implemented in a test system. The test system is booted in the usual way.
• step 61 the RAMs and the microprocessor registers of the sub-systems SI to Sn are scanned in order to obtain corresponding boot-images II to In.
• step 62 the boot-images II to In are concatenated by writing the boot-images sequentially into a nonvolatile RAM corresponding to memory 54 of the system in Fig. 4.
• Fig. 8 is illustrative of the options provided by the system of Fig. 4 for bringing the system into a sleep-mode.
• step 70 the boot-images II to In for the respective sub-systems SI to Sn are loaded such that the normal system operation can start.
• step 72 the DRAMs are continued to be refreshed by the boot controller (cf . controller 31 of Fig. 4) .
• step 73 the clocks of the multi processors are switched on again such that normal system operation can be resumed in step 74.
• both the clocks and the power of the microprocessors can be switched off in step 75 while the DRAMs are continued to be refreshed by the boot controller in step 76.
• step 7 * 7 the microprocessor registers are reloaded and the clocks are switched on in order to resume normal system operation in step 74.
• both the clocks and the power for all components of the sub-systems can be switched off in step 78.
• the complete boot-images II to In need to be reloaded in step 79 to resume normal system operation in step 74.
• DC-power sub-system 38 main processor 39 system RAM 40 multiplexer 41 line 42 line 43 output device 44 mass storage controller 45
• GPS receiver 50 antenna 51 bus 52 bus 53 memory 54 boot control system 55

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• 2002
  • 2002-04-24 WO PCT/EP2002/004480 patent/WO2002095581A2/en not_active Ceased
  • 2002-04-24 EP EP02730195A patent/EP1407352A2/de not_active Withdrawn
  • 2002-04-24 AU AU2002302563A patent/AU2002302563A1/en not_active Abandoned

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