EP1396875B1 - 3-D spiral stacked inductor on semiconductor material - Google Patents
3-D spiral stacked inductor on semiconductor material Download PDFInfo
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- EP1396875B1 EP1396875B1 EP03019916A EP03019916A EP1396875B1 EP 1396875 B1 EP1396875 B1 EP 1396875B1 EP 03019916 A EP03019916 A EP 03019916A EP 03019916 A EP03019916 A EP 03019916A EP 1396875 B1 EP1396875 B1 EP 1396875B1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/4902—Electromagnet, transformer or inductor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/4902—Electromagnet, transformer or inductor
- Y10T29/49021—Magnetic recording reproducing transducer [e.g., tape head, core, etc.]
- Y10T29/49032—Fabricating head structure or component thereof
- Y10T29/4906—Providing winding
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/4902—Electromagnet, transformer or inductor
- Y10T29/49073—Electromagnet, transformer or inductor by assembling coil and core
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Definitions
- the present invention relates generally to integrated circuits and more particularly to on-chip silicon-based inductors.
- CMOS complementary metal oxide semiconductor
- AlCu aluminum-copper
- an active inductor In an active inductor high Q factor and inductance can be achieved in a really small silicon area. However, such approach suffers from high power consumption and high noise levels that are not acceptable for low power and high frequency applications. In addition, performance of active inductors are very sensitive and dependent upon the inductor's biasing circuitry, making it time consuming and tedious to design.
- the simplest and most commonly used on-chip inductors are planar silicon-based spiral inductors, which require careful layout optimization techniques to improve performance.
- the inductor is planar and fabricated on a conductive silicon substrate.
- the top metal is usually stacked with a few layers of lower metal through vias to minimize the overall metal series resistance. Nevertheless, when more layers are used to realize a very thick conductor, the whole spiral is brought closer to the substrate. This increases the spiral-to-substrate parasitic capacitance and hence results in a degradation of Q factor as well as the inductor's self-resonant frequency. It has been observed that the Q factor of a 4-layer stacked inductor decreases at a much faster rate compared to 1- to 3-layer stacked inductors. Because of this, it becomes extremely difficult to design high performance inductors with large inductance values since such a phenomenon is more pronounced when the inductors occupy large areas.
- the basic working principal is to minimize undesirable magnetic flux created by the induced substrate eddy current, especially at the inductor's core. This can be easily accomplished by reducing current density of the inductor's inner turns. Meanwhile, when current density of the inner turns is reduced, induced substrate current at the center of the inductor will also have a lower current density. As a result, at the inductor's core, parasitic magnetic flux generated in the substrate is much weaker and this helps increase the inductance and the Q factor of spiral inductors.
- US 5,831,331 discloses an inductive structure for an integrated circuit.
- the inductor has a first turn that shields the other turn of the inductor from a proximate ground plane.
- Multiple turns are disposed one above another in respective metallization layers of the integrated circuit.
- the turns are partial loops and are electrically coupled end-to-end with vias, thus giving rise to a modified helix structure.
- US 5,446,311 discloses a further inductor structure which is formed with multiple metallization levels.
- this document discloses two metal levels of identical spiral metal patterns which are shunt by vias extending along each spiral pattern.
- the present invention provides a 3-D spiral stacked inductor having a substrate with a plurality of turns in a plurality of levels wherein the number of levels increases from an inner turn to the outer turns of the inductor.
- First and second connecting portions are respectively connected to an inner turn and an outermost turn, and a dielectric material contains the first and second connecting portions and the plurality of turns over the substrate. This will reduce current in the inner turn and lower current density in the outer turns to improve inductance and Q factor beyond 2.5 GHz.
- the present invention further provides a 3-D spiral stacked inductor where neither additional processing steps nor additional masks are required.
- the present invention further provides a 3-D spiral stacked inductor having a greatly reduced average parasitic capacitance as compared to a conventional stacked inductor for the same number of metal layers.
- the present invention further provides a 3-D spiral stacked inductor wherein the difference in current density for every turn is much larger compared to the varying width inductor. This difference is achieved without consuming extra silicon.
- This optimized 3-D stacked design can be implemented for inductors of small as well as large inductance values.
- the present invention further provides a circular type as well as copper inductors along with varying widths.
- FIG. 1 PRIOR ART
- a substrate 12 of a material such as silicon, has a plurality of dielectric layers formed thereon of a material such as silicon dioxide.
- a field dielectric layer 14 such as a field oxide
- a connecting interlayer dielectric (ILD) layer 16 such as a silicon oxide
- a first level ILD layer 18, and a second level ILD layer 20 are formed over the substrate 12.
- a spiral stacked inductor 22 Embedded within the dielectric layers.
- over as used in herein is defined vertically above a horizontal plane parallel to the conventional surface of a wafer on which the on-chip inductor is formed regardless of the orientation of the wafer. Terms, such as “on”, “below”, “higher”, “lower”, “above”, and “under”, are defined with respect to the horizontal plane.
- processed or “forming” as used herein to refer to the formation of vias and turns includes conventional semiconductor deposition of photoresist, hard and soft mask photolithography, etch, and strip, as appropriate.
- the spiral stacked inductor 22 is a two-turn stacked inductor.
- FIG. 1 PRIOR ART
- first and second turns 24 and 26 are shown.
- a first connecting portion 30 having connecting vias 32 connects to the spiral stacked inductor 22 at one end and a second connecting portion 34 connects at the other end.
- the first turn 24 has an inner diameter 36, a width 38 which is common to each of the turns, and a spacing 40 between each of the turns.
- the first connecting portion 30 passes under the two turns and thus is also referred to as an underpass 30.
- FIG. 2 PRIOR ART
- the substrate 12 has the field dielectric layer 14 upon which a conductive material is deposited and patterned to form the underpass 30.
- the connecting ILD layer 16 is then deposited over the underpass 30.
- One or more first via openings are formed in the connecting ILD layer 16 connected to the underpass 30.
- a conductive material layer is deposited on the connecting ILD layer 16 and processed to form a first level of the spiral stacked inductor 22. When processed, first and second turns 24' and 26' of a first level 50' will be formed. The first via openings are also filled with conductive material to form the connecting vias 32.
- the first level ILD layer 18 is then deposited over the first level 50'.
- a conductive material is deposited on the first level ILD layer 18 and processed to form the first and second turns 24 and 26 of a second level 50'.
- the first and second turns 24 and 26 are respectively connected to the first and second turn vias 24v and 26v along their lengths by the conductive material filling the respective vias openings to form first and second turn vias 24v and 26v.
- the second level ILD layer 20 is then deposited over the second level 50'.
- the passage of current (direction indicated by double circles as being an arrow head and the x in a circle being the tail) through the spiral stacked inductor 22 causes the creation of magnetic fields 52 which induce magnetic fields 54 in the substrate 12.
- an eddy current 56 is induced in the low resistivity substrate 12, which flows in a direction that is opposite to the flow in the spiral stacked inductor 22. This causes a magnetic loss that results in the degradation of the overall useful inductance of the spiral stacked inductor 22.
- a substrate 112 of a material such as silicon has a plurality of dielectric layers formed thereon of a material such as silicon dioxide.
- a field dielectric layer 114 such as a field oxide
- a connecting interlayer dielectric (ILD) layer 116 such as a silicon oxide
- a first level ILD layer 118, a second level ILD layer 120, and a third level ILD layer 121 are formed over the substrate 112.
- a 3-D spiral stacked inductor 122 Embedded within the dielectric layers.
- the 3-D spiral stacked inductor 122 is shown as being square spiral but it may also be circular spiral. Similarly, the 3-D spiral stacked inductor 122 can be a spiral, which is either clockwise or counter clockwise as viewed from above.
- the 3-D spiral stacked inductor 122 is a 3-D three-turn inductor.
- first, second, and third turns 124, 126, and 128 are shown.
- the turns can be flat as shown or circular, and can be made from any conductive material including copper.
- a first connecting portion 130 having connecting vias 132 connects to the 3-D spiral stacked inductor 122 at one end and a second connecting portion 134 connects at the other end to the third turn 128.
- the first turn 126 has an inner diameter 136, a width 138 which is common to each of the turns, and a spacing 140 between each of the turns.
- the first connecting portion 130 passes under the three turns and thus is also referred to as an underpass 130.
- FIG. 4 therein is shown a cross-sectional view of the 3-D spiral stacked inductor 100 of the present invention along line 4--4 of FIG. 3 .
- the substrate 112 has the field dielectric 114 upon which a conductive material is deposited and patterned to form the underpass 130.
- the connecting ILD layer 116 is then deposited over the underpass 130.
- One or more first via openings are formed in the connecting ILD layer 116 connected to the under pass 130.
- a conductive material layer is deposited on the connecting ILD layer 116 and processed to form a first level of the spiral stacked inductor 122.
- a third turn 128' of a first level 150' will be formed and a first connecting contact 130' is formed at the first level 150'.
- the first via openings are filled with conductive material to form the connecting vias 132.
- the first level ILD layer 118 is then deposited over the first level 150'.
- One or more second via openings are formed in the first level ILD layer 118 connected to the third turn 128' and the first connecting contact 130'. The second via openings extend substantially along the entire length of the third turn 128'.
- a conductive material is deposited on the first level ILD layer 118 and processed to form second and third turns 126" and 128" and a second connecting contact 130" of a second level 150".
- the third turn 128" is connected to the third turn 128' along its length by the conductive material filling the second via openings to form first level third turn vias 128v1.
- the second connecting contact 130" is connected to the first connecting contact 130' by conductive material filling the second via openings to form first connecting vias 132v1.
- the second level ILD layer 120 is then deposited over the second level 150".
- One or more third via openings are formed in the second ILD layer 120 connected to the second and third turns 126" and 128", and the second connecting contact 130".
- the third via openings extend substantially along the entire length of the second and third turns 126" and 128".
- a conductive material is deposited on the second level ILD layer 120 and processed to form first, second, and third turns 124, 126, and 128 of a third level 150"'.
- the first, second, and third turns 124, 126, and 128 are respectively connected to the second connecting contact 130" by conductive material filling the third via openings to form second connecting vias 132v2, and the second level second and third turns 126" and 128" by conductive material filling the third via openings to form second level second and third turn vias 126v2 and 128v2.
- the third level ILD layer 121 is then deposited over the third level 150"'.
- spiral stacked inductor 22 As will be understood by those skilled in the art, as the spiral stacked inductor 22 has more turns, it will still have the same number of turns in each level and the turns will all be connected by pluralities of vias. On the other hand, as the 3-D spiral stacked inductor 122 has more turns, it has more levels with a fewer number of turns per level and, although the turns will all be connected by pluralities of vias, a lower number of turns at the lowest levels.
- a 3-D two turn inductor has two levels having one turn in a first level and two turns in a second level; a 3-D three turn inductor is shown; a 3-D four turn inductor has four levels with one turn in a first level, two turns in a second level, three turns in a third level, and four turns in a fourth level; etc.
- 3-D spiral stacked inductors could be made in the same fashion as shown with various configurations (such as circular), diameters, widths, and spacings.
- different metals can be used for the inductors including aluminum and copper.
Abstract
Description
- The present invention relates generally to integrated circuits and more particularly to on-chip silicon-based inductors.
- Increasing demands for personal mobile communications equipment have motivated recent research activities to focus on the development of inexpensive, small size, low power consumption, and low noise level systems. To satisfy these requirements, one of the most important and indispensable circuit components is the on-chip silicon-based inductor.
- As a result, miniaturization of the inductor on silicon has become a current key research area and extensive work has been done in this area. However, despite efforts by many researchers having skill in the art, achieving high performance on-chip inductors, i.e., high qualify factor (Q), still remains a major problem especially when radio frequency integrated circuits (RFICs) are built on silicon.
- Conventional inductors built on silicon are generally planar in nature. The current complementary metal oxide semiconductor (CMOS) process uses a very conductive substrate. Spiral inductors fabricated on such a lossy substrate suffer from high capacitive and magnetic losses.
- In addition, high dynamic resistance of metal lines at GHz frequency ranges further degrades the inductor performance in CMOS technology as compared to those fabricated in monolithic microwave integrated circuits (MMICs).
- Many fabricating techniques, processes, and materials have been proposed to improve the performance of on-chip inductors. Tedious processing techniques such as etching away the silicon substrate under the inductor have been introduced to remove the substrate parasitic effects completely. Despite achieving good results, industries are reluctant to adopt such a technique because of reliability issues such as packaging yield, as well as long-term mechanical stability.
- Another approach to minimize the substrate loss for silicon-based inductors has been to increase the substrate resistivity. This technique has yielded significant results, however, the substrate becomes unsuitable for building active MOS devices.
- The most critical factor hindering the performance of silicon-based inductors is the high resistive aluminum-copper (AlCu) interconnects used in silicon processes.
- In comparison, thicker and less resistive gold (Au) metalization together with lossless substrate in gallium arsenide (GaAs) technology permits high performance inductors to be fabricated easily. To overcome high metalization resistance, a popular technique is to have the layers of metal stacked together, thereby achieving a high Q inductor.
- Another possible alternative is to use an active inductor. In an active inductor high Q factor and inductance can be achieved in a really small silicon area. However, such approach suffers from high power consumption and high noise levels that are not acceptable for low power and high frequency applications. In addition, performance of active inductors are very sensitive and dependent upon the inductor's biasing circuitry, making it time consuming and tedious to design.
- As a result of the above, the simplest and most commonly used on-chip inductors are planar silicon-based spiral inductors, which require careful layout optimization techniques to improve performance.
- In the conventional spiral inductor design, the inductor is planar and fabricated on a conductive silicon substrate. To improve the Q factor of the spiral inductors, the top metal is usually stacked with a few layers of lower metal through vias to minimize the overall metal series resistance. Nevertheless, when more layers are used to realize a very thick conductor, the whole spiral is brought closer to the substrate. This increases the spiral-to-substrate parasitic capacitance and hence results in a degradation of Q factor as well as the inductor's self-resonant frequency. It has been observed that the Q factor of a 4-layer stacked inductor decreases at a much faster rate compared to 1- to 3-layer stacked inductors. Because of this, it becomes extremely difficult to design high performance inductors with large inductance values since such a phenomenon is more pronounced when the inductors occupy large areas.
- Magnetic losses occur when inductors are built on conductive substrates. According to Faraday's law, an image current or eddy current is induced in the substrate underneath the spiral inductor. Since a silicon substrate has low resistivity, this image current can flow easily. In compliance with Lenz's law, the direction of flow for this induced current is opposite to that of the inductor current. This characteristic results in a degradation of the inductor's overall useful inductance.
- To reduce these magnetic losses due to the formation of the eddy currents, varying width inductors have been proposed. The basic working principal is to minimize undesirable magnetic flux created by the induced substrate eddy current, especially at the inductor's core. This can be easily accomplished by reducing current density of the inductor's inner turns. Meanwhile, when current density of the inner turns is reduced, induced substrate current at the center of the inductor will also have a lower current density. As a result, at the inductor's core, parasitic magnetic flux generated in the substrate is much weaker and this helps increase the inductance and the Q factor of spiral inductors.
- However, it has been observed that the Q factor degrades drastically at higher frequencies when compared with fixed-width spiral inductors. This suggests that for a large inductor to achieve a difference in current density between the inner and outer turns, the overall inductor area must be enormous. Its Q factor is expected to fall even before 2.45 GHz and would, of course, render this technique completely useless.
- Solutions to these problems have been long sought, but have long eluded those skilled in the art.
-
US 5,831,331 discloses an inductive structure for an integrated circuit. The inductor has a first turn that shields the other turn of the inductor from a proximate ground plane. Multiple turns are disposed one above another in respective metallization layers of the integrated circuit. The turns are partial loops and are electrically coupled end-to-end with vias, thus giving rise to a modified helix structure. -
US 5,446,311 discloses a further inductor structure which is formed with multiple metallization levels. In particular, this document discloses two metal levels of identical spiral metal patterns which are shunt by vias extending along each spiral pattern. - The present invention provides a 3-D spiral stacked inductor having a substrate with a plurality of turns in a plurality of levels wherein the number of levels increases from an inner turn to the outer turns of the inductor. First and second connecting portions are respectively connected to an inner turn and an outermost turn, and a dielectric material contains the first and second connecting portions and the plurality of turns over the substrate. This will reduce current in the inner turn and lower current density in the outer turns to improve inductance and Q factor beyond 2.5 GHz.
- The present invention further provides a 3-D spiral stacked inductor where neither additional processing steps nor additional masks are required.
- The present invention further provides a 3-D spiral stacked inductor having a greatly reduced average parasitic capacitance as compared to a conventional stacked inductor for the same number of metal layers.
- The present invention further provides a 3-D spiral stacked inductor wherein the difference in current density for every turn is much larger compared to the varying width inductor. This difference is achieved without consuming extra silicon. This optimized 3-D stacked design can be implemented for inductors of small as well as large inductance values.
- The present invention further provides a circular type as well as copper inductors along with varying widths.
- The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
-
FIG. 1 (PRIOR ART) is a cross-sectional view of a prior art on-chip inductor along line 1--1 ofFIG. 2 (PRIOR ART); -
FIG. 2 (PRIOR ART) is a cross-sectional view of the prior art on-chip inductor alongline 2--2 ofFIG. 1 (PRIOR ART); -
FIG. 3 is shown a cross-sectional view of a 3-D spiral stacked inductor of the present invention along line 3--3 ofFIG. 4 ; and -
FIG. 4 is shown a cross-sectional view of the 3-D spiral stacked inductor of the present invention alongline 4--4 ofFIG. 3 . - Referring now to
FIG. 1 (PRIOR ART), therein is shown a cross-sectional view of a prior art on-chip inductor 10 along line 1--1 ofFIG. 2 (PRIOR ART). Asubstrate 12, of a material such as silicon, has a plurality of dielectric layers formed thereon of a material such as silicon dioxide. Sequentially, a field dielectric layer 14 (such as a field oxide), a connecting interlayer dielectric (ILD) layer 16 (such as a silicon oxide), a firstlevel ILD layer 18, and a secondlevel ILD layer 20 are formed over thesubstrate 12. Embedded within the dielectric layers is a spiral stackedinductor 22. - The term "over" as used in herein is defined vertically above a horizontal plane parallel to the conventional surface of a wafer on which the on-chip inductor is formed regardless of the orientation of the wafer. Terms, such as "on", "below", "higher", "lower", "above", and "under", are defined with respect to the horizontal plane.
- The term "processed" or "forming" as used herein to refer to the formation of vias and turns includes conventional semiconductor deposition of photoresist, hard and soft mask photolithography, etch, and strip, as appropriate.
- In the described embodiment, the spiral stacked
inductor 22 is a two-turn stacked inductor. InFIG. 1 (PRIOR ART), are shown first and second turns 24 and 26. - A first connecting
portion 30 having connectingvias 32 connects to the spiral stackedinductor 22 at one end and a second connectingportion 34 connects at the other end. - The
first turn 24 has aninner diameter 36, a width 38 which is common to each of the turns, and aspacing 40 between each of the turns. The first connectingportion 30 passes under the two turns and thus is also referred to as anunderpass 30. - Referring now to
FIG. 2 (PRIOR ART), therein is shown a cross-sectional view of the prior art on-chip inductor 10 alongline 2--2 ofFIG. 1 (PRIOR ART). Thesubstrate 12 has thefield dielectric layer 14 upon which a conductive material is deposited and patterned to form theunderpass 30. - The connecting
ILD layer 16 is then deposited over theunderpass 30. One or more first via openings are formed in the connectingILD layer 16 connected to theunderpass 30. - A conductive material layer is deposited on the connecting
ILD layer 16 and processed to form a first level of the spiral stackedinductor 22. When processed, first and second turns 24' and 26' of a first level 50' will be formed. The first via openings are also filled with conductive material to form the connectingvias 32. - The first
level ILD layer 18 is then deposited over the first level 50'. One or more second via openings formed in the firstlevel ILD layer 18 connected to the first and second turns 24' and 26' along their lengths. - A conductive material is deposited on the first
level ILD layer 18 and processed to form the first and second turns 24 and 26 of a second level 50'. The first and second turns 24 and 26 are respectively connected to the first andsecond turn vias 24v and 26v along their lengths by the conductive material filling the respective vias openings to form first andsecond turn vias 24v and 26v. - The second
level ILD layer 20 is then deposited over the second level 50'. - As will be understood by those skilled in the art, as a spiral stacked inductor has more turns, it will still have the same number of turns in each level and the turns will all be connected along their length by pluralities of vias.
- During operation, the passage of current (direction indicated by double circles as being an arrow head and the x in a circle being the tail) through the spiral stacked
inductor 22 causes the creation ofmagnetic fields 52 which inducemagnetic fields 54 in thesubstrate 12. According to Faraday's law, aneddy current 56 is induced in thelow resistivity substrate 12, which flows in a direction that is opposite to the flow in the spiral stackedinductor 22. This causes a magnetic loss that results in the degradation of the overall useful inductance of the spiral stackedinductor 22. - Referring now to
FIG. 3 , therein is shown a cross-sectional view of a 3-D spiral stackedinductor chip 100 of the present invention along line 3--3 ofFIG. 4 . Asubstrate 112, of a material such as silicon, has a plurality of dielectric layers formed thereon of a material such as silicon dioxide. Sequentially, a field dielectric layer 114 (such as a field oxide), a connecting interlayer dielectric (ILD) layer 116 (such as a silicon oxide), a firstlevel ILD layer 118, a secondlevel ILD layer 120, and a thirdlevel ILD layer 121 are formed over thesubstrate 112. Embedded within the dielectric layers is a 3-D spiral stackedinductor 122. - The 3-D spiral stacked
inductor 122 is shown as being square spiral but it may also be circular spiral. Similarly, the 3-D spiral stackedinductor 122 can be a spiral, which is either clockwise or counter clockwise as viewed from above. - In the described embodiment, the 3-D spiral stacked
inductor 122 is a 3-D three-turn inductor. InFIG. 3 , is shown first, second, andthird turns - A first connecting
portion 130 having connectingvias 132 connects to the 3-D spiral stackedinductor 122 at one end and a second connectingportion 134 connects at the other end to thethird turn 128. - The
first turn 126 has aninner diameter 136, awidth 138 which is common to each of the turns, and aspacing 140 between each of the turns. The first connectingportion 130 passes under the three turns and thus is also referred to as anunderpass 130. - Referring now to
FIG. 4 , therein is shown a cross-sectional view of the 3-D spiral stackedinductor 100 of the present invention alongline 4--4 ofFIG. 3 . Thesubstrate 112 has thefield dielectric 114 upon which a conductive material is deposited and patterned to form theunderpass 130. - The connecting
ILD layer 116 is then deposited over theunderpass 130. One or more first via openings are formed in the connectingILD layer 116 connected to the underpass 130. - A conductive material layer is deposited on the connecting
ILD layer 116 and processed to form a first level of the spiral stackedinductor 122. When processed, a third turn 128' of a first level 150' will be formed and a first connecting contact 130' is formed at the first level 150'. The first via openings are filled with conductive material to form the connectingvias 132. - The first
level ILD layer 118 is then deposited over the first level 150'. One or more second via openings are formed in the firstlevel ILD layer 118 connected to the third turn 128' and the first connecting contact 130'. The second via openings extend substantially along the entire length of the third turn 128'. - A conductive material is deposited on the first
level ILD layer 118 and processed to form second andthird turns 126" and 128" and a second connectingcontact 130" of asecond level 150". Thethird turn 128" is connected to the third turn 128' along its length by the conductive material filling the second via openings to form first level third turn vias 128v1. The second connectingcontact 130" is connected to the first connecting contact 130' by conductive material filling the second via openings to form first connecting vias 132v1. - The second
level ILD layer 120 is then deposited over thesecond level 150". One or more third via openings are formed in thesecond ILD layer 120 connected to the second andthird turns 126" and 128", and the second connectingcontact 130". The third via openings extend substantially along the entire length of the second andthird turns 126" and 128". - A conductive material is deposited on the second
level ILD layer 120 and processed to form first, second, andthird turns third level 150"'. The first, second, andthird turns contact 130" by conductive material filling the third via openings to form second connecting vias 132v2, and the second level second andthird turns 126" and 128" by conductive material filling the third via openings to form second level second and third turn vias 126v2 and 128v2. - The third
level ILD layer 121 is then deposited over thethird level 150"'. - As will be understood by those skilled in the art, as the spiral stacked
inductor 22 has more turns, it will still have the same number of turns in each level and the turns will all be connected by pluralities of vias. On the other hand, as the 3-D spiral stackedinductor 122 has more turns, it has more levels with a fewer number of turns per level and, although the turns will all be connected by pluralities of vias, a lower number of turns at the lowest levels. For example, a 3-D two turn inductor has two levels having one turn in a first level and two turns in a second level; a 3-D three turn inductor is shown; a 3-D four turn inductor has four levels with one turn in a first level, two turns in a second level, three turns in a third level, and four turns in a fourth level; etc. - The above means that the induced magnetic fields of the prior art are negligible.
- As will be understood by those skilled in the art, since the turns closest to the substrate have the greatest effect on magnetic loss, higher levels may have more or less turns per level without substantially increasing the magnetic loss while the lowest level is optimized by having the underpass and/or a single turn.
- Also as will be understood by those skilled in the art, 3-D spiral stacked inductors could be made in the same fashion as shown with various configurations (such as circular), diameters, widths, and spacings. Similarly, different metals can be used for the inductors including aluminum and copper.
- While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the included claims. All matters hither-to-fore set forth or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.
Claims (10)
- A method of manufacturing a 3-D spiral stacked inductor comprising:providing a substrate (112);forming a first conductive material layer over the substrate (112);processing the first conductive material layer to form a first level first turn (150'-128);forming a first dielectric layer (118) over the substrate (112) and the first level first turn (150'-128);forming a first turn first via opening in the first dielectric layer (118) connected to the first level first turn (150'-128) and extending substantially along the length thereof;forming a second conductive material layer over the first dielectric layer (118) and in the first turn first via opening;processing the second conductive material layer to form a second level second turn (150"-126) and a second level first turn (150"-128) said second level first and second turns forming turns of a spiral in said second layer and said second level first turn (150'' - 128) being.-connected to the first level first turn (150'-128) by means of the conductive material in said first via opening; andforming a second dielectric layer (120) over the first dielectric layer (118), the second level second turn (150"-126), and the second level first turn (150"-128).
- The method as claimed in claim 1 including:forming a first turn second via opening and a second turn second via opening in the second dielectric layer (120) respectively connected to the second level first turn (150"-128) and second level second turn (150"-126);forming a third conductive material layer over the second dielectric layer (120) and in the first turn second via opening and a second turn second via opening;processing the third conductive material layer to form a third level third turn (150'''-124), a third level second turn (150"'-126) connected to the second level second turn (150"-126), a third level first turn (150"'-128) connected to the second level first turn (150"-128); andforming a third dielectric layer (121) over the second dielectric layer (120), the third level third turn (150"'-124), the third level second turn (150"'-126), and the third level first turn (150"'-128).
- The method as claimed in claim 2 including:forming a first turn third via opening, a second turn third via opening, and a third turn third via opening in the third dielectric layer (121) respectively connected to the third level first turn (150"'-128), the third level second turn (150"'-126), and the third level third turn (150"'-124);forming a fourth conductive material layer over the third dielectric layer (121) and in the first turn (24) third via opening, a second turn (26) third via opening, and a third turn third via opening;processing the fourth conductive material layer to form a fourth level fourth turn; a fourth level third turn connected to the third level third turn (150"'-124), a fourth level second turn connected to the third level second turn (150"'-126), a fourth level first turn connected to the third level first turn (150"'-128); andforming a fourth dielectric layer (14) over the third dielectric layer (121), the fourth level fourth turn, the fourth level third turn, the fourth level second turn, and the fourth level first turn.
- The method as claimed in claim 3 including:forming a first connecting portion (130) under the first level first turn (150'-128) andconnected to the second level second turn (150"-126) and/or the third level third turn (150"'-124) and/or the fourth level fourth turn.
- The method as claimed in claim 3 including:forming a second connecting portion (134) while processing the second conductive material layer and/or the third conductive material layer and/or the fourth conductive material layer.
- A 3-D spiral stacked inductor comprising:a substrate (112);a plurality of spiral turns (124, 126, 128) in a plurality of levels (150', 150", 150"') wherein:the number of levels per spiral turn increases from an inner turn of the plurality of turns (124, 126, 128),the number of spiral turns per level decreases for levels more proximate to the substrate (112) to one turn in the level proximate the substrate (112), andat least one of the plurality of turns (124, 126, 128) is interconnected along the length thereof to another turn in the plurality of levels (150', 150", 150"');a first connecting portion (130) connected to the inner turn of the plurality of turns (124, 126, 128) in the level distal from the substrate (112); anda second connecting portion (134) connected to an outermost of the plurality of turns (124, 126, 128); anda dielectric material (116, 121) containing the first and second connecting portions (130, 134) and the plurality of turns (124, 126, 128).
- The inductor of claim 6 comprising:a first level first turn (150'-128) over the substrate (112);a first dielectric layer (118) over the substrate (112) and the first level first turn (150'-128), the first dielectric layer (118) having provided therein a first turn first via opening connected to the first level first turn (150'-128);a second level second turn (150"-126) over the first dielectric layer (118);a second level first turn (150"-128) over the first dielectric layer (118) and in the first turn first via opening connected to the first level first turn (150'-128); anda second dielectric layer (120) over the first dielectric layer (118), the second level second turn (150"-126), and the second level first turn (150"-128).
- The 3-D spiral stacked inductor as claimed in claim 7 wherein:the second dielectric layer (120) has provided therein a first turn second via opening anda second turn second via opening respectively connected to the second level first turn (150"-128) and second level second turn (150"-126);and including:a third level third turn (150"'-124) over the second dielectric layer (120);a third level second turn (150"'-126) over the second dielectric layer (120) and in the second turn second via opening connected to the second level second turn (150"-126);a third level first turn (150"'-128) over the second dielectric layer (120) and in the first turn second via opening connected to the second level first turn (150"-128); anda third dielectric layer (121) over the second dielectric layer (120), the third level third turn (150"'-124), the third level second turn (150"'-126), and the third level first turn (150"'-128).
- The 3-D spiral stacked inductor as claimed in claim 7 including:a first connecting portion (130) under the first level first turn (150'-128) and connected to the second level second turn (150"-126) and/or the third level third turn (150"'-124) and/or the fourth level fourth turn.
- The 3-D spiral stacked inductor as claimed in claim 7 including:a second connecting portion (134) connected to the second level first turn (150"-128) and/or the third level first turn (150"'-128) and/or the fourth level first turn.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US131336 | 1998-08-07 | ||
US10/131,336 US6841847B2 (en) | 2002-09-04 | 2002-09-04 | 3-D spiral stacked inductor on semiconductor material |
Publications (3)
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EP1396875A2 EP1396875A2 (en) | 2004-03-10 |
EP1396875A3 EP1396875A3 (en) | 2006-06-07 |
EP1396875B1 true EP1396875B1 (en) | 2008-11-19 |
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EP03019916A Expired - Lifetime EP1396875B1 (en) | 2002-09-04 | 2003-09-02 | 3-D spiral stacked inductor on semiconductor material |
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EP (1) | EP1396875B1 (en) |
JP (1) | JP4505201B2 (en) |
AT (1) | ATE414990T1 (en) |
DE (1) | DE60324748D1 (en) |
SG (2) | SG109527A1 (en) |
Families Citing this family (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050104158A1 (en) * | 2003-11-19 | 2005-05-19 | Scintera Networks, Inc. | Compact, high q inductor for integrated circuit |
US7283029B2 (en) * | 2004-12-08 | 2007-10-16 | Purdue Research Foundation | 3-D transformer for high-frequency applications |
US7221251B2 (en) * | 2005-03-22 | 2007-05-22 | Acutechnology Semiconductor | Air core inductive element on printed circuit board for use in switching power conversion circuitries |
US7399696B2 (en) * | 2005-08-02 | 2008-07-15 | International Business Machines Corporation | Method for high performance inductor fabrication using a triple damascene process with copper BEOL |
TWI299556B (en) * | 2006-07-07 | 2008-08-01 | Holtek Semiconductor Inc | Spiral inductor with high quality factor of integrated circuit |
CN101090025B (en) * | 2007-05-25 | 2012-10-03 | 威盛电子股份有限公司 | Helix induction element with multilayer structure |
JP5578797B2 (en) * | 2009-03-13 | 2014-08-27 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
TWI385680B (en) * | 2009-05-19 | 2013-02-11 | Realtek Semiconductor Corp | Stacked structure of a spiral inductor |
US8143952B2 (en) | 2009-10-08 | 2012-03-27 | Qualcomm Incorporated | Three dimensional inductor and transformer |
US8319564B2 (en) * | 2010-03-26 | 2012-11-27 | Altera Corporation | Integrated circuits with configurable inductors |
US8692608B2 (en) | 2011-09-19 | 2014-04-08 | United Microelectronics Corp. | Charge pump system capable of stabilizing an output voltage |
US9030221B2 (en) | 2011-09-20 | 2015-05-12 | United Microelectronics Corporation | Circuit structure of test-key and test method thereof |
US8395455B1 (en) | 2011-10-14 | 2013-03-12 | United Microelectronics Corp. | Ring oscillator |
US8421509B1 (en) | 2011-10-25 | 2013-04-16 | United Microelectronics Corp. | Charge pump circuit with low clock feed-through |
US8588020B2 (en) | 2011-11-16 | 2013-11-19 | United Microelectronics Corporation | Sense amplifier and method for determining values of voltages on bit-line pair |
CN102522388B (en) * | 2011-12-22 | 2015-11-11 | 上海华虹宏力半导体制造有限公司 | Inductance and formation method |
US8493806B1 (en) | 2012-01-03 | 2013-07-23 | United Microelectronics Corporation | Sense-amplifier circuit of memory and calibrating method thereof |
US8970197B2 (en) | 2012-08-03 | 2015-03-03 | United Microelectronics Corporation | Voltage regulating circuit configured to have output voltage thereof modulated digitally |
US8724404B2 (en) | 2012-10-15 | 2014-05-13 | United Microelectronics Corp. | Memory, supply voltage generation circuit, and operation method of a supply voltage generation circuit used for a memory array |
US8836460B2 (en) * | 2012-10-18 | 2014-09-16 | International Business Machines Corporation | Folded conical inductor |
US8669897B1 (en) | 2012-11-05 | 2014-03-11 | United Microelectronics Corp. | Asynchronous successive approximation register analog-to-digital converter and operating method thereof |
US8711598B1 (en) | 2012-11-21 | 2014-04-29 | United Microelectronics Corp. | Memory cell and memory cell array using the same |
US8873295B2 (en) | 2012-11-27 | 2014-10-28 | United Microelectronics Corporation | Memory and operation method thereof |
US8643521B1 (en) | 2012-11-28 | 2014-02-04 | United Microelectronics Corp. | Digital-to-analog converter with greater output resistance |
US8953401B2 (en) | 2012-12-07 | 2015-02-10 | United Microelectronics Corp. | Memory device and method for driving memory array thereof |
US9030886B2 (en) | 2012-12-07 | 2015-05-12 | United Microelectronics Corp. | Memory device and driving method thereof |
US8917109B2 (en) | 2013-04-03 | 2014-12-23 | United Microelectronics Corporation | Method and device for pulse width estimation |
US9105355B2 (en) | 2013-07-04 | 2015-08-11 | United Microelectronics Corporation | Memory cell array operated with multiple operation voltage |
US9831026B2 (en) * | 2013-07-24 | 2017-11-28 | Globalfoundries Inc. | High efficiency on-chip 3D transformer structure |
US9251948B2 (en) | 2013-07-24 | 2016-02-02 | International Business Machines Corporation | High efficiency on-chip 3D transformer structure |
US9171663B2 (en) | 2013-07-25 | 2015-10-27 | Globalfoundries U.S. 2 Llc | High efficiency on-chip 3D transformer structure |
US9779869B2 (en) | 2013-07-25 | 2017-10-03 | International Business Machines Corporation | High efficiency on-chip 3D transformer structure |
US8947911B1 (en) | 2013-11-07 | 2015-02-03 | United Microelectronics Corp. | Method and circuit for optimizing bit line power consumption |
US8866536B1 (en) | 2013-11-14 | 2014-10-21 | United Microelectronics Corp. | Process monitoring circuit and method |
US9143143B2 (en) | 2014-01-13 | 2015-09-22 | United Microelectronics Corp. | VCO restart up circuit and method thereof |
KR20160058592A (en) * | 2014-11-17 | 2016-05-25 | 에스케이하이닉스 주식회사 | RF integrated circuit and method of fabricating the same |
US9653204B2 (en) | 2015-01-22 | 2017-05-16 | Globalfoundries Inc. | Symmetric multi-port inductor for differential multi-band RF circuits |
US10249580B2 (en) * | 2016-06-22 | 2019-04-02 | Qualcomm Incorporated | Stacked substrate inductor |
US10525690B2 (en) | 2016-09-07 | 2020-01-07 | General Electric Company | Additive manufacturing-based low-profile inductor |
US10199157B2 (en) * | 2016-09-30 | 2019-02-05 | Intel IP Corporation | Stacked metal inductor |
TWI723343B (en) * | 2019-02-19 | 2021-04-01 | 頎邦科技股份有限公司 | Semiconductor structure having 3d inductor and manufacturing method thereof |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2938631B2 (en) * | 1991-08-28 | 1999-08-23 | 太陽誘電株式会社 | Manufacturing method of multilayer ceramic inductor |
JPH06163270A (en) * | 1992-11-19 | 1994-06-10 | Murata Mfg Co Ltd | Multilayered board |
JPH07106514A (en) * | 1993-10-07 | 1995-04-21 | Toshiba Corp | Semiconductor integrated circuit device |
US5446311A (en) * | 1994-09-16 | 1995-08-29 | International Business Machines Corporation | High-Q inductors in silicon technology without expensive metalization |
JP2904086B2 (en) * | 1995-12-27 | 1999-06-14 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
US5831331A (en) * | 1996-11-22 | 1998-11-03 | Philips Electronics North America Corporation | Self-shielding inductor for multi-layer semiconductor integrated circuits |
JP3164025B2 (en) * | 1997-08-04 | 2001-05-08 | 日本電気株式会社 | Semiconductor integrated circuit device and method of manufacturing the same |
KR100279753B1 (en) * | 1997-12-03 | 2001-03-02 | 정선종 | Inductor manufacturing method using semiconductor integrated circuit manufacturing process |
JPH11224825A (en) * | 1998-02-06 | 1999-08-17 | Murata Mfg Co Ltd | Manufacture of electronic component |
US6426267B2 (en) * | 1998-06-19 | 2002-07-30 | Winbond Electronics Corp. | Method for fabricating high-Q inductance device in monolithic technology |
US6472285B1 (en) * | 1999-04-30 | 2002-10-29 | Winbond Electronics Corporation | Method for fabricating high-Q inductance device in monolithic technology |
US6054914A (en) * | 1998-07-06 | 2000-04-25 | Midcom, Inc. | Multi-layer transformer having electrical connection in a magnetic core |
TW386279B (en) * | 1998-08-07 | 2000-04-01 | Winbond Electronics Corp | Inductor structure with air gap and method of manufacturing thereof |
DE69931670T2 (en) * | 1998-12-11 | 2006-09-21 | Matsushita Electric Industrial Co., Ltd., Kadoma | High-frequency inductance with high Q-factor |
JP2002246231A (en) * | 2001-02-14 | 2002-08-30 | Murata Mfg Co Ltd | Laminated inductor |
-
2002
- 2002-09-04 US US10/131,336 patent/US6841847B2/en not_active Expired - Lifetime
-
2003
- 2003-09-02 SG SG200305645A patent/SG109527A1/en unknown
- 2003-09-02 SG SG200505168-5A patent/SG151088A1/en unknown
- 2003-09-02 DE DE60324748T patent/DE60324748D1/en not_active Expired - Lifetime
- 2003-09-02 AT AT03019916T patent/ATE414990T1/en not_active IP Right Cessation
- 2003-09-02 EP EP03019916A patent/EP1396875B1/en not_active Expired - Lifetime
- 2003-09-04 JP JP2003312890A patent/JP4505201B2/en not_active Expired - Fee Related
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US7721414B2 (en) | 2010-05-25 |
JP4505201B2 (en) | 2010-07-21 |
SG109527A1 (en) | 2005-03-30 |
US6841847B2 (en) | 2005-01-11 |
EP1396875A3 (en) | 2006-06-07 |
US20050057335A1 (en) | 2005-03-17 |
JP2004104129A (en) | 2004-04-02 |
DE60324748D1 (en) | 2009-01-02 |
EP1396875A2 (en) | 2004-03-10 |
SG151088A1 (en) | 2009-04-30 |
ATE414990T1 (en) | 2008-12-15 |
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