EP1396777B1 - Composant semi-conducteur pour régler le déplacement de la tension de seuil provoqué par l'effet de canal court - Google Patents

Composant semi-conducteur pour régler le déplacement de la tension de seuil provoqué par l'effet de canal court Download PDF

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Publication number
EP1396777B1
EP1396777B1 EP02028136A EP02028136A EP1396777B1 EP 1396777 B1 EP1396777 B1 EP 1396777B1 EP 02028136 A EP02028136 A EP 02028136A EP 02028136 A EP02028136 A EP 02028136A EP 1396777 B1 EP1396777 B1 EP 1396777B1
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Prior art keywords
circuit
transistors
semiconductor device
test circuit
dut
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Expired - Fee Related
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EP02028136A
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German (de)
English (en)
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EP1396777A1 (fr
Inventor
Rafael Nadal Guardia
Joerg Berthold
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Infineon Technologies AG
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Infineon Technologies AG
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage

Definitions

  • the present invention generally relates to a semiconductor device and more specific to a semiconductor device for detecting and adjusting leakage current dependent on threshold voltage of an integrated semiconductor device implemented in sub-micron technology, i.e. transistors, and a method related thereto.
  • FIG. 1 shows a cross-section of a state of the art NMOS transistor in sub-micron technology on a bulk or wafer 6.
  • the distance between n-doped-source 1 and -drain 2 under gate 3 in a p-doped-well 5 is referred to as the channel length 4.
  • a small channel length variation which may be caused by tolerances in the fabrication process, can shift the threshold voltage value around 80 mV.
  • Figure 2 shows the qualitative evolution of the threshold voltage value versus the channel length L in logarithmic scale.
  • V t minimum length transistors with low threshold voltage values (V t ) are implemented (with V t in the range from 0 mV to 400 mV), a small variation of the channel length has great impact on the threshold voltage value (see Fig. 2). This effect is referred to as Short Channel Effect. Therefore, the shift due to the uncertainty introduced in the channel length has a great impact in the performance of the device. Moreover, the impact on the performance of the circuits provided with these transistors is also highly affected in terms of static and dynamic terms. For digital circuits, static and dynamic power consumption increases and the performance in terms of speed is also affected. With regard to these problems, it is necessary to implement any kind of strategy capable to determine whether the length of minimum length devices (NMOS and PMOS transistors) is shifted and therefore causes a change in the threshold voltage value V t .
  • NMOS and PMOS transistors NMOS and PMOS transistors
  • V t can also change by reason of the doping dose used to implant the channel or a change in the thickness of the gate oxide.
  • the doping dose and thickness of the oxide will determine the status of the transistors. Three different status are allocated, "fast”, “nominal” and “slow” corresponding to small, nominal and high value of V t , respectively. Short channel effects can appear in any one of these status of the technology.
  • US 4,789,825 provides method for classifying integrated circuit chips into good an bad chips depending on the influence of a potential short channel effect.
  • An integrated circuit having one test field effect transistor and one reference field effect transistor is disclosed wherein the test transistor may suffer from a short channel effect and the reference transistor is designed to have a long channel length. By monitoring and comparing the current running through the test and reference transistor, a decision is reached as to the entire chip is well or badly functioning.
  • Such as a decision may be indicated by a flag to a test pad on the chip or used to disable operation of the entire integrated circuit or, otherwise, used to provide an indication.
  • US 6,091,283 describes a sub-threshold leakage tuning circuit which aims to compensate for process, activity and temperature-induced device threshold variations in a semiconductor circuit having a transistor, a potential of the gate wherein the transistor is held to a preset subthreshold potential and a channel current of the channel region is compared with a reference current to obtain a comparison result.
  • a bias potential of a substrate is adjusted according to the comparison result to hold the subthreshold current at the reference current.
  • the reference current is provided by a separate reference source.
  • the device under test (DUT) is configured in a circuit in which the current is compared with said isolated reference current.
  • the proposed method does only provide a solution for compensation for changes in device characteristics across process and temperature.
  • Another well known strategy is based on detection of the off current.
  • some of these strategies require the use of band gap references to allow proper operation for a large range of temperatures.
  • none of these strategies allow to compare the performance of a DUT with the performance of a long channel device operating as a reference without requiring any additional temperature reference circuit.
  • a semiconductor device comprising a test circuit containing a set of several transistors connected in parallel as a device under test, the transistors each having a drain, a source, a gate and a channel region under the gate between the drain and the source in a well with a short channel length, the well having an adjustable well potential; a reference circuit containing a set of several transistors connected in parallel as a reference device, the transistors each having a drain, a source, a gate and a channel region under the gate between the drain and the source in a well with a long channel length, the well having a fixed reference well potential; a comparator circuit comparing an output of the test circuit with an output of the reference circuit and providing a comparison result; a bias circuit providing a bias potential to the wells of the test circuit when the output of the test circuit is smaller than output of the reference circuit; wherein the circuits are implemented on the same dye with other digital circuits and the bias potential is applied to wells of said other digital circuits.
  • the new method is based on the use of a group of parallel DUTs, implemented with minimum length, which are compared with a group of reference devices, designed with long channel length. It is understood that said bias circuit is implemented on the same bulk or substrate as the test and reference circuit but may also be an external circuit.
  • the control of the well potential is established by means of comparison of a device under test (DUT) with adjustable well potential and a long channel device as a reference device (Reference) with a fixed well potential. Providing an appropriate potential to the well of the DUT leads to an increase of the absolute value of the threshold voltage and a decrease of the leakage current of the DUT.
  • the well potential can be set to a fixed value referring to a minimum of the leakage current or adjusted in steps.
  • a reference circuit with one or more transistors with long channels is used to provide the reference in the semiconductor device according to the invention, the output of the reference circuit is smaller than that of the test circuit whenever the DUT is not affected by the Short Channel Effect.
  • the shift of the threshold voltage due to the Short Channel Effect is detected and adjusted but not the variations due to changes in temperature or process.
  • This achievement is enhanced by implementation of the test and the reference circuit on the same die of the semiconductor device and so that they are subject to the same temperature and process variations.
  • a set of devices, i.e. transistors both in the reference circuit and the test circuit a shift due to statistical variations of the threshold voltage is avoided.
  • temperature variations are affecting to the output voltage of both circuits in a similar way. Therefore, it is not necessary to provide any kind of temperature compensation for a large range of operating temperatures.
  • a proper circuit design in the proposed invention allows only detection of the variation of V t due to short channel effects.
  • the short channel effects due to variations during the fabrication process will be common for all the implemented transistors in a wafer.
  • variations in the doping profile or the thickness of the gate oxide layer are also taken into account in the proposed invention.
  • several devices in parallel can be implemented.
  • the semiconductor device of the proposed invention can be applied to sense the off-current or the current in saturation of the DUT and the reference device.
  • the method is not limited to cut-off operation of the devices.
  • the proposed compensation of the threshold voltage variation can be based on voltage monitoring or current detection.
  • the comparator circuit In a current mode the comparator circuit is addressed to achieve a fixed ratio between the current of the DUT and the reference circuit. In this mode, said comparator circuit compares the drain current of the test circuit with the drain current of the reference circuit and provides a comparison result and said bias circuit provides a bias potential to the well of the test circuit when the drain current of the test circuit is smaller than the drain current of the reference circuit.
  • a voltage mode the output voltage of the DUT and the Reference circuit are monitored.
  • a first sensing element is connected to the drain of the DUT providing a test circuit output voltage according to the drain current of the test circuit.
  • a second sensing element is connected to the drain of the reference device providing a reference circuit output voltage according to the drain current of the reference circuit.
  • Said comparator circuit compares the output voltage of the test circuit with the output voltage of the reference circuit and said bias circuit provides a bias potential to the well of the test circuit when the output voltage of the test circuit is smaller than the output voltage of the reference circuit.
  • the DUT and the Reference device can either work in saturation region or in cut-off region.
  • the invention can be easily applied to control current consumption during the dynamic or the static operation of digital circuits.
  • the control of the well potential of the DUT taking the output of the reference circuit as reference value in the comparator allows the adjustment of the current flowing through a sensing element. Therefore the applied value in the well of the DUT can be also applied to the digital circuits implemented in the same die.
  • FIG. 3 there are three constitutive circuit blocks that are required for detecting the V t value variations.
  • DUT device under test
  • a second circuit block 8 with a reference device and a third circuit block 9 with a comparator for comparing the outputs of the test circuit and the reference circuit.
  • the well potential can be applied by a charge pump in a well potential bias circuit 10, for instance.
  • the test circuit contains the DUT and the reference circuit contains the reference devices on a wafer 11.
  • both circuit blocks comprise a sensing element.
  • the sensing element is a device providing a voltage drop caused by the current flowing through it. The current depends on the V t of the DUT in the test circuit or the reference devices in the reference circuit.
  • the sensing element is connected between V DD and the drain of the DUT in the case of an NMOS DUT.
  • a similar configuration is implemented for the reference circuit.
  • the sensing element is connected between VSS and the drain of the PMOS devices.
  • the output voltage is taken in the drain of the DUTs and the drain of the reference devices.
  • the sensing element can be implemented with a resistor or a long channel transistor.
  • Adjustment of the threshold voltage is carried out comparing the output voltage of the test circuit 7 and the reference circuit 8.
  • the well potential of the DUT is not adjusted.
  • the output voltage of the test circuit 7 is smaller, the well potential is decreased for the NMOS DUTs and increased for the PMOS DUTs.
  • the well potential is changed up to the point in which the output of the test circuit 7 is equal to the output of the reference circuit 8.
  • the output of the reference circuit 8 is maintained constant because the well potential of the reference devices is not changed. It is important to notice that only in the case of having short channel effects in the DUT, the output voltage in the test circuit 7 is smaller than the output voltage in the reference circuit 8.
  • the reference device and the device under test are a set of devices in order to avoid the shifting due to statistical variations of V t .
  • the output voltage is only affected by variations due to the length of the transistors.
  • a PMOS transistor with the gate connected to its drain is used as sensing element.
  • the detection of the V t shift is carried out for "fast”, “slow", and “nominal” transistors. That is, the method is capable to determine when the shift in the V t value is due to short channel effects or only to a change in the status of the devices (that is "fast”, “slow” or “nom.”).
  • the semiconductor device according to the present invention will compensate the case in which the shift in V t is only due to the short channel effect.
  • the output of the reference circuit is always greater than that of the DUT affected by the short channel effects ("Fast DUT” line for Fig. 7, "Fast NMOS DUT” line in Fig. 8, "Nom. DUT” line in Fig. 9, “Slow NMOS DUT” line in Fig. 10, and “Slow DUT” in Fig. 11).
  • the current consumption control would be carried out as depicted in Fig. 12.
  • the comparator would switch on or switch off the well potential bias block.
  • the adjustment of the well potential can be easily implemented with charge pump circuits.
  • the following example illustrates the detection of Vt and leakage control method based on the saturation regime of the DUTs and the reference devices.
  • the DUT and the reference devices are working in saturation.
  • the saturation can be fixed by connecting the gate of the NMOS DUTs and the reference devices to VDD. If low current consumption is desired, it is also possible to fix the gates to a lower voltage value allowing also saturation operating conditions, see Fig. 16.
  • the same implementation presented in Fig. 4 and 5 will be also used in the case in which the gate of the DUTs and the reference transistors would be connected to voltage values allowing operation in saturation regime.
  • the same operating principle pointed out above is also observed when the saturation current is detected. In nominal operating status, only the short channel effect is detected, and the detection is carried out for the operating temperature range as depicted in Fig. 17.
  • FIG. 19 shows a block diagram for current comparison when NMOS devices are considered.
  • the configuration in which the devices work in cut-off regime is depicted in Fig. 20 whereas Fig. 21 shows a configuration in which the transistors are working in saturation regime.
  • the gate of the transistors are tied to a desired value so that they operate in saturation regime whereby the current consumption is adjusted.
  • the control of the leakage current for a digital circuit would be establish as depicted in Fig. 23.
  • the connection of the gate of the DUT and the reference devices can be any of the implemented in Fig. 20, Fig. 21, and Fig. 22.

Claims (13)

  1. Composant semi-conducteur comportant :
    a) un circuit d'essai (7) contenant un jeu de différents transistors reliés en parallèle comme un composant à l'essai (DUT), les transistors ayant chacun un drain (2), une source (1), une grille (3) et une zone de canal (4) sous la grille (3) entre le drain et la source dans un puits (5) disposant d'une longueur de canal court, le puits ayant un potentiel de puits réglable,
    b) un circuit de référence (8) contenant un jeu de différents transistors reliés en parallèle comme un composant de référence, les transistors ayant chacun un drain (2), une source (1), une grille (3) et une zone de canal (4) sous la grille entre le drain et la source dans un puits (5) disposant d'une longueur de canal long, le puits ayant un potentiel de puits fixe,
    c) un circuit comparateur (9) comparant une sortie du circuit d'essai (7) avec une sortie du circuit de référence (8) et fournissant un résultat de comparaison,
    d) un circuit de polarisation (10) fournissant un potentiel de polarisation aux puits (5) du circuit d'essai (7) quand la sortie du circuit d'essai (7) est inférieure à la sortie du circuit de référence (8),
    e) dans lequel les circuits (7, 8, 9, 10) sont mis en oeuvre sur la même matrice avec d'autres circuits numériques (12) et le potentiel de polarisation est appliqué aux puits desdits autres circuits numériques (12).
  2. Composant semi-conducteur selon la revendication 1,
    caractérisé par le fait que
    - ledit circuit comparateur (9) est réglé de telle sorte qu'il peut comparer un courant de drain du circuit d'essai (7) avec un courant de drain du circuit de référence (8) et fournir un résultat de comparaison,
    - ledit circuit de polarisation (10) est réglé de telle sorte qu'il peut fournir un potentiel de polarisation aux puits (5) du circuit d'essai et aux puits d'autres circuits numériques (12) quand le courant de drain du circuit d'essai (7) est inférieur au courant de drain du circuit de référence (8).
  3. Composant semi-conducteur selon la revendication 2,
    caractérisé par le fait que les grilles (3) desdits transistors du circuit d'essai (DUT) et desdits transistors du circuit de référence sont reliées à la masse de telle sorte que les transistors fonctionnent en régime de coupure.
  4. Composant semi-conducteur selon la revendication 2,
    caractérisé par le fait que les grilles (3) desdits transistors du circuit d'essai (DUT) et desdits transistors du circuit de référence sont liées à une tension fixe de telle sorte que les transistors fonctionnent en régime de saturation.
  5. Composant semi-conducteur selon la revendication 1,
    caractérisé par le fait que
    - un premier élément de détection est relié aux drains du DUT dans le circuit d'essai (7) fournissant une tension de sortie du circuit d'essai selon un courant de drain du circuit d'essai (7),
    - un second élément de détection est relié aux drains du composant de référence fournissant une tension de sortie de circuit de référence (8) selon un courant de drain du circuit de référence (8),
    - ledit circuit comparateur (9) est réglé de telle sorte qu'il peut comparer la tension de sortie du circuit d'essai (7) avec la tension de sortie du circuit de référence (8),
    - ledit circuit de polarisation (10) est réglé de telle sorte qu'il peut fournir un potentiel de polarisation aux puits (5) du circuit d'essai et aux puits d'autres circuits numériques (12) quand la tension de sortie du circuit d'essai (7) est inférieure à la tension de sortie du circuit de référence (8).
  6. Composant semi-conducteur selon la revendication 5,
    caractérisé par le fait que les grilles (3) desdits transistors du circuit d'essai (DUT) et desdits transistors du circuit de référence sont reliées à la masse de telle sorte que les transistors fonctionnent en régime de coupure.
  7. Composant semi-conducteur selon la revendication 5,
    caractérisé par le fait que les grilles (3) desdits transistors du circuit d'essai (DUT) et desdits transistors du circuit de référence sont liées à une tension fixe de telle sorte que les transistors fonctionnent en régime de saturation.
  8. Composant semi-conducteur selon la revendication 5,
    caractérisé par le fait que lesdits transistors du circuit d'essai et du circuit de référence sont des transistors MOS à canal N.
  9. Composant semi-conducteur selon la revendication 8,
    caractérisé par le fait que ledit premier élément de détection est branché entre les drains du DUT et la tension VDD du composant semi-conducteur et que ledit second élément de détection est branché entre les drains du composant de référence et la tension VDD du composant semi-conducteur.
  10. Composant semi-conducteur selon la revendication 5,
    caractérisé par le fait que lesdits transistors du circuit d'essai et du circuit de référence sont des transistors MOS à canal P.
  11. Composant semi-conducteur selon la revendication 10,
    caractérisé par le fait que ledit premier élément de détection est branché entre les drains du DUT et la tension VSS du composant semi-conducteur et que ledit second élément de détection est branché entre les drains du composant de référence et la tension VSS du composant semi-conducteur.
  12. Composant semi-conducteur selon la revendication 1,
    caractérisé par le fait que ledit circuit de polarisation fournit un potentiel de polarisation aux puits du circuit d'essai et aux puits des autres circuits numériques (12) jusqu'à ce que la sortie du circuit d'essai soit égale à la sortie du circuit de référence.
  13. Semi-conducteur selon la revendication 1
    caractérisé par le fait que ledit circuit de polarisation comporte une pompe de charge en tant que source de tension.
EP02028136A 2002-08-30 2002-12-18 Composant semi-conducteur pour régler le déplacement de la tension de seuil provoqué par l'effet de canal court Expired - Fee Related EP1396777B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/640,417 US7030637B2 (en) 2002-08-30 2003-08-13 Semiconductor device for adjusting threshold value shift due to short channel effect

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10240177 2002-08-30
DE10240177 2002-08-30

Publications (2)

Publication Number Publication Date
EP1396777A1 EP1396777A1 (fr) 2004-03-10
EP1396777B1 true EP1396777B1 (fr) 2007-04-04

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EP02028136A Expired - Fee Related EP1396777B1 (fr) 2002-08-30 2002-12-18 Composant semi-conducteur pour régler le déplacement de la tension de seuil provoqué par l'effet de canal court

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DE (1) DE60219309T2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2890239B1 (fr) * 2005-08-31 2008-02-01 St Microelectronics Crolles 2 Compensation des derives electriques de transistors mos

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2447610A1 (fr) * 1979-01-26 1980-08-22 Commissariat Energie Atomique Generateur de tension de reference et circuit de mesure de la tension de seuil d'un transistor mos, applicable a ce generateur de tension de reference
US4346344A (en) * 1979-02-08 1982-08-24 Signetics Corporation Stable field effect transistor voltage reference
JP2592234B2 (ja) * 1985-08-16 1997-03-19 富士通株式会社 半導体装置
US4789825A (en) * 1986-05-14 1988-12-06 American Telephone And Telegraph Co., At&T Bell Laboratories Integrated circuit with channel length indicator
US6091283A (en) * 1998-02-24 2000-07-18 Sun Microsystems, Inc. Sub-threshold leakage tuning circuit

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* Cited by examiner, † Cited by third party
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DE60219309T2 (de) 2008-01-03
EP1396777A1 (fr) 2004-03-10
DE60219309D1 (de) 2007-05-16

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