EP1364399A1 - Semiconductor chip and production method for a housing - Google Patents
Semiconductor chip and production method for a housingInfo
- Publication number
- EP1364399A1 EP1364399A1 EP02714075A EP02714075A EP1364399A1 EP 1364399 A1 EP1364399 A1 EP 1364399A1 EP 02714075 A EP02714075 A EP 02714075A EP 02714075 A EP02714075 A EP 02714075A EP 1364399 A1 EP1364399 A1 EP 1364399A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- compound
- semiconductor chip
- encapsulation
- upper side
- encapsulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims description 69
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 150000001875 compounds Chemical class 0.000 claims abstract description 100
- 238000005266 casting Methods 0.000 claims abstract description 10
- 239000011248 coating agent Substances 0.000 claims abstract description 8
- 238000000576 coating method Methods 0.000 claims abstract description 8
- 238000005538 encapsulation Methods 0.000 claims description 42
- 238000004382 potting Methods 0.000 claims description 14
- 230000004888 barrier function Effects 0.000 claims description 13
- 238000007789 sealing Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 7
- 239000008393 encapsulating agent Substances 0.000 claims description 3
- 238000009736 wetting Methods 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims 3
- 230000001678 irradiating effect Effects 0.000 abstract 1
- 230000006978 adaptation Effects 0.000 description 5
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/12—Fingerprints or palmprints
- G06V40/13—Sensors therefor
- G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present invention relates to a semiconductor chip which is intended to be partially provided with a covering of the connection contact surfaces and / or the bonding wires, which is referred to as the housing, after mounting on a chip carrier, certain active regions of the upper side remaining free, and a production method for a such housing.
- connection contact surfaces of semiconductor chips are usually connected to a chip carrier, on which the semiconductor chip is mounted, via the connection contact surfaces referred to as bond pads.
- Common connection methods are e.g. B. wire bonding, in which the connection contact surfaces of the semiconductor chip and the connection contact surfaces of the chip carrier are connected to one another in pairs by soldered wires, and flip-chip bonding, in which the upper-side contacts of the semiconductor chip are attached directly to assigned contact surfaces of the chip carrier become.
- the semiconductor chip is therefore usually enclosed in a so-called housing by injecting it into a casting compound or covering it with an encapsulating compound. All connections between the chip and the chip carrier and at least the entire active area of the chip are encased.
- this barrier prevents the encapsulation compound or encapsulation compound from flowing into those active chip areas that are to remain free. The barrier can then be removed. The additional attachment of such a barrier requires additional effort and thus additional costs; in special cases, a selective encapsulation of the semiconductor chip can thus only be implemented with difficulty or not at all.
- the object of the present invention is to provide an improved possibility for a selective encapsulation of a semiconductor chip.
- the selective encapsulation is achieved by a specially designed semiconductor chip with a selectively adapted surface or by a method for applying the encapsulation compound or encapsulation compound, in which the encapsulation compound or encapsulation compound is prevented from flowing onto the portions of the chip surface to be left free.
- a semiconductor chip according to the invention has a first portion of the upper side, which is intended to be covered by a potting compound or encapsulating compound of a housing, and a second portion of the upper side, which is intended to remain free of the encapsulating compound or encapsulating compound. The surface of the semiconductor chip in the first portion and in the second portion of the upper side are thus unrelated to one another.
- the proportions can be differentiated from one another by a flat selective adaptation of the respective surfaces to the different requirements or by a structural limitation by means of a barrier formed on the surface of the semiconductor chip.
- a selective adaptation of the chip surface can be brought about by the fact that different materials and / or structures on the chip surface in the portion to be covered by the encapsulation compound or encapsulation compound and the portion of the top side of the semiconductor chip to be left free provide different wettability or different adhesion properties of the encapsulation compound used or coating mass can be achieved. Flowing of the potting compound or encapsulating compound can thus be limited to part of the surface of the semiconductor chip.
- the other possibility mentioned of differentiating the portions of the chip surface by means of a structural limitation consists in delimiting the area of the upper side of the chip to be covered by the housing by means of a barrier which is structured directly on the chip surface and is in particular designed as a dam or trench.
- connection contact areas 3 bond pads
- connection contact areas 4 on the carrier 2 via bond wires 5.
- the connection contact surfaces and bonding wires are to be mechanically protected, which is done here with a suitable cover made of a sealing compound or encapsulating compound.
- This contact surface 6 is part of a fingerprint sensor, for which part of the circuit integrated in the semiconductor chip is provided.
- a covering of the bonding wires 5 by a potting compound or encapsulation compound 8 may therefore not cover this contact surface 6.
- the figure shows that the potting compound or encapsulation compound 8 covers the connection contact surfaces 3, 4 and the bonding wires 5 in a protected area 12 on the top side of the semiconductor chip 1 and thus protects, but not the entire semiconductor chip 1 from the encapsulation compound or encapsulation compound 8 is covered.
- the surface of the portion to be left free from the potting compound or encapsulating compound can be designed according to the invention in such a way that wetting, flowing or adhering to the encapsulating compound or encapsulating compound is prevented or at least made more difficult there.
- This is achieved in particular by a locally limited coating of the surface of the semiconductor chip with a suitable material or by a flat structuring, such as for example roughening, of the surface of the semiconductor chip in the relevant portion of the top side of the semiconductor chip.
- a structural limitation of the portions of the upper side of the semiconductor chip to be covered or left free by a barrier applied to the surface of the semiconductor chip is, for example, a dam or trench.
- the dam 7 shown in the figure, which surrounds the bearing surface ⁇ to be left free in the example shown, can be provided according to the invention to stop the pouring of the potting compound or encapsulating compound.
- the edge 10 of the sealing compound or encapsulant present on the upper side of the semiconductor chip then runs along this dam.
- a trench which is sufficient, particularly in the case of an already moderate lack of sealing of the encapsulation compound or encapsulation compound, to provide a precisely defined edge as a limitation of the encapsulation compound or encapsulation compound along a predetermined limit of the portion of the top side of the semiconductor chip that is to be left free to create. This can be the case, for example, if only a small amount of the casting compound or coating compound is applied or injected and / or if the surface of the semiconductor chip is selectively adapted according to the invention. ) M t » ⁇ »
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Multimedia (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10109327 | 2001-02-27 | ||
DE10109327A DE10109327A1 (en) | 2001-02-27 | 2001-02-27 | Semiconductor chip and manufacturing method for a package |
PCT/DE2002/000714 WO2002069386A1 (en) | 2001-02-27 | 2002-02-27 | Semiconductor chip and production method for a housing |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1364399A1 true EP1364399A1 (en) | 2003-11-26 |
Family
ID=7675599
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP02714075A Withdrawn EP1364399A1 (en) | 2001-02-27 | 2002-02-27 | Semiconductor chip and production method for a housing |
Country Status (6)
Country | Link |
---|---|
US (1) | US6876090B2 (en) |
EP (1) | EP1364399A1 (en) |
JP (1) | JP2004521497A (en) |
DE (1) | DE10109327A1 (en) |
IL (1) | IL157598A0 (en) |
WO (1) | WO2002069386A1 (en) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2839570B1 (en) | 2002-05-07 | 2004-09-17 | Atmel Grenoble Sa | METHOD OF MANUFACTURING FINGERPRINT SENSOR AND CORRESPONDING SENSOR |
DE10300171A1 (en) * | 2003-01-08 | 2004-07-22 | Hella Kg Hueck & Co. | Electronic unit has metal housing part with at least the inner surface roughened by sand blasting, electronic components in interior of housing and setting material filling interior of housing |
US7697729B2 (en) | 2004-01-29 | 2010-04-13 | Authentec, Inc. | System for and method of finger initiated actions |
ATE469403T1 (en) * | 2004-09-02 | 2010-06-15 | Nxp Bv | IDENTIFICATION DOCUMENT WITH CONTACTLESS RFID CHIP |
US7831070B1 (en) | 2005-02-18 | 2010-11-09 | Authentec, Inc. | Dynamic finger detection mechanism for a fingerprint sensor |
US8231056B2 (en) | 2005-04-08 | 2012-07-31 | Authentec, Inc. | System for and method of protecting an integrated circuit from over currents |
US7691675B2 (en) * | 2005-10-24 | 2010-04-06 | Hewlett-Packard Development Company, L.P. | Encapsulating electrical connections |
WO2007060812A1 (en) * | 2005-11-22 | 2007-05-31 | Sony Corporation | Semiconductor device and method for manufacturing semiconductor device |
US7632698B2 (en) | 2006-05-16 | 2009-12-15 | Freescale Semiconductor, Inc. | Integrated circuit encapsulation and method therefor |
US8866347B2 (en) | 2010-01-15 | 2014-10-21 | Idex Asa | Biometric image sensing |
US8421890B2 (en) | 2010-01-15 | 2013-04-16 | Picofield Technologies, Inc. | Electronic imager using an impedance sensor grid array and method of making |
CN109407862B (en) | 2012-04-10 | 2022-03-11 | 傲迪司威生物识别公司 | Biometric sensing |
WO2015026288A1 (en) * | 2013-08-23 | 2015-02-26 | Fingerprint Cards Ab | Connection pads for a fingerprint sensing device |
EP3459109B1 (en) | 2016-05-19 | 2021-11-17 | Sencio B.V. | Integrated circuit package and method of manufacturing the same |
CN108962868B (en) * | 2017-05-25 | 2020-07-03 | 矽品精密工业股份有限公司 | Package structure and method for fabricating the same |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1074869A (en) * | 1996-07-31 | 1998-03-17 | Motorola Inc | Electronic part assembly and assembling method |
EP1041628A2 (en) * | 1999-03-29 | 2000-10-04 | Interuniversitair Microelektronica Centrum Vzw | An image sensor ball grid array package and the fabrication thereof |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4143456A (en) * | 1976-06-28 | 1979-03-13 | Citizen Watch Commpany Ltd. | Semiconductor device insulation method |
JPS6132535A (en) * | 1984-07-25 | 1986-02-15 | Sanyo Electric Co Ltd | Manufacture of sensor |
US5219712A (en) * | 1987-11-28 | 1993-06-15 | Thorn Emi Plc | Method of forming a solid article |
GB8727902D0 (en) * | 1987-11-28 | 1987-12-31 | Emi Plc Thorn | Method of forming a solid article |
GB8911607D0 (en) * | 1989-05-19 | 1989-07-05 | Emi Plc Thorn | A method of encapsulation for electronic devices and devices so encapsulated |
US5530278A (en) * | 1995-04-24 | 1996-06-25 | Xerox Corporation | Semiconductor chip having a dam to prevent contamination of photosensitive structures thereon |
JP4024335B2 (en) * | 1996-01-26 | 2007-12-19 | ハリス コーポレイション | Integrated circuit device having an opening exposing die of integrated circuit and manufacturing method thereof |
US5963679A (en) * | 1996-01-26 | 1999-10-05 | Harris Corporation | Electric field fingerprint sensor apparatus and related methods |
US6388199B1 (en) * | 2000-07-31 | 2002-05-14 | Micron Technology, Inc. | Selectively adjusting surface tension of soldermask material |
-
2001
- 2001-02-27 DE DE10109327A patent/DE10109327A1/en not_active Ceased
-
2002
- 2002-02-27 IL IL15759802A patent/IL157598A0/en unknown
- 2002-02-27 EP EP02714075A patent/EP1364399A1/en not_active Withdrawn
- 2002-02-27 JP JP2002568412A patent/JP2004521497A/en not_active Withdrawn
- 2002-02-27 WO PCT/DE2002/000714 patent/WO2002069386A1/en active Application Filing
-
2003
- 2003-08-27 US US10/649,410 patent/US6876090B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1074869A (en) * | 1996-07-31 | 1998-03-17 | Motorola Inc | Electronic part assembly and assembling method |
EP1041628A2 (en) * | 1999-03-29 | 2000-10-04 | Interuniversitair Microelektronica Centrum Vzw | An image sensor ball grid array package and the fabrication thereof |
Non-Patent Citations (1)
Title |
---|
See also references of WO02069386A1 * |
Also Published As
Publication number | Publication date |
---|---|
WO2002069386A1 (en) | 2002-09-06 |
DE10109327A1 (en) | 2002-09-12 |
IL157598A0 (en) | 2004-03-28 |
JP2004521497A (en) | 2004-07-15 |
US20040159961A1 (en) | 2004-08-19 |
US6876090B2 (en) | 2005-04-05 |
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Legal Events
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PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
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Effective date: 20030806 |
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AX | Request for extension of the european patent |
Extension state: AL LT LV MK RO SI |
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