DE4041346B4 - Standard plastic housing with encapsulated semiconductor chips - Google Patents
Standard plastic housing with encapsulated semiconductor chips Download PDFInfo
- Publication number
- DE4041346B4 DE4041346B4 DE4041346A DE4041346A DE4041346B4 DE 4041346 B4 DE4041346 B4 DE 4041346B4 DE 4041346 A DE4041346 A DE 4041346A DE 4041346 A DE4041346 A DE 4041346A DE 4041346 B4 DE4041346 B4 DE 4041346B4
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- Prior art keywords
- island
- chip
- plastic housing
- standard plastic
- surrounded
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- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
- H01L2224/29191—The principal constituent being an elastomer, e.g. silicones, isoprene, neoprene
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Standard-Kunststoffgehäuse mit zumindest einem darin verkapselten Halbleiterchip, der auf seiner aktiven Oberfläche integrierte Schaltkreise aufweist, wobei jeder Chip auf einer metallischen Unterlage, die als sogenannte Insel bezeichnet wird, aufgebracht ist und die Chips von einem Rahmen aus den die Gehäuseanschlüsse bildenden Leiterbahnen umgeben sind, der bis zum Umhüllen von Chip, Insel und des inneren Teils der Leiterbahnen mit Kunststoff über dünne Stege mit der Insel verbunden ist, wobei die Insel kleiner als die Fläche des Chips ist und der Chipüberstand an den einzelnen Seiten jeweils mindestens 300 μm beträgt, dadurch gekennzeichnet, daß die Insel (5) unter dem Chip (6) an ihren Schmalseiten von einem sich durch Herausdrücken von elastischem Material beim Aufbringen des Chips (6) auf die Insel (5) bildenden Wulst (8) aus dem elastischem Material umgeben ist.Standard plastic housing with at least one semiconductor chip encapsulated therein, on its active surface has integrated circuits, each chip on a metallic Pad, which is referred to as a so-called island applied is and the chips from a frame out of the housing connections forming Circuits are surrounded, which until the wrapping of chip, island and the inner part of the interconnects is connected to plastic via thin webs with the island, where the island is smaller than the area of the chip and the chip overhang each of the individual sides is at least 300 μm, characterized that the Island (5) under the chip (6) on its narrow sides of a itself by pushing out of elastic material when applying the chip (6) to the island (5) forming bead (8) is surrounded by the elastic material.
Description
Die Erfindung bezieht sich auf ein Standard-Kunststoffgehäuse mit zumindest einem darin verkapselten Halbleiterchip, der auf den aktiven Oberflächen integrierte Schaltkreise aufweist, wobei jeder Chip auf eine metallische Unterlage, die als sogenannte Insel bezeichnet wird, aufgebracht ist und von einem Rahmen aus den die Gehäuseanschlüsse bildenden Leiterbahnen umgeben ist, der bis zum Umhüllen von Chip, Insel und des inneren Teils der Leiterbahnen mit Kunststoff über dünne Stege mit der Insel verbunden ist. Die Fläche der Insel ist kleiner als die Fläche des Halbleiterchips und der Chipüberstand beträgt jeweils mindestens 300 μm.The The invention relates to a standard plastic housing at least one semiconductor chip encapsulated therein, which integrated on the active surfaces Having circuits, each chip being mounted on a metallic pad, which is referred to as so-called island, is applied and of a frame from the housing connections forming Circuit traces is surrounded, which until the wrapping of chip, island and the inner part of the interconnects with plastic via thin webs connected to the island is. The area the island is smaller than the area of the semiconductor chip and the chip overhang is each at least 300 microns.
IC-Bauelemente bestehen üblicherweise aus einem Gehäuse, in dem der eigentliche Halbleiterchip verkapselt ist. Zur Montage derartiger Bauelemente wird häufig der Chip zunächst auf einer metallischen Unterlage (sog. Leadframe-Insel) angeordnet, die innerhalb eines äußeren Anschlußrahmens mit Anschlußbahnen gehaltert ist und vor der Verkapselung in Preßmasse kontaktiert wird.IC devices usually exist from a housing, in which the actual semiconductor chip is encapsulated. For assembly Such components become common the chip first arranged on a metallic base (so-called leadframe island), which within an outer lead frame with sidings is held and contacted before encapsulation in molding compound.
Die Integration von immer mehr Funktionen oder Speicherzellen auf einem Halbleiterchip führt nicht nur zu kleineren Strukturen auf der Chipoberfläche, sondern auch zu größeren Chips. Letztere müssen in die international genormten Standardgehäuse eingebaut werden.The Integration of more and more functions or memory cells on one Semiconductor chip does not lead only to smaller structures on the chip surface, but also to larger chips. The latter must be installed in the internationally standardized standard housing.
Beispielsweise sind bei einem 4 Mega-DRAM im genormten S0J20/26-Gehäuse die Gehäusemaße 17.1 mm × 8.89 mm (350 mil). In derartige Gehäuse wird bisher der eigentliche Chip von der Standardgröße 14.05 mm × 6.50 mm auf einer metallischen Unterlage von 14.60 mm × 6.80 mm aufgebracht. Dabei verbleibt zur Verankerung der seitlichen Anschlüsse etwa 1 mm.For example are in a 4 Mega DRAM in the standard S0J20 / 26 package the housing dimensions 17.1 mm × 8.89 mm (350 mils). In such housing So far, the actual chip of the standard size 14.05 mm × 6.50 mm on a metallic base of 14.60 mm × 6.80 mm applied. It remains for anchoring the lateral connections approximately 1 mm.
Im Zuge der Miniaturisierung wird für den gleichen Zweck die Verwendung eines 300 mil-Gehäuses, das 7,62 mm breit ist, angestrebt. Für ein derartiges Gehäuse würden zur Verankerung der seitlichen Anschlüsse beim 4 Mega-DRAM nur noch etwa 0,5 mm verbleiben. Jeder weitere zehntel Millimeter würde aber die Zuverlässigkeit des Bauteiles deutlich verbessern.in the The miniaturization process is for the same purpose using a 300 mil case, the 7.62 mm wide, sought after. For such a housing would to anchor the lateral connections of the 4 Mega DRAM only about 0.5 mm remain. Every other tenth of a millimeter would the reliability significantly improve the component.
Eine Möglichkeit zum Platzgewinn ist die Verkleinerung der metallischen Unterlage für den Halbleiterchip, was unter anderem in Proc. of the El. Comp. Conf. 1988, S. 552 bis 557 vorgeschlagen wird. Es ist allerdings bekannt, daß ein kleinerer Inselüberstand über den Halbleiterchip zu erhöhten mechanischen Spannungen im Bereich der unteren Chipkante und am Inselrand führt. Dadurch können bei dem fertigen Bauelement nach Verpressen des Chips in Pressmasse an den Stellen der erhöhten mechanischen Spannungen Risse in der Pressmasse entstehen. Bisher wurde daher ein Inselüberstand von 50 μm als untere Grenze angesehen.A possibility To gain space is the reduction of the metallic surface for the semiconductor chip, what among others in Proc. of the El. Comp. Conf. 1988, p. 552 bis 557 is proposed. However, it is known that a smaller Island supernatant over the Semiconductor chip to increased mechanical Stresses in the area of the lower chip edge and on the island edge leads. Thereby can at the finished device after pressing the chip in molding compound in the places of increased mechanical Tensions Cracks in the molding compound arise. So far, therefore an island overhang of 50 μm as lower limit.
Ein
Standard-Kunststoffgehäuse
mit darin verkapselten Halbleiterchips ist aus der JP 64-80055 A
bekannt. Dabei ist jeder Chip auf einer metallischen Unterlage aufgebracht,
die als sogenannte Insel bezeichnet wird. Die Chips sind von einem
Rahmen aus den die Gehäuseanschlüsse bildenden
Leiterbahnen umgeben, der bis zum Umhüllen von Chip, Insel und des
inneren Teils der Leiterbahnen mit Kunststoff über dünne Stege mit der Insel verbunden
ist. Die Insel ist dabei kleiner als die Fläche des Chips. Ein ähnliches
Kunststoffgehäuse
mit darin verkapselten Halbleiterchips, bei dem die Insel deutlich
kleiner ist als die Fläche
des Chips, ist weiterhin aus der JP 1-187841 A bekannt. Aus Hacke,
H.-J.: Montage Integrierter Schaltungen, Springer-Verlag 1987, Seiten 35–42, ist
eine Methode bekannt, beim Befestigen von Chips auf einem Substrat
mittels eines Klebers durch die Wahl eines elastischen Materials
und einer dicken Klebstoffschicht Spannungen abzubauen. Ein Standard-Kunststoffgehäuse, bei
dem unter der Insel eine Kunststofffolie angeordnet ist, die an
allen Sei ten über
die Insel hervorsteht, ist aus der
Aufgabe der Erfindung ist es daher, ein Standard-Kunststoffgehäuse mit Halbleiterchips der eingangs genannten Art anzugeben, bei dem die Platzverhältnisse innerhalb des Gehäuses verbessert werden, ohne daß hohe mechanische Spannungen in der Pressmasse auftreten.task The invention is therefore a standard plastic housing with Specify semiconductor chips of the type mentioned, in which the space inside the case be improved without high mechanical stresses occur in the molding compound.
Die Aufgabe ist erfindungsgemäß dadurch gelöst, daß die Insel kleiner ist als die Fläche des Chips und der Chipüberstand an den einzelnen Seiten jeweils mindestens 300 μm beträgt und dass die Insel unter dem Chip an ihren Schmalseiten von einem sich durch Herausdrücken des Materials beim Aufbringen des Chips auf die Insel bildenden Wulst aus elastischem Material umgeben ist.The Task is inventively achieved in that the island smaller than the area of the chip and the chip overhang at the individual sides in each case at least 300 microns is and that the island under the chip on its narrow sides of a by pressing out the Material during application of the chip on the island forming bead surrounded by elastic material.
Im Rahmen der Erfindung konnte durch Finite-Elemente-Berechnungen gezeigt werden, daß die mechanischen Spannungen im Bereich der unteren Chipkante und am Inselrand überraschenderweise dann geringer werden, wenn die Insel deutlich kleiner ist als die Chipfläche. Damit ist das eingangs aufgezeigte Problem umgangen.in the Frame of the invention could be demonstrated by finite element calculations be that mechanical Tensions in the area of the lower edge of the chip and at the edge of the island surprisingly then become smaller if the island is significantly smaller than the chip area. In order to the problem indicated at the beginning has been bypassed.
In vorteilhafter Weiterbildung der Erfindung ist die Insel unter dem Halbleiterchip an ihren Schmalseiten von einem Wulst aus Klebstoff umgeben. Vorzugsweise ist der Klebstoff ein gefüllter Epoxidharz- oder ein Silikonkleber. Fertigungstechnisch erweist es sich auch als vorteilhaft, wenn unter die Insel eine Kunststoffolie geklebt ist, die an allen Seiten über die Insel hervorsteht, damit herausquellender Kleber nicht die Fertigungseinrichtung verschmutzt.In an advantageous embodiment of the invention, the island is surrounded by a bead of adhesive under the semiconductor chip on its narrow sides. Preferably, the adhesive is a filled Epo xidharz- or a silicone adhesive. Manufacturing technology, it also proves to be advantageous if under the island a plastic film is glued, which protrudes on all sides of the island, so that swelling adhesive does not pollute the manufacturing facility.
Die Stege, die die Insel in der Mitte des sogenannten Anschlußrahmens (Leadframe) halten, können vorteilhafterweise nach unten gekröpft ausgebildet sein. Dies gewährleistet, daß in der Preßmasse keine Risse im Bereich der Stege entstehen. Damit ergibt sich ein Standard-Kunststoffgehäuse mit optimaler Platzausnutzung in der Preßmasse.The Footbridges that connect the island in the middle of the so-called lead frame (Lead frame) can hold be formed advantageously bent down. This guaranteed that in the molding compound none Cracks in the area of the webs arise. This results in a standard plastic housing with optimal space utilization in the molding compound.
Weitere Einzelheiten und Vorteile der Erfindung ergeben sich aus der nachfolgenden Figurenbeschreibung von Ausführungsbeispielen anhand der Zeichnung. Es zeigenFurther Details and advantages of the invention will become apparent from the following Description of the figures of exemplary embodiments based on the drawing. Show it
In
der
In
Anhand
Der
Chip
Speziell
aus
Der
so vorbereitete Aufbau wird in Preßmasse aus Kunststoff eingehüllt. Dazu
wird die gesamte Insel
Das
somit montierte IC-Bauelement zeichnet sich durch optimale Platzausnutzung
innerhalb des Gehäuses
Claims (5)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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DE4041346A DE4041346B4 (en) | 1990-12-21 | 1990-12-21 | Standard plastic housing with encapsulated semiconductor chips |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE4041346A DE4041346B4 (en) | 1990-12-21 | 1990-12-21 | Standard plastic housing with encapsulated semiconductor chips |
Publications (2)
Publication Number | Publication Date |
---|---|
DE4041346A1 DE4041346A1 (en) | 1992-06-25 |
DE4041346B4 true DE4041346B4 (en) | 2005-10-06 |
Family
ID=6421139
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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DE4041346A Expired - Lifetime DE4041346B4 (en) | 1990-12-21 | 1990-12-21 | Standard plastic housing with encapsulated semiconductor chips |
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Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4206437A1 (en) * | 1992-02-29 | 1993-09-16 | Telefunken Microelectron | Semiconductor mounting eg for GaP LED - supports chip on raised surface of carrier with intermediate metallised silicon chip of similar thermal expansion coefficient |
DE4428320A1 (en) * | 1994-08-10 | 1996-02-15 | Duerrwaechter E Dr Doduco | Plastic housing with a vibration-damping bearing of a bondable element |
DE19526010B4 (en) * | 1995-07-17 | 2005-10-13 | Infineon Technologies Ag | Electronic component |
EP0954879A1 (en) | 1997-01-22 | 1999-11-10 | Siemens Aktiengesellschaft | Electronic component |
DE112005003614B4 (en) | 2005-07-28 | 2014-08-21 | Infineon Technologies Ag | Semiconductor module for a switching power supply and method for its assembly |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0209265A1 (en) * | 1985-06-25 | 1987-01-21 | Toray Silicone Co., Ltd. | Lead frame for semiconductor devices |
DE3635375C2 (en) * | 1986-10-17 | 1988-07-21 | W.C. Heraeus Gmbh, 6450 Hanau, De | |
JPS6480055A (en) * | 1987-09-21 | 1989-03-24 | Nec Corp | Resin sealed semiconductor device |
JPH01187841A (en) * | 1988-01-22 | 1989-07-27 | Hitachi Ltd | Semiconductor device |
JPH01204459A (en) * | 1988-02-10 | 1989-08-17 | Hitachi Ltd | Lead frame for semiconductor device |
JPH0225061A (en) * | 1988-07-13 | 1990-01-26 | Hitachi Ltd | Semiconductor device and lead frame used for manufacture thereof |
-
1990
- 1990-12-21 DE DE4041346A patent/DE4041346B4/en not_active Expired - Lifetime
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0209265A1 (en) * | 1985-06-25 | 1987-01-21 | Toray Silicone Co., Ltd. | Lead frame for semiconductor devices |
DE3635375C2 (en) * | 1986-10-17 | 1988-07-21 | W.C. Heraeus Gmbh, 6450 Hanau, De | |
JPS6480055A (en) * | 1987-09-21 | 1989-03-24 | Nec Corp | Resin sealed semiconductor device |
JPH01187841A (en) * | 1988-01-22 | 1989-07-27 | Hitachi Ltd | Semiconductor device |
JPH01204459A (en) * | 1988-02-10 | 1989-08-17 | Hitachi Ltd | Lead frame for semiconductor device |
JPH0225061A (en) * | 1988-07-13 | 1990-01-26 | Hitachi Ltd | Semiconductor device and lead frame used for manufacture thereof |
Non-Patent Citations (10)
Title |
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1-204459 A. E-845, Nov.14, 1989, Vol.13/No.507 |
1-80055 A. E-785, July 11, 1989, Vol.13/No.301 |
HACKE, H.-J.: Montage Integrierter Schaltungen, Springer-Verlag, Berlin 1987, S. 35-42 * |
JP 2025061 A. In: Patent Abstracts of Japan * |
JP 2-25061 A. In: Patent Abstracts of Japan |
Kleben von Mikroelektronik - Bauteilen mit Epoxyharzen. In: ELEKTRONIK, H.7, 1973, S.264-266 * |
Patents Abstracts of Japan Vol.13/No.301, E-785, July 11, 1989 & JP 1080055 A * |
Patents Abstracts of Japan Vol.13/No.476, E-837, Oct.27, 1989 & JP 1187841 A * |
Patents Abstracts of Japan Vol.13/No.507, E-845, Nov.14, 1989 & JP 1204459 A * |
Patents Abstracts of Japan: 1-187841 A. E-837, Oct.27, 1989, Vol.13/No.476 |
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DE4041346A1 (en) | 1992-06-25 |
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