Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/40—Bus structure
  • G06F13/4004—Coupling between buses
  • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Definitions

• the present invention generally relates to microprocessors and more particularly to a microprocessor using a non-volatile memory containing executable instructions of a program and a volatile memory for storing data used by the program.
• microprocessors can present two architectures for connection with memories.
• the microprocessor In the first architecture, called Von Neumann, the microprocessor is connected to all memories by a single address and data bus. Consequently, the microprocessor can only access a single datum or a single instruction code at a given instant.
• a second architecture known as Harvard, has been developed, in which the microprocessor can simultaneously access an instruction code and a data item, which for this purpose are stored in different memories.
• This architecture requires providing a microprocessor with two different buses, one being dedicated to accessing the program and connected to the memory containing the program, and the other being dedicated to accessing the data and connected to the memory containing the data. In this way, the microprocessor can, during the same clock cycle, read an instruction in the program memory and perform an operation of reading or writing data in the data memory.
• a Harvard architecture microprocessor takes fewer clock cycles to execute a program than a Von Neumann architecture microprocessor.
• the Harvard architecture has some drawbacks, in particular in terms of flexibility in the use of memories connected to the microprocessor. Indeed, this architecture requires storing in respective predefined and distinct memory areas, the program instructions and the non-modifiable data, including the operating parameters, or which must be stored in a non-volatile manner. This architecture cannot be used in the case of a microprocessor connected to a single non-volatile memory and a single volatile memory. In addition, it does not allow program instructions to be stored in volatile memory, for example for testing purposes. Furthermore, it does not authorize either that a program can modify itself by writing in a memory, as data, executable instruction codes.
• the present invention aims to eliminate these drawbacks by proposing an architecture with two buses, without however affecting the linearity of the space addressable by the microprocessor, which is obtained with a Von Neumann architecture.
• a microprocessor connected to a first memory space via a first bus, and to a second memory space via a second bus, and comprising a processing unit provided an access bus to executable program instructions and a data access bus, characterized in that it comprises a bus interface unit connected on one side to the access bus program instructions and to the data access bus, and the other to the first and to the second bus, the interface unit comprising first switching means for connecting the access bus to the program either to the first bus, either to the second bus, according to a request for access to the program, sent by the processing unit, and second switching means, to connect the data access bus either to the first bus or to the second bus , based on a data access request issued by the processing unit ent.
• the first switching means are independent of the second switching means, the interface unit further comprising access control means designed to manage access conflicts which occur when the processing unit simultaneously transmits an access request to data and a request for access to a program instruction, which relate to the same memory space.
• the access control means are designed to give priority to a request for access to a datum, when there is a conflict of access to the memory spaces.
• the access control means are designed to authorize simultaneous access to a program instruction in one of the two memory spaces and a data item in the other of the two memory spaces.
• the access control means comprise means for preventing access by the processing unit to a program instruction following the transmission by the processing unit of simultaneous access requests to an instruction and a data in the same memory space.
• the access control means comprise means for authorizing the access of the processing unit to a memory space only for a duration where the memory space authorizes its access.
• the microprocessor is connected to a program instruction address decoder and a data address decoder, which are designed to generate selection signals according to the addresses appearing on the buses. access to the program and to the data, and according to the access requests sent by the processing unit, these selection signals being applied to the input of the interface unit and comprising two selection signals indicating a request d access to a program instruction in the first and second respectively memory space, and two selection signals indicating a request to access data in the first and second memory space respectively.
• the microprocessor comprises control means for controlling the first switching means so as to connect the program access bus to the first or to the second bus, when the selection signals indicate a request for access to a instruction of program, in the respective memory space, and no simultaneous request to a datum therein.
• the microprocessor comprises control means for controlling the second switching means so as to connect the data access bus, to the first bus or to the second bus, when the selection signals indicate a request for access to a data item. , in the corresponding memory space.
• the first memory space comprises a non-volatile memory
• the second memory space comprises a volatile memory
• FIG. 1 schematically shows the architecture of a microprocessor according to the invention, connected to a program memory and a data memory;
• FIG. 1 shows the circuit of a component of the architecture shown in Figure 1;
• FIGS. 5a to 5d represent circuits of alternative embodiments of a component of the architecture shown in FIG. 1;
• FIG. 6 represents the circuit of a component of the architecture shown in FIG. 1;
• FIG. 7 illustrates in the form of timing diagrams different signals used in the architecture represented in FIG. 1.
• the microprocessor 1 shown in Figure 1 has a Harvard architecture. To this end, it conventionally comprises a processing unit 2 comprising a program access interface and a data access interface.
• the program access interface includes:
• the data access interface includes:
• a read or write RW access mode output indicating whether the address provided by port A is to be read or write
• an NDR data request output which is in the active state during a clock cycle when a read or write operation must be performed
• the microprocessor 1 is connected on one side to a program memory 4 and an address decoder 6 of program memory, and on the other side, to a data memory 5 and a decoder of data memory address 7.
• the program memory 4 is non-volatile, for example of the ROM, E 2 PROM or Flash type, while the data memory 5 is of the volatile type, for example of the RAM type.
• the PC port and the NPR output of the processing unit 2 are connected to the address decoder 6, while the address port A and the NDR output of the processing unit 2 are connected to the address decoder 7 .
• the microprocessor 1 comprises an interface unit 3 connected between the processing unit 2 on the one hand, and on the other hand the memories 4, 5, this interface unit being designed to ensure access linear to the memory space addressable by the microprocessor 1.
• the address decoders 6, 7 are designed to supply different signals for selecting the access mode of the program and data memories 4, 5.
• the program memory address decoder 6 delivers an NPPSEL selection signal indicating a request for access to an instruction or operand in the program memory 4, and an NPDSEL selection signal indicating a request for access to an instruction or operand in the data memory 5.
• the address decoder 7 of the data memory 5 delivers a signal NDDSEL selection indicating an access to a data in the data memory 5, and an NDPSEL selection signal indicating an access to a data in the program memory 4.
• the selection signals are generated by the address decoders 6, 7 only according to that the address appearing on the bus A or PC corresponds to an address of the memory 4 or of the memory 5.
• the signals NPR and NDR allow respectively to activate the decoders 6, 7, when they are at active state. In FIG.
• the interface unit 3 comprises a program access control unit 12, connected to the NPA input of the processing unit 2, a data access control unit 13, connected at the input NDA, and a bus multiplexer 11 connected between the processing unit 2 and the memories 4, 5. Furthermore, the data output port DBO of the processing unit (2) is connected simultaneously, via respective DOP and DOD outputs of the interface unit 3, to the data input ports DI of the memories 4 and 5. More specifically, the bus multiplexer 11 is connected to the ports PC, A, DBI and INS, as well as at the RW output of the processing unit. It includes two identical connection interfaces for connecting respectively to the two memories 4, 5.
• Each of these interfaces includes an output port AP, AD intended to be connected to the input address port AD of the memory 4, 5, a data input port DIP, DID intended to be connected to the data output port DO of the memory 4, 5, an access mode output RWP, RWD connected to the corresponding input RW of the memory, and a component selection output NCSP, NCSD connected to the corresponding input CSN of the memory 4, 5.
• the four selection signals NPPSEL, NPDSEL, NDDSEL and NDPSEL are applied to the input of the multiplexer 11 and the access control unit 12 to the program, while only the signals NDDSEL and NDPSEL relating to the accesses to the memory of data 5 are applied at the input of the access control unit 13 to the data.
• the access control units 12, 13 also receive respectively the NPR and NDR signals from the processing unit 2. In the description which follows, all the signals mentioned above are for example active in the low state (logic level 0).
• the multiplexer 11 comprises a bus control unit 21 which receives as input the four selection signals NPPSEL, NPDSEL, NDDSEL and NDPSEL and outputs the component selection signals NCSP, NCSD, and two signals control CMD25, CMD26 respectively of two multiplexers 25, 26 with two inputs 0 and 1 and one output.
• These two multiplexers 25, 26 receive as input the addresses coming from the ports PC and A of the processing unit 2, and according to the value of their respective control signals CMD25, CMD26, apply to the output ports of address AP, AD of the bus multiplexer 11, the address coming either from the PC port, or from the A port.
• the NPDSEL and NDPSEL selection signals indicating data in the program memory or of an instruction in the data memory are applied as control signals respectively to two multiplexers 23, 24 to which the data read from the data are applied as input. memories 4, 5 and coming from the DIP and DID input ports of the multiplexer 11.
• the outputs of these multiplexers are respectively connected to the INS and DBO output ports of the bus multiplexer 11, so as to direct the input to these ports data either from program memory 4 or from data memory 5.
• NDPSEL 0
• the DIP port connected to the output port of data DO of the program memory is connected to the data output port DBO of the multiplexer 11.
• the port DID which is connected to the data output port DBO of the multiplexer 11.
• the DID port of the multiplexer 11 is connected to the instruction output port INS of the latter. Otherwise, it is the DIP port of the multiplexer 11 which is connected to the output port INS.
• the bus multiplexer 11 includes a signal demultiplexer 27 for directing the RW signal from the processing unit 2 either to the program memory 4 through the RWP output, or to the data memory 5 through of the RWD output, according to the selection signals NDPSEL and NDDSEL relating to the access to a data in the program memory or in the data memory.
• the bus control unit 21 comprises for example three AND logic gates 31, 32, 33.
• Gate 31 receives the input signals as input
• NCSD NPDSEL AND NDDSEL
• NCSP NPPSEL AND NDPSEL
• the third AND gate 33 comprises an inverted input to which is applied the NPDSEL selection signal and a direct input to which is applied • NDDSEL signal, the output of said gate supplying the control CMD26 signal of the multiplexer 26 shown in Figure 2
• FIG. 4 shows an exemplary embodiment of the signal multiplexer circuit 27.
• This circuit comprises two multiplexers 36 and 37, with two inputs 0, 1, whose input 0 receives the signal RW coming from the processing unit 2, and input 1 the selection signals NDPSEL and NDDSEL respectively.
• the control input of each multiplexer 36, 37 is also looped back to input 1.
• Figure 5a shows a first embodiment of the access control unit 12 to the program.
• the access control unit 12 comprises two AND logic gates 45, 46 whose inputs are reversed.
• the first gate 45 receives the NDDSEL and NPDSEL selection signals as an input
• the second gate 46 receives the NDPSEL and NPPSEL selection signals.
• the outputs of these two doors are connected to an OR gate 47, the output of which is connected to the control input and the input 1 of a multiplexer 48 to two inputs 0, 1, the output of this multiplexer providing the NPA signal. which is applied at the input of the processing unit 2, and the input 0 of the multiplexer receiving the NPR signal from the processing unit.
• the NPA signal is equal to 1 (access of the processing unit to the blocked program) when the following condition is fulfilled:
• FIG. 5b represents a second embodiment of the access control unit 12 which can be used when the program memory 4 has an output ACKN of acknowledgment signal NPMA of an access request. When high, this signal indicates that no access to the memory is in progress.
• this NPMA acknowledgment signal exists, it is applied at the input of the access control unit 12.
• the circuit shown in this figure corresponds to the circuit shown in Figure 5a, except that it includes a second multiplexer 49 with two inputs 0, 1, which is interposed between the input of the NPR signal and the input 0 of the multiplexer 48, the NPR signal being applied to the input 1 of this multiplexer 49 and the NPMA signal being applied to the entry 0 of it.
• the multiplexer 49 is controlled by the selection signal NPPSEL.
• the access control unit 12 outputs the signal NPMA if the selection signal NPPSEL is at 0 and the signal NPR in the case opposite .
• FIG. 5c represents a third embodiment of the access control unit 12 which can be used when only the data memory 5 has an output ACKN of acknowledgment signal NDMA. In this case, this acknowledgment signal is applied to the input of the access control unit 12.
• the circuit shown in this figure corresponds to the circuit shown in figure 5b, with the difference that the NDMA signal is applied to input 0 of the multiplexer 49 in place of the NPMA signal, and the multiplexer 49 is controlled by the selection signal NPDSEL at NPPSEL signal location.
• the access control unit 12 outputs the signal NDMA if the selection signal NPDSEL is at 0, and the signal NPR in the opposite case.
• FIG. 5d represents a fourth embodiment of the access control unit 12 which can be used when the two memories 4, 5 have an output ACKN of acknowledgment signal NDMA and NPMA, respectively.
• the two acknowledgment signals are applied to the input of the access control unit 12.
• the circuit shown in this figure corresponds to the circuit shown in Figure 5c, with the difference that it includes a third multiplexer 50 with two inputs 0, 1, interposed between input 1 of multiplexer 49 and the input of the NPR signal which is connected to input 1 of multiplexer 50 whose input 0 receives the NPMA signal, and the input of controls the NPPSEL signal.
• the access control unit 12 outputs the signal NPMA if the selection signal NPPSEL is at 0, the signal NDMA if the signal NPDSEL selection switch is 0, and the NPR signal otherwise.
• the control unit 13 applies to the input NDA of the processing unit 2, the signal NDR coming from the latter.
• Such a function can be carried out using a single multiplexer, the control input of which receives the NDDSEL signal, the input 0 of which receives the NPMA signal and the input 1 of which receives the NDR signal.
• the access control unit 13 can be produced as shown in FIG. 6.
• the control unit 13 comprises two multiplexers 61 and 62 with two inputs 0, 1.
• the multiplexer 61 receives the NPMA signal on its input 0, the NDR signal on its input 1 and the NDDSEL signal on its control input.
• the output of this multiplexer 61 is connected to the input 1 of the second multiplexer 62 whose input 0 receives the signal NDMA, the control input the signal NDPSEL and the output provides the signal NDA which is applied as input of the processing unit 2.
• FIG. 7 illustrates the function of the interface unit 3, using timing diagrams of the various signals mentioned above, in synchronism with the clock signal CK of the microprocessor 1. These signals are in the active state when they are at logic level 0.
• the phase 71 represented in this figure corresponds to an extended access to the data memory 4. Such an access occurs when the processing unit 2 delivers an NDR signal in the active state for 2 clock cycles, this is ie with a waiting cycle W.
• the NDDSEL signal which is generated by the address decoder 7 corresponds to the NDR signal
• the NDMA signal which is generated by the memory 5 is in the state active only during the second cycle when the NDR signal is active.
• the signal NDA is at the active state only during the second cycle where memory access 5 takes place.
• Phase 72 illustrates the case of a standard, simultaneous access to memories 4, 5, a data item being accessed in data memory 5 and an instruction or an operand being read out from program memory 4.
• the unit processing unit issues requests to access the two memories (NPR and NDR in the active state).
• the address decoders 6, 7 place the selection signals NPPSEL and NDDSEL in the active state.
• the bus controller 21 activates the memories 4, 5 using the signals NCSP and NCSD.
• the NDMA and NPMA signals then also pass to the active state, and the access control unit 12 applies the NPMA signal to the NPA input of the processing unit 2 which is then authorized to carry out the reading of an instruction or operand in the program memory 4.
• the access control unit 13 applies the signal NPMA to the input NDA of the processing unit 2 which is thus authorized to access data in program memory 4.
• This phase shows that the processing unit 2 can simultaneously access memories 4 and 5 during a single clock cycle, in order to read an instruction in program memory 4 and a data item in data memory 5.
• the processing unit 2 accesses the program memory 4 to access data. To this end, it places its NDR output in the active state. In response, and using the memory address to be accessed, the address decoder 7 places the selection signal NDPSEL in the active state. As a result, the bus controller 21 activates the memory 4 using the signal NCSP. The NPMA signal then also goes to the active state and the access control unit 12 applies the NDMA signal to the NPA input of the processing unit. 2 which is thus authorized to access data in the program memory 4.
• the processing unit 2 accesses the data memory 5 to read a program instruction or an operand. For this purpose, it places its NPR output in the active state. In response, and using the memory address to be accessed, the address decoder 6 places the selection signal NPDSEL in the active state. As a result, the bus controller 21 activates memory 5 using the signal NCSD. The NDMA signal then also goes to the active state and the access control unit 12 applies the NDMA signal to the NPA input of the processing unit 2 which is thus authorized to read an instruction in data memory 5.
• Phase 75 illustrates the opposite case of phase 72, where the processing unit simultaneously sends a request for access to a data item in the program memory 4 and request to read an instruction or operand in the data memory 5.
• the NPR and NDR signals therefore switch to the active state at the same time.
• the address decoders 6, 7 place the signals NDPSEL and NPDSEL in the active state.
• the bus controller 21 activates the memories 4, 5 using the signals NCSP and NCSD.
• the NDMA and NPMA signals then also pass to the active state and the access control unit 12 applies the NDMA signal to the NPA input of the processing unit 2 which is then authorized to read a instruction or operand in data memory 5.
• the access control unit 13 applies the NPMA signal to the NDA input of the processing unit 2 which is thus authorized to access data in the program memory 4.
• This phase shows that , in this case also, simultaneous access to the two memories 4 and 5 during a single clock cycle (NPA and NDA signals active at the same time), can be carried out without conflict, which was not the case with the prior architectures .
• the processing unit 2 seeks to access the program memory 4 to read both an instruction or operand, and a piece of data. The NPR and NDR signals therefore switch to the active state at the same time.
• the signals NDPSEL and NPPSEL also pass into the active state at the same time, as well as the signal NCSP coming from the bus controller 21, and therefore the signal NPMA coming from the program memory 4.
• the NDR signal returns to the inactive state, which returns the NDPSEL and NDA signals to the inactive state, the NDR signal being applied in this case to the NDA input. by the control unit 13.
• Phase 77 illustrates the case of two simultaneous accesses to the data memory 5 for reading an instruction, and accessing a data item.
• the signals NPR and NDR are placed in the active state at the same time by the processing unit 2.
• the signals NDDSEL and NPDSEL also pass into the active state at the same time, as well as the signal NCSD coming from the bus controller 21, and therefore the signal NDMA coming from the data memory 5.
• the signal NDR returns to the inactive state, which brings the signals NDPSEL and NDA back to the inactive state.
• the invention therefore makes it possible to obtain undifferentiated access to the program and to the data, the latter being distributed in any manner in two memory spaces accessible simultaneously by the 'processing unit by means of two respective buses.

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