EP1360718A2 - Integrated circuit arrangement consisting of a flat substrate - Google Patents

Integrated circuit arrangement consisting of a flat substrate

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Publication number
EP1360718A2
EP1360718A2 EP02703497A EP02703497A EP1360718A2 EP 1360718 A2 EP1360718 A2 EP 1360718A2 EP 02703497 A EP02703497 A EP 02703497A EP 02703497 A EP02703497 A EP 02703497A EP 1360718 A2 EP1360718 A2 EP 1360718A2
Authority
EP
European Patent Office
Prior art keywords
substrate
integrated circuit
circuit arrangement
carrier
flat substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02703497A
Other languages
German (de)
French (fr)
Inventor
Marcus Janke
Peter Laackmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1360718A2 publication Critical patent/EP1360718A2/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • Integrated circuit arrangement made of a flat substrate
  • the invention relates to an integrated circuit arrangement made of a flat substrate.
  • the substrate is brought from the flat shape into a non-planar shape by the carrier at least in one direction of propagation, it cannot be machined by means of grinding processes with reasonable effort such that the surface can be removed in layers in a completely analyzable manner.
  • the desired deformation can also be generated by mechanical stresses that arise in the substrate itself, for example by changing the chemical or physical structure of the substrate. For example, implantation processes, diffusion processes or thermal processes can be used for this. With suitable technology, soldering and connection methods, for example between a plurality of substrates which are arranged one above the other, can also be used to specifically generate mechanical stresses in the substrate.
  • a deformed substrate usually retains its deformed shape after some time.
  • partial areas can also be removed at least on one surface.
  • FIG. 1 shows the basic structure of an integrated circuit arrangement on a semiconductor chip
  • FIG. 2 shows a first exemplary embodiment of an integrated circuit arrangement according to the invention on a semiconductor chip
  • FIG. 3 shows the surface in a modification of the first exemplary embodiment
  • FIG. 4 shows a second exemplary embodiment according to the invention
  • FIG. 5 shows a modification of the second exemplary embodiment
  • FIG. 6 shows a second modification of the second exemplary embodiment
  • Figure 7 shows a possible surface design.
  • FIG. 1 the basic structure of an integrated circuit arrangement is shown.
  • An integrated circuit is built up in a known manner on a substrate 1 in several layers, which are shown here as layers 2 and 3 as a minimal solution.
  • layers 2 and 3 are shown here as layers 2 and 3 as a minimal solution.
  • Well over two shifts are currently common.
  • At least the invention can only be meaningfully applied from two layers, since only then is there a layer that can be removed in order to analyze the layer underneath.
  • FIG. 2 it is shown that on the side used for layers 2 and 3, a material 4 is applied, which during
  • Hardening leads to a tension of the substrate 1, so that there is a surface that is curved at least in one direction forms.
  • Commercial epoxy-based adhesives can be used for this.
  • curvature in two directions is also possible.
  • deformations of at least 1 ⁇ m can easily be achieved over the entire chip area. It should be noted that the chip could possibly be thinned more in order to achieve greater deformation.
  • a torsion-like deformation, as shown in FIG. 7, should also be considered. For example, as indicated by the arrows shown, it is possible to twist opposite sides in opposite directions.
  • parts A can be removed from the substrate surface, as indicated by dashed lines in FIG , This is done either by obliquely etching or grinding edge regions of the substrate as shown on the left side of FIG. 2 or by etching out or grinding individual parts A as shown on the right side of FIG. In this way it is ensured that it is not possible, or at least very expensive, to bring the substrate 1 back into a flat shape after deformation.
  • the integrated circuit arrangement is constructed such that the substrate is applied to a carrier 5, the carrier 5 forming the substrate.
  • Recesses could also be provided here, which are not shown in connection with FIG. 4.
  • the carrier 5 is not only deformed on one surface as shown in FIG. 4, but is also made overall from a flat shape to a curved or twisted shape.
  • elevations 6 are formed on the surface of the carrier, which, when brought together with the substrate 1, deforms the substrate 1 together with its applied layers. This can take place in particular in that a material 4 similar to that in the exemplary embodiment shown in FIG. 2 is introduced into the spaces between the elevations, the substrate and the carrier, which leads to the bracing of the substrate when drying.
  • the basic idea of the invention resides in permanently deforming the substrate carrying an integrated circuit in such a way that the layers applied to the substrate cannot be selectively removed by means of a grinding process.

Landscapes

  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Structure Of Printed Boards (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention relates to an integrated circuit arrangement whose substrate has an integrated circuit that is configured on several layers, wherein at least one surface of the substrate does not have a planar configuration in the direction of propagation.

Description

Beschreibungdescription
Integrierte Schaltungsanordnung aus einem flächigen SubstratIntegrated circuit arrangement made of a flat substrate
Die Erfindung betrifft eine integrierte Schaltungsanordnung aus einem flächigen Substrat gemäß Patentanspruch 1.The invention relates to an integrated circuit arrangement made of a flat substrate.
Die Entwicklungskosten von integrierten Schaltungen, die sich auf einem Halbleiterchip befinden, sind heutzutage so hoch, daß es für den Wettbewerber zunehmend interessant wird diese zu analysieren, um sie nachzubauen. Außerdem beruhen einige der heutigen Angriffe auf Halbleiterchips, die deren Sicherheit gefährden können, auf der detaillierten Kenntnis des internen Aufbaus dieser Bausteine. Daher wird auch aus Sicher- heitsgründen versucht zu verhindern, daß ein Angreifer Details über den Aufbau eines solchen Halbleiterchips erfährt. Weiterhin sind inzwischen Anwendungen üblich, bei denen die integrierten Schaltungen fest abgespeicherte Daten aufweisen. Um derartige Bausteine vor der Analyse zu schützen, sind bis- her eine Vielzahl von Verfahren bekannt. Beispielsweise ist es bekannt, die Oberfläche integrierter Schaltungen so abzudecken, daß sie auf optischem Wege nicht ohne weiteres analysierbar sind. In der EP 0981162 AI ist ein solcher Schutz beschrieben.The development costs of integrated circuits that are located on a semiconductor chip are so high today that it is becoming increasingly interesting for competitors to analyze them in order to reproduce them. In addition, some of today's attacks on semiconductor chips that can compromise their security are based on detailed knowledge of the internal structure of these devices. For security reasons, therefore, attempts are made to prevent an attacker from knowing details about the structure of such a semiconductor chip. Furthermore, applications are now common in which the integrated circuits have permanently stored data. A large number of methods have hitherto been known to protect such building blocks from analysis. For example, it is known to cover the surface of integrated circuits in such a way that they cannot be easily analyzed optically. Such protection is described in EP 0981162 AI.
Solche Schutzmaßnahmen lassen sich jedoch dadurch umgehen, daß die Abdeckung durch vorsichtiges Abschleifen freigelegt wird, selbst wenn der Oberflächenschutz ätzfest ist. Durch schichtweises Abtragen und Fotografieren der jeweils freige- legten Schicht läßt sich bei derartigen Anordnungen der Aufbau der integrierten Schaltung nachträglich analysieren.However, such protective measures can be avoided by exposing the cover by careful grinding, even if the surface protection is caustic. With such arrangements, the structure of the integrated circuit can be subsequently analyzed by layer-by-layer removal and photographing of the respectively exposed layer.
Aus der US 5,955,766 ist es bekannt auf einem kugelförmigen Substrat eine integrierte Schaltung auszubilden. Dieses Ge- bilde ist jedoch nicht mit üblichen Technologien herstell bar. Der Erfindung liegt somit die Aufgabe zugrunde, eine integrierte Schaltungsanordnung vorzusehen, die mit geringem Aufwand eine hohe Analysiersicherheit bietet .From US 5,955,766 it is known to form an integrated circuit on a spherical substrate. However, this structure cannot be produced using conventional technologies. The invention is therefore based on the object of providing an integrated circuit arrangement which offers high analysis reliability with little effort.
Diese Aufgabe wird erfindungsgemäß mit den im Patentanspruch 1 angegebenen Maßnahmen gelöst. Dadurch, daß das Substrat zumindest in einer Ausbreitungsrichtung durch den Träger von der ebenen Form in eine nicht planare gebracht ist, läßt es sich mit vertretbarem Aufwand nicht mittels Schleifverfahren derart bearbeiten, daß die Oberfläche schichtweise vollständig analysierbar abgetragen werden kann.This object is achieved with the measures specified in claim 1. Because the substrate is brought from the flat shape into a non-planar shape by the carrier at least in one direction of propagation, it cannot be machined by means of grinding processes with reasonable effort such that the surface can be removed in layers in a completely analyzable manner.
Weitere vorteilhafte Ausgestaltungen der Erfindung sind in den untergeordneten Ansprüche angegeben. Durch die nicht vor- handene Planarität in einer zweiten Richtung, wird die zuvor angegebene Sicherheit erhöht. Durch das Auftragen eines Materials, zum Beispiel eines Klebstoffs oder einer aushärtbaren Keramik, welches eine hohe mechanische Spannung erzeugt, erfolgt die Verformung des Substrates .Further advantageous embodiments of the invention are specified in the subordinate claims. Due to the lack of planarity in a second direction, the previously specified security is increased. The substrate is deformed by applying a material, for example an adhesive or a hardenable ceramic, which generates a high mechanical tension.
Die gewünschte Verformung kann auch durch mechanische Spannungen erzeugt werden, die in dem Substrat selbst entstehen, beispielsweise durch Veränderung des chemischen oder physikalischen Gefüges des Substrats. Hierfür sind beispielsweise Implantationsverfahren, Diffusionsverfahren oder thermische Verfahren nutzbar. Löt- und Verbindungsverfahren, etwa zwischen mehreren Substraten, die übereinander angeordnet sind, können ebenfalls bei geeigneter Technologie dazu verwendet werden, gezielt mechanische Spannungen im Substrat zu erzeu- gen.The desired deformation can also be generated by mechanical stresses that arise in the substrate itself, for example by changing the chemical or physical structure of the substrate. For example, implantation processes, diffusion processes or thermal processes can be used for this. With suitable technology, soldering and connection methods, for example between a plurality of substrates which are arranged one above the other, can also be used to specifically generate mechanical stresses in the substrate.
Ein verformtes Substrat behält in der Regel nach einiger Zeit seine verformte Gestalt bei. Um zu verhindern, daß durch Ausüben eines Druckes das Substrat wieder in eine ebene, planare Form gebracht wird, können auch zumindest auf einer Oberfläche Teilbereiche entfernt sein. Durch das Vorsehen von Erhöhungen auf dem Träger läßt sich mit einfachen Mitteln eine sehr aufwendige nicht planare Oberflächenform der integrierten Schaltungsanordnung erzielen.A deformed substrate usually retains its deformed shape after some time. In order to prevent the substrate from being brought back into a flat, planar shape by exerting a pressure, partial areas can also be removed at least on one surface. By providing elevations on the carrier, a very complex, non-planar surface shape of the integrated circuit arrangement can be achieved with simple means.
Nachfolgend wird die Erfindung unter Bezugnahme auf die Zeichnung erläutert .The invention is explained below with reference to the drawing.
Es zeigen:Show it:
Figur 1 den grundsätzlichen Aufbau einer integrierten Schal- tungsanordnung auf einem Halbleiter-Chip,FIG. 1 shows the basic structure of an integrated circuit arrangement on a semiconductor chip,
Figur 2 ein erstes Ausführungsbeispiel einer erfindungsgemäßen integrierten Schaltungsanordnung auf einem Halbleiter- Chip,FIG. 2 shows a first exemplary embodiment of an integrated circuit arrangement according to the invention on a semiconductor chip,
Figur 3 die Oberfläche bei einer Abwandlung des ersten Aus- führungsbeispiels ,FIG. 3 shows the surface in a modification of the first exemplary embodiment,
Figur 4 ein zweites erfindungsgemäßes Ausführungsbeispiel, Figur 5 eine Abwandlung des zweites Ausführungsbeispiels, Figur 6 eine zweite Abwandlung des zweiten Ausfuhrungsbei- spiels und4 shows a second exemplary embodiment according to the invention, FIG. 5 shows a modification of the second exemplary embodiment, FIG. 6 shows a second modification of the second exemplary embodiment and
Figur 7 eine mögliche Oberflächengestaltung.Figure 7 shows a possible surface design.
In Figur 1 ist der grundsätzliche Aufbau einer integrierten Schaltungsanordnung dargestellt. Auf einem Substrat 1 sind in mehreren Schichten, die hier als die Schichten 2 und 3 als Minimallösung dargestellt sind, eine integrierte Schaltung in bekannter Weise aufgebaut. Üblich sind derzeit deutlich mehr als zwei Schichten. Minimal ist die Erfindung erst ab zwei Schichten sinnvoll anwendbar, da nur dann eine Schicht vorhanden ist, die abgetragen werden kann, um die darunter liegende Schicht zu analysieren.In Figure 1, the basic structure of an integrated circuit arrangement is shown. An integrated circuit is built up in a known manner on a substrate 1 in several layers, which are shown here as layers 2 and 3 as a minimal solution. Well over two shifts are currently common. At least the invention can only be meaningfully applied from two layers, since only then is there a layer that can be removed in order to analyze the layer underneath.
In Figur 2 ist dargestellt, daß auf der den Schichten 2 und 3 angewandten Seite ein Material_4 aufgebracht ist, das beimIn FIG. 2 it is shown that on the side used for layers 2 and 3, a material 4 is applied, which during
Aushärten zu einer Verspannung des Substrates 1 führt, so daß sich eine zumindest in einer Richtung gekrümmte Oberfläche bildet. Hierzu sind handelsübliche Klebstoffe auf Epoxydharzbasis einsetzbar.Hardening leads to a tension of the substrate 1, so that there is a surface that is curved at least in one direction forms. Commercial epoxy-based adhesives can be used for this.
Wird diese Oberfläche mit einem SchleifVorgang beispielsweise auf Höhe der gestrichelten Linie S abgetragen, so ist von der darunter liegenden Schicht nur ein geringer Ausschnitt zu erkennen. Soll auch der Rest der Schicht 3 abgetragen werden, so würde gleichzeitig ein großer Teil der Schicht 2 ebenfalls mit abgetragen werden.If this surface is removed with a grinding process, for example at the level of the dashed line S, only a small section of the layer underneath can be seen. If the rest of layer 3 were also to be removed, a large part of layer 2 would also be removed at the same time.
Neben einer in eine Richtung möglichen Krümmung ist, wie in Figur 3 dargestellt, auch eine Krümmung in zwei Richtungen möglich. Bei heute üblichen Chipdicken von 185 μm lassen sich somit leicht zu Verformungen von mindestens 1 μm über die ge- samte Chipfläche erreichen. Dabei ist zu beachten, daß gegebenenfalls der Chip stärker gedünnt werden könnte um eine stärkere Verformung zu erzielen. Ebenfalls ist an eine torsionsartige Verformung, wie in Figur 7 dargestellt zu denken. Dabei ist beispielsweise, wie mit den dargestellten Pfeilen angedeutet, ein gegengleiches Verdrehen jeweils gegenüberliegender Seiten, möglich.In addition to a curvature possible in one direction, as shown in FIG. 3, curvature in two directions is also possible. With today's common chip thicknesses of 185 μm, deformations of at least 1 μm can easily be achieved over the entire chip area. It should be noted that the chip could possibly be thinned more in order to achieve greater deformation. A torsion-like deformation, as shown in FIG. 7, should also be considered. For example, as indicated by the arrows shown, it is possible to twist opposite sides in opposite directions.
Um zu verhindern, daß für den Fall, daß es gelingt, das Material 4 abzutragen, mittels Druck das Substrat 1 wieder in ei- ne ebene Form zu drücken sei, können von der Substratoberfläche Teile A entfernt werden, wie in Figur 2 gestrichelt angedeutet ist. Dies erfolgt entweder durch schräges Abätzen oder Schleifen von Randbereichen des Substrates wie auf der linken Seite von Figur 2 dargestellt ist oder durch Herausätzen oder Schleifen von einzelnen Teilen A, wie auf der rechten Seite von Figur 2 dargestellt ist. Auf diese Weise ist gewährleistet, daß es nicht gelingt, oder zumindest sehr aufwendig ist, das Substrat 1 nach einer Verformung wieder in eine ebene Form zu bringen.In order to prevent the substrate 1 from being pressed back into a flat shape by means of pressure in the event that the material 4 can be removed, parts A can be removed from the substrate surface, as indicated by dashed lines in FIG , This is done either by obliquely etching or grinding edge regions of the substrate as shown on the left side of FIG. 2 or by etching out or grinding individual parts A as shown on the right side of FIG. In this way it is ensured that it is not possible, or at least very expensive, to bring the substrate 1 back into a flat shape after deformation.
Gemäß Figur 4 ist die integrierte Schaltungsanordnung so aufgebaut, daß das Substrat auf einem Träger 5 aufgebracht ist, wobei der Träger 5 das Substrat formt. Auch hier könnten wieder Ausnehmungen vorgesehen sein, die im Zusammenhang mit Figur 4 nicht dargestellt sind. Gemäß der Ausgestaltung nach Figur 5, ist der Träger 5 nicht wie gemäß Figur 4 nur an ei- ner Oberfläche verformt, sondern ebenfalls insgesamt aus einer ebenen Form in eine gekrümmte oder auch verdrehte Form gebracht .According to FIG. 4, the integrated circuit arrangement is constructed such that the substrate is applied to a carrier 5, the carrier 5 forming the substrate. Recesses could also be provided here, which are not shown in connection with FIG. 4. According to the embodiment according to FIG. 5, the carrier 5 is not only deformed on one surface as shown in FIG. 4, but is also made overall from a flat shape to a curved or twisted shape.
In einem weiteren erfindungsgemäßen Ausführungsbeispiel sind auf der Oberfläche des Trägers 5 Erhebungen 6 ausgebildet, die beim Zusammenbringen mit dem Substrat 1, das Substrat 1 zusammen mit seinen aufgetragenen Schichten verformt . Dies kann insbesondere dadurch erfolgen, daß ein ähnliches Material 4, wie im gemäß Figur 2 dargestellten Ausführungsbeispiel in die Zwischenräume zwischen den Erhebungen, dem Substrat und dem Träger eingebracht ist, der mit dem Trocknen zur Verspannung des Substrates führt .In a further exemplary embodiment according to the invention, elevations 6 are formed on the surface of the carrier, which, when brought together with the substrate 1, deforms the substrate 1 together with its applied layers. This can take place in particular in that a material 4 similar to that in the exemplary embodiment shown in FIG. 2 is introduced into the spaces between the elevations, the substrate and the carrier, which leads to the bracing of the substrate when drying.
Zusammenfassend sei darauf hingewiesen, daß die Grundidee der Erfindung darin beruht, das eine integrierte Schaltung tragende Substrat dauerhaft so zu verformen, daß es nicht gelingt mittels eines Schleifverfahrens selektiv die auf dem Substrat aufgetragenen Schichten schichtweise abzutragen.In summary, it should be pointed out that the basic idea of the invention resides in permanently deforming the substrate carrying an integrated circuit in such a way that the layers applied to the substrate cannot be selectively removed by means of a grinding process.
Grundsätzlich ist es auch denkbar, einen Halbleiter-Chip mit einer grundsätzlich von der Planarität abweichenden Oberfläche direkt zu fertigen. Auf einer derartigen Chipoberfläche sind die üblichen Verfahrensschritte zu Herstellung integrierter Schaltungen mit den heute verfügbaren Technologien nur sehr schwer einsetzbar, um integrierte Schaltungen mit der gewünschten Komplexität herzustellen. BezugszeichenlisteIn principle, it is also conceivable to produce a semiconductor chip directly with a surface that fundamentally deviates from planarity. On such a chip surface, the usual method steps for producing integrated circuits with the technologies available today are very difficult to use in order to produce integrated circuits with the desired complexity. LIST OF REFERENCE NUMBERS
1 Substrat1 substrate
2 erste Schicht2 first layer
3 zweite Schicht3 second layer
4 Material (z.B. Klebstoff, Keramik)4 material (e.g. adhesive, ceramic)
5 Träger5 carriers
6 Erhebungen6 surveys
A Ausnehmungen A recesses

Claims

Patentansprüche claims
1. Integrierte Schaltungsanordnung bestehend aus einem flächigen Substrat (1), auf dem zumindest einseitig eine in- tegrierte Schaltung in mehreren Schichten (2, 3) ausgebildet ist, wobei zumindest eine Oberfläche des Substrats (1) zumindest in einer Ausbreitungsrichtung nicht planar ist, d a d u r c h g e k e n n z e i c h n e t, daß das Substrat (1) auf einem Träger (5) angeordnet ist, der dem Substrat eine Krümmung verleih .1. Integrated circuit arrangement consisting of a flat substrate (1) on which an integrated circuit is formed in several layers (2, 3) on at least one side, at least one surface of the substrate (1) being non-planar at least in one direction of propagation, characterized in that the substrate (1) is arranged on a carrier (5) which gives the substrate a curvature.
2. Integrierter Schaltungsanordnung nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t, daß die zumindest eine Oberfläche in einer zweiten Richtung nicht planar ist.2. Integrated circuit arrangement according to claim 1, so that the at least one surface is not planar in a second direction.
3. Integrierte Schaltungsanordnung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß das Substrat (1) durch eine geeignete Verbindungstechnik mit mindestens einem zweiten Substrat verbunden wird, wodurch mechanische Spannungen entstehen, die dem Substrat die Krümmung verleihen.3. Integrated circuit arrangement according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the substrate (1) is connected by a suitable connection technology with at least one second substrate, thereby creating mechanical stresses that give the substrate the curvature.
4. Integrierte Schaltung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß im Substrat (1) durch chemische oder physikalische Änderungen des Gefüges des Substrates mechanische Spannungen entstehen, die dem Substrat die Krümmung verleihen.4. Integrated circuit according to one of the preceding claims, so that mechanical stresses arise in the substrate (1) by chemical or physical changes in the structure of the substrate, which give the substrate the curvature.
5. Integrierte Schaltungsanordnung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß dem Substrat (1) an einer seiner Oberflächen Teilbereiche entfernt sind, so daß Strukturen entstehen, in die das nach Anspruch 3 aufgebrachte Material eindringen kann.5. Integrated circuit arrangement according to one of the preceding claims, characterized in that partial areas of the substrate (1) are removed on one of its surfaces, so that structures arise into which the material applied according to claim 3 can penetrate.
6. Integrierte Schaltungsanordnung nach Anspruch 4, d a d u r c h g e k e n n z e i c h n e t, daß der Träger (5) an seiner Oberfläche mindestens eine Erhebung (6) aufweist. 6. Integrated circuit arrangement according to claim 4, so that the carrier (5) has at least one elevation (6) on its surface.
EP02703497A 2001-02-14 2002-01-22 Integrated circuit arrangement consisting of a flat substrate Withdrawn EP1360718A2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10106836 2001-02-14
DE10106836A DE10106836B4 (en) 2001-02-14 2001-02-14 Integrated circuit arrangement of a flat substrate
PCT/DE2002/000191 WO2002065548A2 (en) 2001-02-14 2002-01-22 Integrated circuit arrangement consisting of a flat substrate

Publications (1)

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EP1360718A2 true EP1360718A2 (en) 2003-11-12

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US (1) US7199448B2 (en)
EP (1) EP1360718A2 (en)
JP (1) JP3979942B2 (en)
CN (1) CN100392846C (en)
DE (1) DE10106836B4 (en)
TW (1) TW519759B (en)
WO (1) WO2002065548A2 (en)

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DE102004007690B3 (en) * 2004-02-16 2005-10-13 Infineon Technologies Ag Integrated circuit arrangement
US8691663B2 (en) * 2009-11-06 2014-04-08 Alliance For Sustainable Energy, Llc Methods of manipulating stressed epistructures
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JP2004523904A (en) 2004-08-05
CN1541413A (en) 2004-10-27
JP3979942B2 (en) 2007-09-19
WO2002065548A3 (en) 2002-10-17
DE10106836B4 (en) 2009-01-22
US7199448B2 (en) 2007-04-03
US20040070052A1 (en) 2004-04-15
CN100392846C (en) 2008-06-04
DE10106836A1 (en) 2002-09-05
WO2002065548A2 (en) 2002-08-22

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