EP1352397A1

EP1352397A1 - Method for testing a non-volatile memory and the use of such a method

Info

Publication number: EP1352397A1
Application number: EP02710781A
Authority: EP
Inventors: Wolfgang Rankl
Original assignee: Giesecke and Devrient GmbH
Current assignee: Giesecke and Devrient GmbH
Priority date: 2001-01-11
Filing date: 2002-01-08
Publication date: 2003-10-15
Also published as: DE10101234A1; WO2002063634A1

Abstract

The invention relates to a method for testing a programmable memory, whereby the test is integrated into the programming process and the data which is to be stored is used as test models so that said data remains in the memory immediately after the test without it being necessary to add a writing step. The depth of the test n can be adjusted in a variable manner. The test model is produced, particularly, by inverting the data which is to be stored and the test is carried out twice.

Description

Method of testing non-volatile memory and use of such a method

The invention relates to a method for testing a non-volatile memory according to claim 1 and a use of the method according to claims 14 and 15.

Chip cards have a wide variety of applications and uses. So-called memory cards are primarily used as telephone cards, health insurance cards or as cards for automatic machines or in public transport. However, their functionality is limited to a specific application.

Microprocessor cards also contain a CPU. In addition to the CPU, these cards usually contain an I / O unit, a data,

Control and address bus, a volatile read / write memory (RAM) and a non-volatile programmable memory (EEPROM) and a non-volatile read-only memory (ROM). The operating system is mainly stored in the ROM and partly in the EEPROM. Fields of application for such microprocessor cards are: ID cards, electronic payments or access to the digital cellular network (GSM) etc.

It is common to all card types that the cards are produced in large numbers, so that the production process must be optimized in terms of time and costs.

When enumerating the possible areas of application of these cards, it becomes clear that particular importance must be attached to the safe and error-free functioning of the card and its components in order to be able to guarantee reliable operation of the card system overall. The error-free function of the components used must therefore be checked during card production.

The manufacturing cycle of a card can be divided into the following sections: The chip and the chip card are initially manufactured. In this first phase, the design of the chip is carried out, the operating system of the chip card is created, the card body and the module are manufactured, and the modules are embedded in the card body.

In the second phase, all basic, non-card-specific data is loaded. In this phase, special tests of the individual hardware components are carried out. Here it is essential to achieve a high throughput so that the tests take up as little of the expensive production time as possible. The test of the EEPROM is particularly important here, since it is very time-consuming due to the regular write times. Furthermore, all card-specific data relating to the respective application are transferred from the card issuer to the company that personalizes the cards, such as the file tree for the respective application, its name etc. The operating system previously stored in ROM is then completed by Parts of it, such as link tables or certain program code, are written into the EEPROM. In the next initialization step, all application-specific data are loaded.

Only then can all the data that are assigned to the person using the card be loaded in the third phase, the so-called personalization.

The throughput is restrictive for both the second and the third phase of the card manufacturing process Bottleneck in the transmission of data and memory access to the EEPRROM can be seen.

The card is only operational after the three phases just described have expired. It is therefore necessary to ensure that this complex process runs without errors and that no multiple executions of individual manufacturing steps are necessary because, for example, a single component proves to be defective.

It is only recognized after the personalization of the card that a

Memory module does not work properly, all previous steps have been pointless. It is therefore necessary to recognize early and safely, if possible with no additional effort, whether the components used in the manufacture of the chip card are also working correctly so that the function of the card can be ensured.

So far, a test for an EEPROM memory of a chip card has been carried out by alternately writing two special test patterns on the memory cells of the EEPROM. The memory content was then read out again and the operating system monitors whether the read date corresponds to the write date. The binary coding "10101010" and the binary coding "01010101" - corresponding to a checkerboard pattern - were alternately selected as the test pattern, which corresponds to the date "AA" or "55" in the hexadecimal coding.

A microcomputer with a PROM is known from US Pat. No. 5,175,840, which increases the access to the PROM from the outside and thus increases security by providing additional access monitoring means, in particular in the form of a control circuit. However, this method does not disclose an improved test method. In the test methods from the prior art, it is disadvantageously necessary to create a specific test pattern (for example a checkerboard pattern) as a test data record and to read this in and out. Only then can the actual data to be saved be transferred to the EEPROM.

A major disadvantage with regard to the production time is therefore the additional time required for accessing the memory for test purposes only. Because in order to make the manufacturing process as cost-effective as possible, all necessary steps must be carried out in a time-minimized manner. It proves disadvantageous here that the write and read accesses to the memory modules, in particular to the EEPROM, are very time-consuming. For a check of the read / write memory according to the prior art, in addition to the read / write accesses which are necessary due to the application, additional write and read accesses had to be factored in for checking these modules.

EEPROM cells can only be written to and deleted again to a limited extent; the number of possible accesses is physical. On

EEPROM memory is divided into pages. If only a single bit of an EEPROM memory needs to be changed, the associated page - ie the entire page of the memory - must be deleted beforehand.

With a 32-byte memory page, this process alone takes approx. 10 ms. For this reason, too, access to the EEPROM cells must be minimized in order not to unnecessarily reduce the life of the card.

In previous tests, it was necessary, depending on the desired test depth, to write several test patterns to the memory, to read them out again and then to compare them for agreement. Only after that could - at positive test result - the data to be stored is written to the EEPROM in an additional access. The tests are necessary, but in their current form they do not significantly extend the manufacturing cycle.

It is therefore the object of the present invention to provide a method which enables a time and therefore cost-minimized checking of read / write memories with any test depth.

This object is achieved according to the invention by a test method of the type mentioned in the introduction, in which the test is carried out with data to be stored and is integrated in time in a write operation of the memory and in that at least one test pattern is created based on the data to be stored, so that storing data can be regenerated automatically at least from the test pattern last created, the following process steps being carried out at least once in an n-fold iteration:

(1) creating a test pattern (2) write access f to the non-volatile memory with the test pattern,

(3) Read access to the non-volatile memory to acquire an nth test result

(4) Comparison of the nth test result with the test sample for agreement.

This object is further achieved by using the method just described by the operating system as a long-term test for the memory chips used in the operation of the card, or by only occasionally using it as a functional test in the test, initialization and personalization of the chip card production steps. With this solution, the test of a memory component can be optimally integrated into the card's production cycle. The test according to the invention can be activated in particular during or immediately before a write access to the memory which is necessary anyway and without the use of special test data or devices which generate the test data.

Advantageously, multi-stage tests with one and the same data set are also possible by means of the method according to the invention. The depth of the test can be changed by repeatedly inverting the data and thus by the number of iterations. In the preferred embodiment, the test is carried out in two stages, i.e. with a first inversion of the data and a second re-inversion, so that when the test is successfully completed, the data to be stored are immediately in the memory. This advantageously saves several 5 time-consuming write accesses to the memory. With the solution according to the invention, once the test has been successfully completed, the data to be stored are immediately in the memory, regardless of the test depth or the number of process runs.

By using the data to be stored as test data, the test times of the chip card can advantageously be significantly reduced.

So far, the CPU had to be equipped with specific software modules in order to generate the test patterns so that the best possible test coverage could be achieved. With the method according to the invention, however, this is no longer necessary, since the data to be stored can be used directly for the test.

Furthermore, it proves to be advantageous that an optimal test quality is automatically achieved by inverting the ones to be stored Data and the subsequent re-inversion of each bit are once set to "0" and "1" and thus tested.

Alternatively, the method is also used for the temporary swapping out of memory contents.

As already explained, in the preferred embodiment of the invention, the method is run twice (i.e. n = 2). During the first run, the test pattern is created by inverting the data to be stored, so that after the first positive run of the method, the complement of the data to be stored is in the memory. This test pattern is then inverted again at the end of the first process run. In the second process run, the memory is thus written with the data to be stored, so that after the second process run has been completed positively, the data to be stored are exactly in the non-volatile memory and no additional writing process is necessary. In this embodiment, the creation of the test pattern is based on inverting the data to be stored.

In an alternative embodiment, the test pattern can also be derived in another way from the data to be stored, for example by means of an XOR link or the like.

Furthermore, it is possible to run through the method not only twice but several times and to invert the test pattern again and again until the data to be stored are again in memory until the end after the end of the last method.

In general, the described method can be used for all types of

Use free memory management of chip card systems by each Memory access and thus currently the functionality of the memory or memory area is checked. The main application, however, is in memory defragmentation, in which data has to be moved from certain memory areas.

However, the method is also used sensibly for cases in which memory space that is no longer required is released for other applications - the so-called garbage collection.

However, it is also possible according to the invention to use flash memory cells, such as a flash EEPROM or a FeRAM memory, which allow much faster access times than the regular EEPROM cells. This leads to even better manufacturing and especially test times.

Further advantages, features and alternative embodiments of the invention result from the following detailed description of the figures.

1 shows a schematic flow diagram of a method according to the invention.

An example of a possible sequence of the method is explained below with reference to FIG. 1.

There are basically two main areas of application for the invention:

1. the use of the method for testing a memory before commissioning a chip card and 2. the use of the method during the operation of the chip card with each memory access as an endurance test, which is controlled by a memory test manager.

In the first embodiment, the test is used in the test-initialization-personalization production steps of the chip card. Data to be stored is used in such a way that it is automatically stored in the memory after the last test run and without additional write access.

The second use is to use the EEPROM test as a long-term test in order to check the functionality of the memory or memory area before each write access to the memory. The data to be saved is also used to create a test sample.

The test depth n and thus also the test time can advantageously be variably adjusted. It can therefore be adapted to the respective system conditions.

For example, is it necessary to have a very quick but relatively rough test, i.e. to use a test with only a little test coverage, then the test depth chosen is n = 1, which means that the method according to the invention is run through only once. Then the data to be saved are used identically for the creation of the first and only test sample. The

Test patterns and thus the data to be stored are then written to the non-volatile memory, preferably to the EEPROM, in the next method step. The memory content is then read out. The reading out of the memory content is recorded in a test result and compared with the test pattern, that is to say with the data which have been written into the memory. If the two data records do not match, then there is an error and the process terminates with an error message. Otherwise, the method ends successfully and after the test the data to be saved are immediately in the memory.

In the main and preferred embodiment, however, the test has a test depth of n = 2. This means that the process steps of test pattern generation, write access, read access and comparison are carried out twice. The first test pattern is preferably created during the first run by inverting the data to be stored. The first test pattern is thus the complement of the data to be stored. After the write and subsequent read access to the memory and the comparison of the read and written data, the first test pattern is inverted again, so that a second test pattern now again corresponds identically to the data to be stored. After the process run with the second test pattern, if the test result is positive (i.e. the data written and read match), the data to be stored are in the memory and the test / write process is completed.

In order to achieve a better test depth n, the just described can

The method can also be repeated several times by setting the test depth n to more than "2".

In the embodiment just described, the operation by means of which the test pattern is created from the data to be stored is one

Inversion operation. The data to be stored or the test pattern is inverted bit by bit, ie changed from "0" to "1" and from "1" to "0". This has the advantage that each bit in the memory is tested for both values at least once. Thus, the method provides maximum test coverage with a minimal test time, whereby for the write access of the data to be stored no additional access is necessary.

Alternatively, however, other operations are also conceivable, such as an XOR operation.

Furthermore, it is possible not to perform the operation on the data to be stored and the complement of this operation alternately, as in the previously described method, but rather to select a series of operations which enable maximum test coverage and again after the last process run the original data from the last test sample can be restored. The following example is intended to illustrate this:

1st operation: "+1",

2nd operation: "+1" n. Operation: "+1" and last operation: "- n".

The individual operations to create the respective

Test samples may be different; the only requirement for the selection of the operations is that the data to be stored can be restored after the last run or after the last test pattern. Firstly, it is possible to derive the data directly from the current, last test pattern (as with the inversion operation) or secondly by analyzing the previous operations (in the example above: by the number of increments by "1". This does, however, set something complex analysis device for the regeneration of the data to be stored in advance, since all operations on the data to be stored must be traced. It is therefore the cost-effective form of the method if inversion is used as the operation. Then it is important to distinguish whether the method has an even or odd test depth n. In the first case (n even), the first test pattern has to be inverted and the last one is left because it matches the original data. In the second case (n odd), the first test pattern must match the data to be stored identically.

It proves to be advantageous that the method provides for iteration of certain method steps. A counter i, which is at the beginning of the

Method is 1, incremented with each iteration. As long as the counter has not reached the predetermined value of the test depth n - that is, as long as T <n '- the iteration is run through. This makes it possible to achieve a higher test coverage by selecting the test depth. If, for example, two test patterns - by inverting the data - are used, the iteration can also be run through more than twice in order, for example, to record external disturbing influences which affect the function of the memory. These can be factors such as the changing temperature or the minimally changing voltage level of the circuit.

The invention is accordingly to be seen in a device which carries out the method just explained. For this purpose, the chip card, in particular the operating system, must be equipped with an inverter and possibly with a multiplexer and a counter i so that the data to be stored and then the respective test pattern can be inverted. However, if the test pattern is not to be created by an inversion operation, the chip card must have means for creating a test pattern. This means must be designed in such a way that, at a test depth of n, after the nth test run, the data to be stored can be regenerated from the last test sample. If the EEPROM test is to be used while the card is in operation, the so-called memory test manager is used. It uses the test procedure described above to check whether the requested memory area is functional. The memory test manager is thus an intermediate instance between a memory manager of the chip card and the memory.

Claims

claims

1. Method for testing a programmable memory, in which the test is carried out with data to be stored and is integrated in time in a programming operation of the memory and in that at least one test pattern is created based on the data to be stored, so that the data to be stored are at least a test sample created last can be regenerated automatically, the following procedural steps being carried out at least once: - Creation of the test sample

Write access to the memory with the test pattern,

Read access to the memory for recording an i-th test result

Comparison of the i-th test result with the test sample

Accordance.

2. The method according to claim 1, characterized in that the number of iterations defines a test depth (n), with n> 1 and where n is an even number.

3. The method according to claim 2, characterized in that in the first step, the first test pattern is created by inverting the data to be stored and that after the last process run, the data to be stored are regenerated by inverting the last test pattern.

4. The method according to any one of the preceding claims, characterized in that the iteration is run through twice and that two test patterns are used, the first test pattern being the complement of the data to be stored and the second test pattern being the data to be stored.

5. The method according to claim 1, characterized in that the number of iterations is not an even number (n = 1,3,5,7) and that in the first step the first test pattern is created identically from the data to be stored and that the others Test samples are inverted after each process run.

6. The method according to any one of the preceding claims, characterized in that the test pattern is created automatically on the basis of the data to be stored.

7. The method according to any one of the preceding claims, characterized in that the memory is a non-volatile read / write memory, in particular an EEPROM.

8. The method according to any one of the preceding claims, characterized in that the memory is a flash or a FeRAM memory.

9. The method according to any one of the preceding claims, characterized in that the test is carried out automatically before each write access to the memory.

10. The method according to any one of the preceding claims, characterized in that the test patterns are created by at least one operation on the data to be stored, so that the data to be stored can be regenerated automatically from the last test pattern after the last process run.

11. The method according to claim 10, characterized in that the operation is an XOR operation.

12. The method according to any one of the preceding claims, characterized in that the method terminates with an error message if the i-th test result does not match the i-th test pattern.

13. The method according to any one of the preceding claims, characterized in that the test pattern is recreated from iteration to iteration and does not have to match the other test patterns.

14. Use of the method according to one of the preceding claims, characterized in that the method of the operating system in each

Write access to the memory is used as an endurance test.

15. Use of the method according to any one of claims 1 to 13, characterized in that the method is used once as a function test before starting up the memory.