Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/46—Multiprogramming arrangements
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/46—Multiprogramming arrangements
  • G06F9/48—Program initiating; Program switching, e.g. by interrupt
  • G06F9/4806—Task transfer initiation or dispatching
  • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system

Definitions

• the present invention relates to the field of parallel electronic architectures (multiprocessors and multitasking). It relates to an architecture comprising a plurality of processing units connected to a communication bus and dialoguing with one another according to a new protocol.
• each processing unit is identified on the bus by its own physical address.
• the communication protocols known to date allow a first processing unit (hereinafter called the transmitting unit) to dialogue with a second processing unit (hereinafter called the target unit).
• the transmitting unit sends a message to the target unit, with a view for example to triggering the execution by the target unit of a predefined task
• the transmitting unit transmits on the bus the address of the target unit.
• Each processing unit is able to decode an address sent on the bus, and when a target unit recognizes its address, it loads the associated message into local memory and executes the task for which it is programmed.
• the target and sending unit generally have similar address and data buses of fixed size.
• the parallel architecture of the invention which is known in that it comprises a plurality of processing units connected to a communication bus, each processing unit being designed to automatically execute one or more predefined tasks .
• the operation of the architecture of the invention is based on a new principle which is the addressing of a functionality on the communication bus, rather than the addressing of a target processing unit. given.
• the header which characterizes a functionality thus makes it possible to wake up all the connected processing units which recognize this functionality, so that these processing units execute in parallel the task associated with this functionality.
• FIG. 4 shows a timing diagram of the main signals implemented during a write operation on the bus ⁇ , by the master processing unit, of a word of a frame.
• FIG. 5 represents a timing diagram of the main signals implemented during a reading operation, by a slave processing unit, of a valid header present on the bus ⁇ ,
• FIG. 6 represents a timing diagram of the main signals implemented by a slave processing unit, after reception by this slave processing unit of a valid header, and writing on the bus oc, of a frame of words by the master processing unit,
• the bus is a data bus which is generally composed of (q) parallel electrical conductors, q being an integer greater than or equal to 1.
• the bus is a bus consisting of sixteen parallel electrical conductors (16-bit bus (D0-D15)).
• the processing unit 1a is a 16-bit machine (data bus D0- D15)
• the processing unit 1 _ is a 4-bit machine (data bus D0- D3)
• the processing unit 1 ⁇ is an 8-bit machine (data bus D0-D7).
• A, B, C, D, ... a processing unit capable of communicating only on one (AG) will be of color A; a processing unit capable of communicating a maximum of two (AG) will be color B; a processing unit capable of communicating a maximum of four (AG) will be color C, a processing unit capable of communicating a maximum of eight (AG) will be color D, etc.
• a word corresponds to the value of the bus ⁇ at a given instant.
• the maximum size of a word is limited by the number of parallel bus conductors - Message
• serial format allows you to define all the words that make up a message traveling on the bus.
• the serial formats usable on the bus can be very different, and necessarily have the common characteristic that the first word of a message is a header.
• XXXX indicates that it is possible to take any possible value.
• the 0 indicates that all the conductors of this AG are set to zero.
• FP-A we use the AG first conductors of the bus for all the other words which will compose the frame of the message thereafter. We therefore address all the processing units connected to the bus and having the desired functionality, since by definition even the smallest processing unit can communicate on an AG.
• FP-B we use the 2AG first conductors of the bus for all the other words which will compose the frame of the message thereafter.
• FP-C we use the 4AG first conductors of the bus for all the other words that will compose the message frame thereafter.
• FP-D we use the first 8AG conductors of the bus for all the other words that will compose the message frame thereafter.
• the FP-AB format is intended for both processing units that can read on 1 AG and those that can read on 2 AG. Those who read on 1 GA have sufficient information to fulfill the functionality but do not necessarily have all the details. Those who read on 2 GA can for example have an error correcting code on the 2 em ⁇ AG to check the information which passed on the 1 st AG.
• the FP-AD format is a format which can for example be advantageous for the transmission of small images on the bus -
• the first AG can be used to code the average level of gray (or color) of a block of 9 pixels. Processing units having access only to this information still benefit from the data: an image three times smaller.
• the header is the first word of any message passing on the bus, and it mainly defines what functionality is addressed.
• this header also makes it possible to define:
• Functionality Any function (or task) which can be executed automatically by a processing unit connected to the bus is called “functionality”.
• a processing unit 1a, 1b, ..., or 1n When a processing unit 1a, 1b, ..., or 1n has taken the direction of the bus ⁇ , it begins by writing a header on the bus (FunctionKey), then writes then on the bus to a frame (a or more words in depending on the serial format (FS) used).
• FunctionKey a header on the bus
• FS serial format
• the header is read by each slave processing unit.
• the header mainly allows each slave processing unit to determine whether the frame sent on the bus a is intended for it, and if so, what is the task that it must perform.
• the slave processing unit When the header sent on the bus is not part of the functional table of a slave processing unit, the latter ignores the frame sent on the bus subsequent to the header. Otherwise, the slave processing unit also reads the frame sent on the bus after the header, and automatically executes the task which is associated with this header in its functionality table.
• a processing unit 1a, ..., 1n essentially comprises:
• a validation memory 3 a memory 4 of the FIFO type
• a logic unit 5 allowing the sequencing of the operation of the validation memory 3 and of the FIFO memory 4, from clock signals CLKA and CLKD,
• a data bus 6, hereinafter called the interface bus - an internal bus 7, on which the microprocessor 2 can read or write data
• - three-state registers 6a which under the control of microprocessor 2 (signal 8) allow the writing present on the interface bus 6 (D0-D15) of the data present on the internal bus 7.
• the read access to the validation memory 3 is sequenced by the signal 5a, delivered by the logic unit 5, from the clock signals CLKA and CLKD.
• the validation memory 3 has the function of validating or not (signals 9), for the microprocessor 2, a header present on the bus ⁇ -
• a header present on the bus ⁇ -
• the microprocessor 2 is informed that it must load the frame which is transmitted on the bus after the header which has been validated .
• the microprocessor 2 ignores the frame which is sent on the bus ⁇ after this header.
• the FIFO memory 4 is connected at the input to the bus ⁇ via the interface bus 6, and at the output to the data bus of the internal bus 7.
• the microprocessor 2 can control the loading, in the FIFO memory 4, of a word present on the bus ⁇ , by means of the write signal 10, as well as the output of a word stored in the FIFO memory 4, and its writing on the data bus of the internal bus 7, by means of the read signal 11.
• the sequencing of the loading of a word in FIFO memory 4, or of a reading of a word in FIFO memory 4 is synchronized by a timing signal 5b, delivered by logic unit 5 from CLKA and CLKD clock signals.
• the FIFO memory 4 also delivers at the output for the microprocessor 2 status signals 12 making it possible to indicate to the microprocessor 2 its filling level.
• the FIFO memory 4 is produced from two 8-bit integrated circuits CI2 and CI3, and for example from integrated circuits marketed under the reference IDT7200, each integrated circuit CI2 and CI3 being dedicated respectively to the storage of the most significant bits (D8 to D15) and of the least significant (D0 to D7) of the bus ⁇ .
• the signals referenced in FIG. 2 "EmptyJlag_H”, “FullJlag_H”, “HalfJull_H”, “EmptyJlag_B”, “FullJlag_B”, “HalfJull_B”, correspond to the aforementioned status signals 12 of the block diagram of FIG.
• the signal referenced “Write_FIFO_OK” corresponds to the above-mentioned write signal 10 in FIG. 1.
• the signals “Read_ FIFO _ B” and “Read _FIFO _ H” correspond to the aforementioned read signal 11 in FIG 1.
• the signal “Reset_FIFO »I s a reset signal of the FIFO memory which is delivered by the microprocessor 2, and which is used to initialize the memory 4.
• the data bus of the internal bus 7 of a processing unit is connected in parallel to the interface bus 6, via one or more three-state registers 6a.
• the processing unit 1a implementing a 16-bit internal bus (DJSA0- DJSA15)
• two eight-bit registers dedicated to writing in parallel on the interface bus 6 can be used, and thereby even on the bus ⁇ , respectively the eight least significant bits (D- ISA0-DJSA7) and the eight most significant bits (DJSA8-DJSA15) of the data bus of the internal bus 7.
• Transfer to the bus (DO- D15 ) of data present on the data bus (DJSAO - DJSA15) of the internal bus 7 is controlled by the microprocessor by means of the write signal 8 (FIG. 1).
• each microprocessor 2 of a processing unit outputs two clock signals 2a and 2b, which are connected, via doors 13 with open collector, to a clock bus (CLKA, CLKD) common to all processing units.
• CLKA, CLKD clock bus
• the clock signals CLKA and CLKD correspond respectively to the clock signals 2a and 2b of the microprocessor 2 of this master processing unit; the clock signals 2a and 2b of the other slave processing units are floating and isolated from the clock bus CLKA and CLKD.
• the exchange of data on the bus is thus clocked by the master processing unit, the slave processing units ensuring the loading of the messages written on the bus ⁇ (validation memory 3 / signal 5a; FIFO memory 4 / signal 5b) whatever their own clock speed (natural operating frequency of their microprocessor 2). Processing units having different own clock speeds can therefore advantageously interact with one another.
• the microprocessor 2 of a processing unit is programmed to execute the following main program in a loop: a) reading in FIFO memory 4 of a message (header and frame), b) decoding of the functionality associated with this header in the functionality table; c) automatic execution of the routine (task) corresponding to this functionality.
• step c) it may happen that the microprocessor 2 is required to write on the bus ⁇ a message, in order to activate a functionality managed by one or more other processing units. connected to the bus ⁇ -
• the processing unit writes on the bus the header coding this functionality, and the frame of the words of the message, then releases the bus ⁇ -
• the timing diagrams of the main signals used during such a write operation are shown in Figures 3 and 4 respectively.
• FIG. 6 represents the timing diagrams of the main signals implemented during a reading operation on the bus ⁇ , by a slave processing unit, of a valid header
• FIG. 6 represents the timing diagrams of the main signals implemented during a reading operation on the bus ⁇ , by a slave processing unit, of a frame of words (FIG. 6 / "Data n", "Data n + 1") written on the bus by a master processing unit, in relation to a valid header previously written on the bus ⁇ -
• the IRQ # P interrupt momentarily changes state.
• the capture of this valid header in the FIFO 4 memory (signal 10 / Writing_FIFO_OK) is done by the simultaneous action of the signals CLKA and CLKD.
• the capture of data in the FIFO memory 4 is clocked only by the signal CLKD.
• Reception of an invalid header / figure 7 With reference to figure 7, when the header present on the bus ⁇ is not valid for a slave processing unit, the interrupt signal IRQ # P does not change state, and the aforementioned main program of microprocessor 2 is not interrupted.
• the microprocessor 2 does not command the loading of the header present on the bus ⁇ in the FIFO memory 4 (signal Writing_FIFO_OK does not change state), nor subsequently the loading in FIFO memory 4 of the frame of words passing over the bus after this header. The message passing over the bus is thus ignored by the slave processing unit.
• the multi-processor architecture which has been described with reference to FIGS. 1 to 7 has the main advantages below:
• This parallel architecture is “universal”: it makes it possible to make dialogue between them different processing units, and in particular processing units having data buses (bus interface 6) of different sizes; the only limitation on the size of the processing units that can be connected is the number of bits in parallel of the bus', this architecture does not work with a single data format, but works with any data format, greater than or equal to the size of the atom of granularity (AG).
• the processing units can communicate with one another regardless of their processors, and above all regardless of the clock rate of their processors.
• the propulsion card includes in its functional table the header values '1', '2', '3', '6' and '10' associated respectively with the following functionalities: "emergency stop” , "Request to move forward”, “request to move back”, “recognition of a human”, “request to identify the cards present”.

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• 2000
  • 2000-12-22 FR FR0016858A patent/FR2818774B1/fr not_active Expired - Fee Related
• 2001
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