EP1342260A1 - Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing - Google Patents

Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing

Info

Publication number
EP1342260A1
EP1342260A1 EP01990802A EP01990802A EP1342260A1 EP 1342260 A1 EP1342260 A1 EP 1342260A1 EP 01990802 A EP01990802 A EP 01990802A EP 01990802 A EP01990802 A EP 01990802A EP 1342260 A1 EP1342260 A1 EP 1342260A1
Authority
EP
European Patent Office
Prior art keywords
nickel
high resistance
nickel silicide
processing process
semiconductor processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01990802A
Other languages
German (de)
French (fr)
Inventor
Eric N. Paton
Ercan Adem
Jacques J. Bertrand
Paul R. Besser
Matthew S. Buynoski
John Clayton Foster
Paul L. King
George Jonathan Kluth
Minh Van Ngo
Christy Mei-Chu Woo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/729,699 external-priority patent/US6605513B2/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of EP1342260A1 publication Critical patent/EP1342260A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/01312—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional layer comprising a metal or metal silicide formed by deposition, i.e. without a silicidation reaction, e.g. sputter deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions (64, 66) of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy (52) is reacted with a silicon material (46) to form at least one high resistance nickel silicide region (56, 58). Unreacted nickel (54) is removed. A dielectric layer (60) is then deposited over the high resistance nickel silicide regions (56, 58). In a second temperature treatment, the at least one high resistance nickel silicide regions (56, 58) and dielectric (60) are reacted at a prescribed temperature to form at least one low resistance silicideregion (64, 66) and process the dielectri c layer (60). Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel (54) between silicide region (56, 58) is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions (56, 58) and the dielectric layer (60) are conveniently combined into a single temperature treatment. In other embodiments, the second temperature treatment is performed prior to, and separate from, the depositing and processing of the dielectric layer (60).

Claims

CLAIMSWHAT IS CLAIMED IS
1. A semiconductor processing process, comprising the steps of: depositing nickel metal or nickel alloy (52) on at least one silicon layer (46); reacting at least a portion of the nickel metal or nickel alloy (52) with the silicon layer (46) at a first temperature for a first period of time to form at least one high resistance nickel silicide region (56, 58); removing unreacted nickel metal or nickel alloy (54); and reacting the high resistance nickel silicide region (56, 58) at a second temperature for a second period of time to form at least one low resistance nickel silicide region (64, 66).
2. The semiconductor processing process of claim 1, further comprising depositing a dielectric layer (60) over at least one high resistance nickel silicide region (56 58) prior to reacting the high resistance nickel silicide region (56, 58).
3. The semiconductor processing process of claim 1, wherein the first temperature is in the range of about 250°C to about 350°C.
4. The semiconductor processing process of claim 1, wherein the second temperature is in the range of about 400°C to about 600°C.
5. The semiconductor processing process of claim 1, wherein the high resistance nickel silicide region (56, 58) is at least one of Ni3Si and Ni2Si and the low resistance nickel silicide region (64, 66) is NiSi.
6. The semiconductor processing process of claim 1, wherein the first period of time is about 15 to about 90 seconds and the second period of time is about 15 to about 90 seconds.
7. The semiconductor processing process of claim 1, wherein the first period of time is about 30 to about 60 seconds and the second period of time is about 30 to about 60 seconds.
8. The semiconductor processing process of claim 1, wherein the first and second reacting steps form a two-step rapid thermal anneal process.
9. The semiconductor processing process of claim 2, wherein the first reacting step and the second reacting step from a one-step rapid thermal anneal with backend processing process.
EP01990802A 2000-12-06 2001-12-03 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing Withdrawn EP1342260A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US72969800A 2000-12-06 2000-12-06
US729698 2000-12-06
US729699 2000-12-06
US09/729,699 US6605513B2 (en) 2000-12-06 2000-12-06 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing
PCT/US2001/045829 WO2002047145A1 (en) 2000-12-06 2001-12-03 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing

Publications (1)

Publication Number Publication Date
EP1342260A1 true EP1342260A1 (en) 2003-09-10

Family

ID=27111928

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01990802A Withdrawn EP1342260A1 (en) 2000-12-06 2001-12-03 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing

Country Status (7)

Country Link
EP (1) EP1342260A1 (en)
JP (1) JP2004521486A (en)
CN (1) CN1633703A (en)
AU (1) AU2002230565A1 (en)
GB (1) GB2390224B (en)
TW (1) TW531792B (en)
WO (1) WO2002047145A1 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7232756B2 (en) 2003-04-16 2007-06-19 Samsung Electronics Co., Ltd. Nickel salicide process with reduced dopant deactivation
KR100870176B1 (en) * 2003-06-27 2008-11-25 삼성전자주식회사 Nickel alloy salicide process, method for manufacturing a semiconductor device using the same, nickel alloy silicide film formed thereby and a semiconductor device manufactured using the same
US7592674B2 (en) * 2004-06-23 2009-09-22 Nec Corporation Semiconductor device with silicide-containing gate electrode and method of fabricating the same
US7385294B2 (en) 2005-09-08 2008-06-10 United Microelectronics Corp. Semiconductor device having nickel silicide and method of fabricating nickel silicide
CN1937181B (en) * 2005-09-19 2010-11-17 联华电子股份有限公司 Semiconductor element with nickel silicide and method for manufacturing nickel silicide
US7456095B2 (en) * 2005-10-03 2008-11-25 International Business Machines Corporation Method and apparatus for forming nickel silicide with low defect density in FET devices
US7622374B2 (en) 2005-12-29 2009-11-24 Infineon Technologies Ag Method of fabricating an integrated circuit
JP2007242894A (en) * 2006-03-08 2007-09-20 Toshiba Corp Semiconductor device and manufacturing method thereof
CN100442460C (en) * 2006-04-03 2008-12-10 中芯国际集成电路制造(上海)有限公司 Method for forming nickel silicide by plasma annealing
US7432255B2 (en) * 2006-05-16 2008-10-07 Hoffmann-La Roche Inc. 1H-indol-5-yl-piperazin-1-yl-methanone derivatives
JP5538975B2 (en) 2010-03-29 2014-07-02 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
CN102468150B (en) * 2010-11-19 2013-12-04 中芯国际集成电路制造(上海)有限公司 Method for forming semiconductor device
CN103165485B (en) * 2011-12-08 2015-11-25 中芯国际集成电路制造(上海)有限公司 The monitoring method of Millisecond annealing technology stability

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980024663A (en) * 1996-09-18 1998-07-06 윌리엄 비. 켐플러 Method for forming silicide region
EP0836223A3 (en) * 1996-10-08 1999-12-15 Texas Instruments Inc. Method of forming a silicide layer
US5953612A (en) * 1997-06-30 1999-09-14 Vlsi Technology, Inc. Self-aligned silicidation technique to independently form silicides of different thickness on a semiconductor device
US6071782A (en) * 1998-02-13 2000-06-06 Sharp Laboratories Of America, Inc. Partial silicidation method to form shallow source/drain junctions

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0247145A1 *

Also Published As

Publication number Publication date
GB2390224B (en) 2004-12-08
AU2002230565A1 (en) 2002-06-18
JP2004521486A (en) 2004-07-15
GB0315661D0 (en) 2003-08-13
WO2002047145A1 (en) 2002-06-13
CN1633703A (en) 2005-06-29
TW531792B (en) 2003-05-11
GB2390224A (en) 2003-12-31

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Inventor name: WOO, CHRISTY, MEI-CHU

Inventor name: NGO, MINH, VAN

Inventor name: KLUTH, GEORGE, JONATHAN

Inventor name: KING, PAUL, L.

Inventor name: FOSTER, JOHN, CLAYTON

Inventor name: BUYNOSKI, MATTHEW, S.

Inventor name: BESSER, PAUL, R.

Inventor name: BERTRAND, JACQUES, J.

Inventor name: ADEM, ERCAN

Inventor name: PATON, ERIC, N.

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