EP1338029A1 - Semiconductor structure having high dielectric constant material - Google Patents

Semiconductor structure having high dielectric constant material

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Publication number
EP1338029A1
EP1338029A1 EP01981536A EP01981536A EP1338029A1 EP 1338029 A1 EP1338029 A1 EP 1338029A1 EP 01981536 A EP01981536 A EP 01981536A EP 01981536 A EP01981536 A EP 01981536A EP 1338029 A1 EP1338029 A1 EP 1338029A1
Authority
EP
European Patent Office
Prior art keywords
layer
monocrystalline
growing
earth metal
alkali earth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01981536A
Other languages
German (de)
French (fr)
Inventor
Jamal Ramdani
Ravindranath Droopad
Lyndee Hilt
Jay Curless
Stefan Zollner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of EP1338029A1 publication Critical patent/EP1338029A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer

Definitions

  • This invention relates generally to semiconductor structures and devices and to a method for their fabrication, and more specifically to semiconductor structures and devices and to the fabrication and use of semiconductor structures, devices, and integrated circuits that include a non-stoichiometric, high dielectric constant oxide to reduce leakage current density.
  • Epitaxial growth of single crystal oxide thin films on silicon is of great interest in numerous device applications, such as, for example, ferroelectric devices, nonvolatile high density memory devices, and next-generation MOS devices. Also, in the preparation of these films, it is pivotal to establish an ordered transition layer or buffer layer on the silicon surface for the subsequent growth of the single crystal oxides, such as, for example, perovskites. Some of these oxides, such as BaO and BaTi0 3, were formed on silicon
  • SrTi0 3 on silicon (100) using an SrO buffer layer has been accomplished. See, e.g., T. Tambo et al., Jpn. J. Appl. Phys., Vol. 37, p. 4454-4459 (1998).
  • the SrO buffer layer was thick (100 A), thereby limiting application for transistor films, and crystallinity was not maintained throughout the growth.
  • SrTi0 3 has been grown on silicon using thick oxide layers (60- 120 A) of SrO or TiO. See, e.g., B.K. Moon et al., Jpn. J. Appl. Phys., Vol. 33, p. 1472-1477 (1994). These thick buffer layers, however, would limit the application for transistors.
  • these types of oxide layers are fabricated using molecular oxygen and are formed thin ⁇ i.e., less than 50 A). Accordingly, a result is leaky films in which high electrical leakage is experienced due to oxygen deficiencies or vacancies. Furthermore, these films require a post-growth anneal in oxygen to reduce leakage current density across the oxide layer.
  • FIG. 1 illustrates schematically, in cross section, a semiconductor structure fabricated in accordance with one embodiment of the present invention
  • FIG. 2 illustrates schematically, in cross section, a semiconductor device structure fabricated in accordance with an alternative embodiment of the present invention
  • FIG. 3 illustrates schematically, in cross section, a structure in accordance with a further embodiment of the present invention
  • FIG. 4 illustrates schematically, in cross section, a semiconductor device structure fabricated in accordance with yet a further embodiment of the present invention
  • FIG. 5 illustrates schematically, in cross section, a semiconductor device structure fabricated in accordance with another embodiment of the present invention
  • the following example illustrates a process, in accordance with one embodiment of the invention, for fabricating such a semiconductor structure having a low leakage current density.
  • the process starts by providing a monocrystalline semiconductor substrate comprising, for example, silicon and/or germanium.
  • the semiconductor substrate is a silicon wafer having a (100) orientation.
  • the substrate may be oriented on axis or, at most, about 0.5° off axis.
  • At least a portion of the semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures.
  • the term "bare" in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material.
  • bare silicon is highly reactive and readily forms a native oxide.
  • the term "bare" is intended to encompass such a native oxide.
  • a thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process in accordance with the invention.
  • the native oxide layer is first removed to expose the crystalline structure of the underlying substrate. The following process is generally carried out by molecular beam epitaxy (MBE), although other processes, such as those outlined below, may also be used in accordance with the present invention.
  • MBE molecular beam epitaxy
  • the native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus.
  • strontium the substrate is then heated to a temperature of about 750° C to cause the strontium to react with the native silicon oxide layer.
  • the strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface.
  • the resultant surface which exhibits an ordered 2x1 structure, includes strontium, oxygen, and silicon.
  • the ordered 2x1 structure forms a template for the ordered growth of an overlying layer of a monocrystalline oxide.
  • the template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer.
  • the native silicon oxide can be converted and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkali earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 750°C. At this temperature a solid state reaction takes place between the strontium oxide and the native silicon oxide causing the reduction of the native silicon oxide and leaving an ordered 2x1 structure with strontium, oxygen, and silicon remaining on the substrate surface.
  • an alkali earth metal oxide such as strontium oxide, strontium barium oxide, or barium oxide
  • the substrate is cooled to a temperature in the range of about 200-800°C and a layer of strontium titanate is grown on the template layer by molecular beam epitaxy.
  • the MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources.
  • the ratio of strontium and titanium is approximately 1:1.
  • the partial pressure of oxygen is initially set at a minimum value to grow stoichiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value.
  • the process described above illustrates a process for forming a semiconductor structure including a silicon substrate and an overlying oxide layer by the process of molecular beam epitaxy.
  • the process can also be carried out by the process of chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), migration enhanced epitaxy (MEE), atomic layer epitaxy (ALE), physical vapor deposition (PVD), chemical solution deposition (CSD), pulsed laser deposition (PLD), or the like.
  • CVD chemical vapor deposition
  • MOCVD metal organic chemical vapor deposition
  • MEE migration enhanced epitaxy
  • ALE atomic layer epitaxy
  • PVD physical vapor deposition
  • CSSD chemical solution deposition
  • PLD pulsed laser deposition
  • alkaline earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown.
  • FIG. 1 illustrates schematically, in cross section, a structure 100 in accordance with one embodiment of the present invention.
  • Structure 100 may be a device such as, for example, a gate dielectric component for a MOS device or any high dielectric constant device.
  • Structure 100 includes a monocrystalline semiconductor substrate 101.
  • Substrate 101 may comprise any suitable monocrystalline semiconductor material, such as, for example, silicon (Si), germanium (Ge), silicon germanium (Si-Ge), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAIAs), aluminum gallium arsenide (AIGaAs), and indium gallium phosphide (InGaP).
  • substrate 101 comprises a monocrystalline silicon wafer.
  • a monocrystalline oxide layer 103 is formed overlying substrate 101.
  • monocrystalline oxide layer 103 is a monocrystalline oxide material selected for its crystalline compatibility with the underlying substrate and with the overlying compound semiconductor material in this embodiment, iayer 103 may comprise, for example, stoichiometric alkali earth metal titanate, such as barium titanate (BaTiOs), strontium titanate (SrTi0 3 ), or barium strontium titanate (Sr z Ba ⁇ - z Ti ⁇ 3, 0 ⁇ z ⁇ 1).
  • a stoichiometric alkali earth metal titanate is achieved where the ratio of alkali earth metal to titanium is 1 :1.
  • layer 103 is a layer of stoichiometric SrTi0 3 having a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers.
  • monocrystalline oxide layer 104 is formed overlying layer 103.
  • monocrystalline oxide layer 104 is a monocrystalline oxide material selected for its crystalline compatibility with layer 103.
  • layer 104 may comprise, for example, non-stoichiometric alkali earth metal titanate, such as barium titanate, strontium titanate, or barium strontium titanate.
  • a non- stoichiometric alkali earth metal titanate is achieved where the ratio of alkali earth metal to titanium is greater than 1 :1 , and may be achieved by establishing different flux rates for the alkali earth metal and titanium during formation of the alkali earth metal titanate layer.
  • a non-stoichiometric alkali earth metal titanate will be formed having a ratio of alkali earth metal to titanium greater than 1 :1.
  • the ratio of alkali earth metal to titanium is less than or equal to about 1.8:1.
  • layer 104 is a layer of non-stoichiometric SrTi0 3 and can have a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers.
  • the combined equivalent oxide thickness of layer 103 and 104 is less than or equal to about 1.5 nm.
  • a third monocrystalline oxide layer 105 is formed overlying layer 104.
  • Layer 105 may comprise, for example, stoichiometric alkali earth metal titanate, such as barium titanate (BaTi0 3 ), strontium titanate (SrTi0 3 ), or barium strontium titanate (Sr z Ba ⁇ - z Ti0 3 , 0 ⁇ z ⁇ 1).
  • layer 105 is a layer of stoichiometric SrTi0 3 and can have a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers.
  • a conductive gate electrode (not shown) may be formed on layer 105 in accordance with techniques well known to those skilled in the art.
  • FIG. 2 illustrates schematically, in cross section, a semiconductor device structure 200 in accordance with another embodiment of the present invention.
  • Device structure 200 may be a device such as, for example, a MOS device or any high dielectric constant device.
  • Structure 200 includes a monocrystalline semiconductor substrate 201 , preferably a monocrystalline silicon wafer.
  • a monocrystalline oxide layer 203 is formed overlying substrate 201.
  • Monocrystalline oxide layer 203 is preferably a monocrystalline oxide material selected for its crystalline compatibility with the underlying substrate and with the overlying compound semiconductor material.
  • layer 203 may comprise, for example, non-stoichiometric alkali earth metal titanate, such as barium titanate (Ba x Ti 1 - x 0 3 ), strontium titanate (Sr x Ti ⁇ - 0 3 ), or barium strontium titanate ((SrzBa ⁇ xTi ⁇ Os, 0 ⁇ x ⁇ 1 , 0 ⁇ z ⁇ 1).
  • layer 203 is a layer of non- stoichio etric SrTi0 3 and can have a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers.
  • An additional monocrystalline oxide layer 204 is formed overlying layer 203.
  • Monocrystalline oxide layer 204 is preferably a monocrystalline oxide material selected for its crystalline compatibility with layer 203.
  • layer 204 may comprise, for example, stoichiometric alkali earth metal titanate, such as barium titanate, strontium titanate, or barium strontium titanate.
  • layer 204 is a layer of stoichiometric SrTi0 3 and can have a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers. In one aspect of this embodiment, layers 203 and 204 have a combined equivalent oxide thickness of less than or equal to about 1.5 nm.
  • layers 203 and 204 collectively comprise a gate dielectric for a high dielectric constant semiconductor device, such as a MOS device.
  • a conductive gate electrode 205 may be formed on layer 204 in accordance with techniques well known to those skilled in the art to complete the device structure. Processing may then continue in accordance with standard processing techniques to form a substantially complete integrated circuit incorporating a device structure of the present invention, such as that illustrated in FIG. 2.
  • FIG. 3 illustrates schematically, in cross section, a structure 300 in accordance with a further embodiment of the present invention.
  • Structure 300 may be a structure such as, for example, a gate dielectric component for a MOS device or any high dielectric constant device.
  • Structure 300 includes a monocrystalline semiconductor substrate 301 , preferably a monocrystalline silicon wafer.
  • a monocrystalline oxide layer 302 is formed overlying substrate 301.
  • monocrystalline oxide layer 302 is a monocrystalline oxide material selected for its crystalline compatibility with the underlying substrate and with the overlying compound semiconductor material.
  • layer 302 may comprise, for example, non-stoichiometric alkali earth metal titanate, such as barium titanate (Ba x Ti ⁇ - x 0 3 ), strontium titanate (Sr x Ti ⁇ - x 0 3 ), or barium strontium titanate ((Sr z Ba 1 - z ) ⁇ Ti ⁇ - x 0 3 , 0 ⁇ x ⁇ 1 , 0 ⁇ z ⁇ 1).
  • An additional monocrystalline oxide layer 303 is formed overlying layer 302.
  • Monocrystalline oxide layer 303 is preferably a monocrystalline oxide material selected for its crystalline compatibility with layer 302.
  • layer 303 may comprise, for example, stoichiometric alkali earth metal titanate, such as barium titanate, strontium titanate, or barium strontium titanate.
  • a plurality of alternating layers of non-stoichiometric alkali earth metal titanate and stoichiometric alkali earth metal titanate are formed overlying layer 303.
  • the stoichiometric/non-stoichiometric nature of layers 302, 303, and additional layers is not critical, so long as the layers alternate between non-stoichiometric and stoichiometric as the structure is formed.
  • a stoichiometric alkali earth metal titanate layer not be formed overlying another stoichiometric alkali earth metal titanate layer, and that a non-stoichiometric alkali earth metal titanate layer not be formed overlying another non-stoichiometric alkali earth metal titanate layer.
  • a third monocrystalline oxide layer 304 is formed overlying layer 303.
  • Layer 304 may comprise, for example, a non-stoichiometric alkali earth metal titanate.
  • a fourth monocrystalline oxide layer 305 is formed overlying layer 304.
  • Layer 305 may comprise, for example, a stoichiometric alkali earth metal titanate.
  • FIG. 4 illustrates schematically, in cross section, a semiconductor device structure 400 fabricated in accordance with one alternative embodiment of the present invention, wherein semiconductor device structure 400 comprises a MOS device.
  • Structure 400 includes a monocrystalline semiconductor substrate 401 , preferably a monocrystalline silicon wafer. Drain region 402 and source region 403 are formed in substrate 401 using techniques well known to those skilled in the art, such as, for example, ion implantation.
  • a channel region 408 is defined by drain region 402 and source region 403 as the portion of substrate 401 between regions 402 and 403.
  • a monocrystalline oxide layer 404 is formed overlying substrate 401 adjacent channel region 408.
  • Layer 404 is preferably a monocrystalline oxide material selected for its crystalline compatibility with the underlying substrate and with any overlying compound semiconductor material.
  • layer 404 may comprise, for example, stoichiometric alkali earth metal titanate, such as barium titanate (BaTi0 3 ), strontium titanate (SrTi0 3 ), or barium strontium titanate (Sr z Ba- ⁇ - z Ti0 3 , 0 ⁇ x ⁇ 1 , 0 ⁇ z ⁇ 1).
  • layer 404 is a layer of stoichiometric SrTi0 3 having a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers.
  • a second monocrystalline oxide layer 405 is formed overlying layer 404.
  • Layer 405 is preferably a monocrystalline oxide material selected for its crystalline compatibility with layer 404.
  • layer 405 may comprise, for example, non-stoichiometric alkali earth metal titanate, such as barium titanate, strontium titanate, or barium strontium titanate.
  • layer 405 is a layer of non-stoichiometric Sr x Ti ⁇ - x 0 3 , with 0 ⁇ x ⁇ 1 , having a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers.
  • a third monocrystalline oxide layer 406 is formed overlying layer 405.
  • Layer 406 may comprise, for example, stoichiometric alkali earth metal titanate, such as barium titanate (BaTi0 3 ), strontium titanate (SrTi0 3 ), or barium strontium titanate (Sr z Ba ⁇ - z Ti0 3 , 0 ⁇ x ⁇ 1, 0 ⁇ z ⁇ 1).
  • layer 406 is a layer of stoichiometric SrTi0 3 having a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers.
  • a conductive gate electrode 407 is then formed on layer 406 in accordance with techniques well known to those skilled in the art to complete the structure of the MOS device.
  • FIG. 5 illustrates schematically, in cross section, a semiconductor device structure 500 fabricated in accordance with a further embodiment of the present invention, wherein semiconductor device structure 500 comprises a MOS device.
  • Structure 500 includes a monocrystalline semiconductor substrate 501 , preferably a monocrystalline silicon wafer. Drain region 502 and source region 503 are formed in substrate 501 using techniques well known to those skilled in the art, such as, for example, ion implantation.
  • a channel region 510 is defined by drain region 502 and source region 503 as a portion of substrate 501 between regions 502 and 503.
  • a monocrystalline oxide layer 504 is formed overlying substrate 501.
  • layer 504 is a monocrystalline oxide material selected for its crystalline compatibility with the underlying substrate and with an overlying compound semiconductor material layer 505.
  • layer 504 may comprise, for example, an alkali earth metal titanate, an alkali earth metal hafnate, or an alkali earth metal zirconate.
  • layer 504 is a layer of (Ba,Sr)Ti0 3 having a thickness of about 2 - 10 monolayers.
  • Compound semiconductor layer 505 may comprise, for example, silicon germanium (Si-Ge), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAIAs), aluminum gallium arsenide (AIGaAs), or indium gallium phosphide (InGaP).
  • Si-Ge silicon germanium
  • GaAs gallium arsenide
  • InGaAs indium gallium arsenide
  • InAIAs indium aluminum arsenide
  • AIGaAs aluminum gallium arsenide
  • InGaP indium gallium phosphide
  • a monocrystalline oxide layer 506 is then formed overlying layer 505 and channel region 510.
  • Layer 506 is preferably a monocrystalline oxide material selected for its crystalline compatibility with layer 505.
  • layer 506 may comprise, for example, stoichiometric alkali earth metal titanate, such as barium titanate, strontium titanate, or barium strontium titanate.
  • layer 506 is a layer of stoichiometric SrTi0 3 having a thickness of about 5 monolayers.
  • a second monocrystalline oxide layer 507 is formed overlying layer 506.
  • Layer 507 may comprise, for example, a non-stoichiometric alkali earth metal titanate having a ratio of alkali earth metal to titanium of greater than 1 :1. In one embodiment, layer 507 is a layer of non-stoichiometric Sr x Ti- ⁇ - x 0 3 having a thickness of about 5 monolayers. Further, in accordance with this embodiment of the invention, a third monocrystalline oxide layer 508 is formed overlying layer 507. Layer 508 may comprise, for example, a stoichiometric alkali earth metal titanate. In one embodiment, layer 508 is a layer of stoichiometric SrTi0 3 having a thickness of about 5 monolayers.
  • layers 506, 507 and 508 exhibit a bandgap of greater than about 3.2 eV.
  • a conductive gate electrode 509 is then formed on layer 508 in accordance with techniques well known to those skilled in the art to complete the structure of the MOS device.
  • various layers of the semiconductor device may be formed using a variety of growth deposition methods, including, but not limited to molecular beam epitaxy (MBE), chemical beam epitaxy (CBE), metal-organic molecular beam epitaxy (MOMBE), ultra-high vacuum chemical vapor deposition (UHVCVD), physical vapor deposition (PVD), metal-organic chemical vapor deposition (MOCVD) or the like.
  • MBE molecular beam epitaxy
  • CBE chemical beam epitaxy
  • MOMBE metal-organic molecular beam epitaxy
  • UHVCVD ultra-high vacuum chemical vapor deposition
  • PVD physical vapor deposition
  • MOCVD metal-organic chemical vapor deposition

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Abstract

A semiconductor structure (400) and method for forming a semiconductor structure including a high dielectric constant material includes a monocrystalline semiconductor substrate (401), one or more layers of a stoichiometric monocrystalline, high dielectric constant material (404), and one or more layers of a non-stoichiometric, high dielectric constant material (405). The high dielectric constant material may include a monocrystalline alkali earth metal titanate, such as (Ba,Sr)TiO3. Semiconductor devices fabricated in accordance with the present invention exhibit reduced leakage current density.

Description

SE ICONDUCTOR STRUCTURE HAVING HIGH DIELECTRIC CONSTANT MATERIAL
FIELD OF THE INVENTION
This invention relates generally to semiconductor structures and devices and to a method for their fabrication, and more specifically to semiconductor structures and devices and to the fabrication and use of semiconductor structures, devices, and integrated circuits that include a non-stoichiometric, high dielectric constant oxide to reduce leakage current density.
BACKGROUND OF THE INVENTION
Epitaxial growth of single crystal oxide thin films on silicon is of great interest in numerous device applications, such as, for example, ferroelectric devices, nonvolatile high density memory devices, and next-generation MOS devices. Also, in the preparation of these films, it is pivotal to establish an ordered transition layer or buffer layer on the silicon surface for the subsequent growth of the single crystal oxides, such as, for example, perovskites. Some of these oxides, such as BaO and BaTi03, were formed on silicon
(100) using a BaSi2 (cubic) template by depositing one fourth monolayer of Ba on silicon (100) using molecular beam epitaxy at temperatures greater than 850°C. See, e.g., R. McKee et al., Appl. Phys. Lett. 59(7), p. 782-784 (12 Aug. 1991); R. McKee et al., Appl. Phys. Lett. 63(20), p. 2818-2820 (15 Nov. 1993); R. McKee et al., Mat. Res. Soc. Symp. Proc, Vol. 21 , p. 131-135 (1991); U.S. Patent No.
5,225,031 , issued July 6, 1993, entitled "PROCESS FOR DEPOSITING AN OXIDE EPITAXIALLY ONTO A SILICON SUBSTRATE AND STRUCTURES PREPARED WITH THE PROCESS"; and U.S. Patent No. 5,482,003, issued January 9, 1996, entitled "PROCESS FOR DEPOSITING EPITAXIAL ALKALINE EARTH OXIDE ONTO A SUBSTRATE AND STRUCTURES PREPARED WITH THE PROCESS." A strontium suicide (SrSi2) interface model with a c(4x2) structure was proposed. See, e.g., R. McKee et al., Phys. Rev. Lett. 81 (14), 3014 (5 Oct. 1998). Atomic level simulation of this proposed structure, however, indicates that it likely is not stable at elevated temperatures.
Growth of SrTi03 on silicon (100) using an SrO buffer layer has been accomplished. See, e.g., T. Tambo et al., Jpn. J. Appl. Phys., Vol. 37, p. 4454-4459 (1998). However, the SrO buffer layer was thick (100 A), thereby limiting application for transistor films, and crystallinity was not maintained throughout the growth.
Furthermore, SrTi03 has been grown on silicon using thick oxide layers (60- 120 A) of SrO or TiO. See, e.g., B.K. Moon et al., Jpn. J. Appl. Phys., Vol. 33, p. 1472-1477 (1994). These thick buffer layers, however, would limit the application for transistors.
In CMOS applications, these types of oxide layers are fabricated using molecular oxygen and are formed thin {i.e., less than 50 A). Accordingly, a result is leaky films in which high electrical leakage is experienced due to oxygen deficiencies or vacancies. Furthermore, these films require a post-growth anneal in oxygen to reduce leakage current density across the oxide layer.
Accordingly, a need exists for a method for fabricating a high dielectric constant oxide on a semiconductor structure having low leakage current density.
It is a purpose of the present invention to provide for a method of fabricating a high dielectric constant semiconductor device structure using a non-stoichiometric alkali earth metal titanate, thus reducing leakage current density.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and in which:
FIG. 1 illustrates schematically, in cross section, a semiconductor structure fabricated in accordance with one embodiment of the present invention;
FIG. 2 illustrates schematically, in cross section, a semiconductor device structure fabricated in accordance with an alternative embodiment of the present invention;
FIG. 3 illustrates schematically, in cross section, a structure in accordance with a further embodiment of the present invention; FIG. 4 illustrates schematically, in cross section, a semiconductor device structure fabricated in accordance with yet a further embodiment of the present invention;
FIG. 5 illustrates schematically, in cross section, a semiconductor device structure fabricated in accordance with another embodiment of the present invention;
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.
DETAILED DESCRIPTION OF THE DRAWINGS
The following example illustrates a process, in accordance with one embodiment of the invention, for fabricating such a semiconductor structure having a low leakage current density. The process starts by providing a monocrystalline semiconductor substrate comprising, for example, silicon and/or germanium. In accordance with one embodiment of the invention, the semiconductor substrate is a silicon wafer having a (100) orientation. The substrate may be oriented on axis or, at most, about 0.5° off axis. At least a portion of the semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures. The term "bare" in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material. As is well known, bare silicon is highly reactive and readily forms a native oxide. The term "bare" is intended to encompass such a native oxide. A thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process in accordance with the invention. In order to epitaxially grow a monocrystalline oxide layer overlying the monocrystalline substrate, the native oxide layer is first removed to expose the crystalline structure of the underlying substrate. The following process is generally carried out by molecular beam epitaxy (MBE), although other processes, such as those outlined below, may also be used in accordance with the present invention. The native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus. In the case where strontium is used, the substrate is then heated to a temperature of about 750° C to cause the strontium to react with the native silicon oxide layer. The strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface. The resultant surface, which exhibits an ordered 2x1 structure, includes strontium, oxygen, and silicon. The ordered 2x1 structure forms a template for the ordered growth of an overlying layer of a monocrystalline oxide. The template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer.
In accordance with an alternate embodiment of the invention, the native silicon oxide can be converted and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkali earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 750°C. At this temperature a solid state reaction takes place between the strontium oxide and the native silicon oxide causing the reduction of the native silicon oxide and leaving an ordered 2x1 structure with strontium, oxygen, and silicon remaining on the substrate surface.
Following the removal of the silicon oxide from the surface of the substrate, in accordance with one embodiment of the invention, the substrate is cooled to a temperature in the range of about 200-800°C and a layer of strontium titanate is grown on the template layer by molecular beam epitaxy. The MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources. The ratio of strontium and titanium is approximately 1:1. The partial pressure of oxygen is initially set at a minimum value to grow stoichiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value.
The process described above illustrates a process for forming a semiconductor structure including a silicon substrate and an overlying oxide layer by the process of molecular beam epitaxy. The process can also be carried out by the process of chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), migration enhanced epitaxy (MEE), atomic layer epitaxy (ALE), physical vapor deposition (PVD), chemical solution deposition (CSD), pulsed laser deposition (PLD), or the like. Further, by a similar process, other monocrystalline such as alkaline earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates, peroskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown.
FIG. 1 illustrates schematically, in cross section, a structure 100 in accordance with one embodiment of the present invention. Structure 100 may be a device such as, for example, a gate dielectric component for a MOS device or any high dielectric constant device. Structure 100 includes a monocrystalline semiconductor substrate 101. Substrate 101 may comprise any suitable monocrystalline semiconductor material, such as, for example, silicon (Si), germanium (Ge), silicon germanium (Si-Ge), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAIAs), aluminum gallium arsenide (AIGaAs), and indium gallium phosphide (InGaP). Preferably, substrate 101 comprises a monocrystalline silicon wafer.
A monocrystalline oxide layer 103 is formed overlying substrate 101. In one embodiment, monocrystalline oxide layer 103 is a monocrystalline oxide material selected for its crystalline compatibility with the underlying substrate and with the overlying compound semiconductor material in this embodiment, iayer 103 may comprise, for example, stoichiometric alkali earth metal titanate, such as barium titanate (BaTiOs), strontium titanate (SrTi03), or barium strontium titanate (SrzBaι- zTiθ3, 0<z<1). A stoichiometric alkali earth metal titanate is achieved where the ratio of alkali earth metal to titanium is 1 :1. In one embodiment, layer 103 is a layer of stoichiometric SrTi03 having a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers.
An additional monocrystalline oxide layer 104 is formed overlying layer 103. In one embodiment, monocrystalline oxide layer 104 is a monocrystalline oxide material selected for its crystalline compatibility with layer 103. In this embodiment, layer 104 may comprise, for example, non-stoichiometric alkali earth metal titanate, such as barium titanate, strontium titanate, or barium strontium titanate. A non- stoichiometric alkali earth metal titanate is achieved where the ratio of alkali earth metal to titanium is greater than 1 :1 , and may be achieved by establishing different flux rates for the alkali earth metal and titanium during formation of the alkali earth metal titanate layer. For example, if the flux rate for the alkali earth metal is greater than the flux rate for the titanium, a non-stoichiometric alkali earth metal titanate will be formed having a ratio of alkali earth metal to titanium greater than 1 :1. Preferably, the ratio of alkali earth metal to titanium is less than or equal to about 1.8:1. In one embodiment, layer 104 is a layer of non-stoichiometric SrTi03 and can have a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers. Preferably, the combined equivalent oxide thickness of layer 103 and 104 is less than or equal to about 1.5 nm.
In accordance with this embodiment of the invention, a third monocrystalline oxide layer 105 is formed overlying layer 104. Layer 105 may comprise, for example, stoichiometric alkali earth metal titanate, such as barium titanate (BaTi03), strontium titanate (SrTi03), or barium strontium titanate (SrzBaι-zTi03, 0<z<1). In one embodiment layer 105 is a layer of stoichiometric SrTi03 and can have a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers. If structure 100 comprises a gate dielectric for a high dielectric constant semiconductor device, a conductive gate electrode (not shown) may be formed on layer 105 in accordance with techniques well known to those skilled in the art.
FIG. 2 illustrates schematically, in cross section, a semiconductor device structure 200 in accordance with another embodiment of the present invention. Device structure 200 may be a device such as, for example, a MOS device or any high dielectric constant device. Structure 200 includes a monocrystalline semiconductor substrate 201 , preferably a monocrystalline silicon wafer.
A monocrystalline oxide layer 203 is formed overlying substrate 201. Monocrystalline oxide layer 203 is preferably a monocrystalline oxide material selected for its crystalline compatibility with the underlying substrate and with the overlying compound semiconductor material. In this embodiment, layer 203 may comprise, for example, non-stoichiometric alkali earth metal titanate, such as barium titanate (BaxTi1-x03), strontium titanate (SrxTiι- 03), or barium strontium titanate ((SrzBa^xTi^Os, 0<x<1 , 0<z<1). In one embodiment, layer 203 is a layer of non- stoichio etric SrTi03 and can have a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers. An additional monocrystalline oxide layer 204 is formed overlying layer 203. Monocrystalline oxide layer 204 is preferably a monocrystalline oxide material selected for its crystalline compatibility with layer 203. In this embodiment, layer 204 may comprise, for example, stoichiometric alkali earth metal titanate, such as barium titanate, strontium titanate, or barium strontium titanate. In one embodiment, layer 204 is a layer of stoichiometric SrTi03and can have a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers. In one aspect of this embodiment, layers 203 and 204 have a combined equivalent oxide thickness of less than or equal to about 1.5 nm.
In this embodiment, layers 203 and 204 collectively comprise a gate dielectric for a high dielectric constant semiconductor device, such as a MOS device. A conductive gate electrode 205 may be formed on layer 204 in accordance with techniques well known to those skilled in the art to complete the device structure. Processing may then continue in accordance with standard processing techniques to form a substantially complete integrated circuit incorporating a device structure of the present invention, such as that illustrated in FIG. 2.
FIG. 3 illustrates schematically, in cross section, a structure 300 in accordance with a further embodiment of the present invention. Structure 300 may be a structure such as, for example, a gate dielectric component for a MOS device or any high dielectric constant device. Structure 300 includes a monocrystalline semiconductor substrate 301 , preferably a monocrystalline silicon wafer.
A monocrystalline oxide layer 302 is formed overlying substrate 301. In one embodiment, monocrystalline oxide layer 302 is a monocrystalline oxide material selected for its crystalline compatibility with the underlying substrate and with the overlying compound semiconductor material. In this embodiment, layer 302 may comprise, for example, non-stoichiometric alkali earth metal titanate, such as barium titanate (BaxTiι-x03), strontium titanate (SrxTiι-x03), or barium strontium titanate ((SrzBa1-z)χTiι-x03, 0<x<1 , 0<z<1). An additional monocrystalline oxide layer 303 is formed overlying layer 302. Monocrystalline oxide layer 303 is preferably a monocrystalline oxide material selected for its crystalline compatibility with layer 302. In this embodiment, layer 303 may comprise, for example, stoichiometric alkali earth metal titanate, such as barium titanate, strontium titanate, or barium strontium titanate.
In accordance with this embodiment of the invention, a plurality of alternating layers of non-stoichiometric alkali earth metal titanate and stoichiometric alkali earth metal titanate are formed overlying layer 303. The stoichiometric/non-stoichiometric nature of layers 302, 303, and additional layers is not critical, so long as the layers alternate between non-stoichiometric and stoichiometric as the structure is formed. That is, it is generally preferred that a stoichiometric alkali earth metal titanate layer not be formed overlying another stoichiometric alkali earth metal titanate layer, and that a non-stoichiometric alkali earth metal titanate layer not be formed overlying another non-stoichiometric alkali earth metal titanate layer. As illustrated in FIG. 3, a third monocrystalline oxide layer 304 is formed overlying layer 303. Layer 304 may comprise, for example, a non-stoichiometric alkali earth metal titanate. Finally, a fourth monocrystalline oxide layer 305 is formed overlying layer 304. Layer 305 may comprise, for example, a stoichiometric alkali earth metal titanate. In this preferred embodiment, layers 302, 303, 304, and 305 collectively comprise a gate dielectric for a high dielectric constant semiconductor device, such as a MOS device. In one aspect of this embodiment, each of the plurality of alternating monocrystalline oxide layers has a thickness of about 1 - 2 nm. FIG. 4 illustrates schematically, in cross section, a semiconductor device structure 400 fabricated in accordance with one alternative embodiment of the present invention, wherein semiconductor device structure 400 comprises a MOS device. Structure 400 includes a monocrystalline semiconductor substrate 401 , preferably a monocrystalline silicon wafer. Drain region 402 and source region 403 are formed in substrate 401 using techniques well known to those skilled in the art, such as, for example, ion implantation. A channel region 408 is defined by drain region 402 and source region 403 as the portion of substrate 401 between regions 402 and 403.
A monocrystalline oxide layer 404 is formed overlying substrate 401 adjacent channel region 408. Layer 404 is preferably a monocrystalline oxide material selected for its crystalline compatibility with the underlying substrate and with any overlying compound semiconductor material. In this embodiment, layer 404 may comprise, for example, stoichiometric alkali earth metal titanate, such as barium titanate (BaTi03), strontium titanate (SrTi03), or barium strontium titanate (SrzBa-ι- zTi03, 0<x<1 , 0<z<1). In one embodiment, layer 404 is a layer of stoichiometric SrTi03 having a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers. In this embodiment, a second monocrystalline oxide layer 405 is formed overlying layer 404. Layer 405 is preferably a monocrystalline oxide material selected for its crystalline compatibility with layer 404. In the illustrated embodiment, layer 405 may comprise, for example, non-stoichiometric alkali earth metal titanate, such as barium titanate, strontium titanate, or barium strontium titanate. In one embodiment, layer 405 is a layer of non-stoichiometric SrxTiι-x03 , with 0<x<1 , having a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers.
In accordance with this embodiment of the invention, a third monocrystalline oxide layer 406 is formed overlying layer 405. Layer 406 may comprise, for example, stoichiometric alkali earth metal titanate, such as barium titanate (BaTi03), strontium titanate (SrTi03), or barium strontium titanate (SrzBaι-zTi03, 0<x<1, 0<z<1). In this embodiment, layer 406 is a layer of stoichiometric SrTi03 having a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers. A conductive gate electrode 407 is then formed on layer 406 in accordance with techniques well known to those skilled in the art to complete the structure of the MOS device.
FIG. 5 illustrates schematically, in cross section, a semiconductor device structure 500 fabricated in accordance with a further embodiment of the present invention, wherein semiconductor device structure 500 comprises a MOS device. Structure 500 includes a monocrystalline semiconductor substrate 501 , preferably a monocrystalline silicon wafer. Drain region 502 and source region 503 are formed in substrate 501 using techniques well known to those skilled in the art, such as, for example, ion implantation. A channel region 510 is defined by drain region 502 and source region 503 as a portion of substrate 501 between regions 502 and 503. A monocrystalline oxide layer 504 is formed overlying substrate 501. In one embodiment, layer 504 is a monocrystalline oxide material selected for its crystalline compatibility with the underlying substrate and with an overlying compound semiconductor material layer 505. In this embodiment, layer 504 may comprise, for example, an alkali earth metal titanate, an alkali earth metal hafnate, or an alkali earth metal zirconate. In an exemplary embodiment, layer 504 is a layer of (Ba,Sr)Ti03 having a thickness of about 2 - 10 monolayers. Compound semiconductor layer 505 may comprise, for example, silicon germanium (Si-Ge), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAIAs), aluminum gallium arsenide (AIGaAs), or indium gallium phosphide (InGaP).
A monocrystalline oxide layer 506 is then formed overlying layer 505 and channel region 510. Layer 506 is preferably a monocrystalline oxide material selected for its crystalline compatibility with layer 505. In the illustrated embodiment, layer 506 may comprise, for example, stoichiometric alkali earth metal titanate, such as barium titanate, strontium titanate, or barium strontium titanate. In one embodiment, layer 506 is a layer of stoichiometric SrTi03 having a thickness of about 5 monolayers. In accordance with this embodiment of the invention, a second monocrystalline oxide layer 507 is formed overlying layer 506. Layer 507 may comprise, for example, a non-stoichiometric alkali earth metal titanate having a ratio of alkali earth metal to titanium of greater than 1 :1. In one embodiment, layer 507 is a layer of non-stoichiometric SrxTi-ι-x03 having a thickness of about 5 monolayers. Further, in accordance with this embodiment of the invention, a third monocrystalline oxide layer 508 is formed overlying layer 507. Layer 508 may comprise, for example, a stoichiometric alkali earth metal titanate. In one embodiment, layer 508 is a layer of stoichiometric SrTi03 having a thickness of about 5 monolayers. Collectively, in accordance with one aspect of this embodiment, layers 506, 507 and 508 exhibit a bandgap of greater than about 3.2 eV. A conductive gate electrode 509 is then formed on layer 508 in accordance with techniques well known to those skilled in the art to complete the structure of the MOS device.
Accordingly, disclosed is a method for fabricating a high dielectric constant semiconductor device having decreased leakage current density. As disclosed, various layers of the semiconductor device may be formed using a variety of growth deposition methods, including, but not limited to molecular beam epitaxy (MBE), chemical beam epitaxy (CBE), metal-organic molecular beam epitaxy (MOMBE), ultra-high vacuum chemical vapor deposition (UHVCVD), physical vapor deposition (PVD), metal-organic chemical vapor deposition (MOCVD) or the like. In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Further, no element described herein is essential to the practice of the invention unless expressly described as "essential" or " required.

Claims

1. A high dielectric constant device structure comprising: a monocrystalline semiconductor substrate having a surface; a first layer of stoichiometric monocrystalline alkali earth metal titanate overlying the surface; and a second layer of non-stoichiometric monocrystalline alkali earth metal titanate overlying the surface.
2. The structure of claim 1 wherein the second layer comprises a material having a ratio of alkali earth metal to titanium greater than 1:1.
3. The structure of claim 2 wherein the first layer comprises an alkali earth metal selected from the group consisting of barium, strontium, and barium and strontium.
4. The structure of claim 2 wherein the second layer comprises an alkali earth metal selected from the group consisting of barium, strontium, and barium and strontium.
The structure of claim 4 wherein the ratio is less than or equal to 1.8:1 ,
6. The structure of claim 1 wherein the first layer and the second layer have a combined equivalent silicon dioxide thickness less than or equal to about 1.5 nm.
7. The structure of claim 1 wherein the semiconductor substrate comprises a semiconductor material selected from the group consisting of Si, Ge, Si-Ge, GaAs, InP, and SiC.
8. The structure of claim 1 further comprising a semiconductor device structure formed at least partially in the substrate.
9. The structure of claim 8 wherein the first layer and the second layer collectively form a gate dielectric of the semiconductor device structure.
10. The structure of claim 9 further comprising a conductive gate electrode overlying the gate dielectric.
11. The structure of claim 1 wherein the second layer is formed overlying the first layer.
12. The structure of claim 14 further comprising a third layer of stoichiometric monocrystalline alkali earth metal titanate overlying the second layer.
13. The structure of claim 1 wherein the first layer is formed overlying the second layer.
14. A high dielectric constant device structure comprising: a monocrystalline semiconductor substrate; a plurality of alternating layers of stoichiometric monocrystalline alkali earth metal titanate and non-stoichiometric monocrystalline alkali earth metal titanate overlying the substrate.
15. The structure of claim 14 wherein each of the plurality of alternating layers comprises (Ba,Sr)Ti03.
16. The structure of claim 15 wherein the layers of non-stoichiometric monocrystalline alkali earth metal titanate comprise a material having a ratio of barium or strontium or barium and strontium to titanium greater than 1:1.
17. The structure of claim 15 wherein each of the plurality of alternating layers has a thickness of about 1-2 nm.
18. A semiconductor device structure comprising: a monocrystalline semiconductor substrate; spaced apart source and drain regions formed in the substrate and defining a channel region therebetween; a first layer of monocrystalline non-stoichiometric (Ba,Sr)Ti03 overlying the channel region; and a conductive gate electrode overlying the first layer and the channel region.
19. The device structure of claim 18 further comprising a second layer of monocrystalline stoichiometric (Ba,Sr)Ti03 overlying the channel region.
20. The device structure of claim 19 wherein the second layer overlies the first layer.
21. The device structure of claim 20 further comprising a third layer of monocrystalline stoichiometric (Ba,Sr)Ti03 underlying the first layer.
22. The device structure of claim 19 wherein the substrate comprises a material selected from the group consisting of Si, Ge, Si-Ge, GaAs, SiC, and InP.
23. The device structure of claim 19 wherein the substrate comprises a monocrystalline layer of compound semiconductor material selected from the group consisting of GaAs, InGaAs, InAIAs, AIGaAs, and InGaP overlying a bulk monocrystalline substrate comprising a material selected from the group consisting of Si, Ge, Si-Ge, GaAs, InP, and SiC.
24. The device structure of claim 23 further comprising a monocrystalline layer of oxide underlying the monocrystalline layer of compound semiconductor material.
25. A semiconductor device structure comprising: a monocrystalline semiconductor substrate; a semiconductor device formed at least partially in the substrate; and a monocrystalline layer of (Ba,Sr)Ti03 having a band gap greater than about 3.2eV overlying the semiconductor device.
26. The device structure of claim 25 wherein the monocrystalline layer comprises a layer of non-stoichiometric (Ba,Sr)Ti03 having a ratio of Ba or Sr or Ba and Sr to Ti greater than 1 :1.
27. The device structure of claim 25 wherein the monocrystalline layer comprises a plurality of sublayers at least one of which is non-stoichiometric (Ba,Sr)Tι'03 having a ratio of Ba or Sr or Ba and Sr to Ti greater than 1 :1.
28. A process for fabricating a high dielectric constant device structure comprising the steps of: providing a monocrystalline semiconductor substrate; growing a first layer of monocrystalline alkali earth metal titanate overlying the substrate; and growing a second layer of monocrystalline alkali earth metal titanate overlying the first layer wherein one of the first layer and the second layer comprises a non- stoichiometric alkali earth metal titanate.
29. The process of claim 28 wherein the steps of growing a first layer and growing a second layer each comprise growing by a process selected from the group consisting of molecular beam epitaxy, chemical vapor deposition, metal organic chemical vapor deposition, migration enhanced epitaxy, atomic layer epitaxy, physical vapor deposition, chemical solution deposition, and pulsed laser deposition.
30. The process of claim 28 wherein the steps of growing a first layer and growing a second layer each comprise growing by molecular beam epitaxy.
31. The process of claim 30 wherein one of the steps of growing a first layer and growing a second layer comprises the step of growing a layer of alkali earth metal titanate in which the ratio of alkali earth metal to titanium is greater than 1 :1.
32. The process of claim 31 wherein the step of growing a first layer comprises the step of establishing a first flux of alkali earth metal and a second flux of titanium.
33. The process of claim 32 wherein the step of growing a second layer comprises the step of maintaining the first flux of alkali earth metal and establishing a third flux of titanium different than the second flux.
34. The process of claim 32 wherein the step of growing a second layer comprises the step of maintaining the second flux of titanium and establishing a fourth flux of alkali earth metal different than the first flux.
35. The process of claim 30 wherein the step of growing a second layer comprises terminating the step of growing a first layer before initiating the step of growing a second layer.
36. The process of claim 30 further comprising the step of forming a transition layer comprising 1-2 monolayers between the first layer and the second layer.
37. The process of claim 28 wherein the steps of growing a first layer and growing a second layer each comprises the step of growing a layer comprising (Ba,Sr)Ti03.
38. The process of claim 28 wherein the step of providing a monocrystalline semiconductor substrate comprises the step of providing a substrate comprising a material selected from the group consisting of silicon, germanium, silicon-germanium, and gallium arsenide.
39. The process of claim 28 wherein the step of providing a monocrystalline semiconductor substrate comprises the step of providing a monocrystalline layer of a material selected from the group consisting of GaAs, InGaAs, InAIAs, AIGaAs, and InGaP.
40. A process for fabricating a semiconductor device comprising the steps of: providing a monocrystalline substrate comprising silicon, the substrate having a surface; ion implanting impurity dopant ions to form spaced apart source and drain regions at the surface; molecular beam epitaxially growing a monocrystalline layer comprising (Ba,Sr)Ti03 overlying the surface, the layer comprising a sublayer having a band gap greater than 3.2eV; and forming a conductive electrode overlying the layer and positioned between the source and drain regions.
41. The process of claim 40 wherein the step of molecular beam epitaxially growing comprises growing a first sublayer comprising an alkali earth metal rich (Ba,Sr)Ti03and a second sublayer comprising stoichiometric (Ba,Sr)Ti03 overlying the first sublayer.
42. The process of claim 40 wherein the step of molecular beam epitaxially growing comprises growing a first sublayer comprising stoichiometric (Ba,Sr)Ti03, a second sublayer comprising an alkali earth metal rich (Ba,Sr)Ti03 overlying the first sublayer, and a third sublayer comprising stoichiometric (Ba,Sr)Ti03 overlying the second sublayer.
43. The process of claim 40 wherein the step of molecular beam epitaxially growing comprises growing alternating sublayers of an alkali metal rich (Ba,Sr)Ti03 and stoichiometric (Ba,Sr)Ti03.
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