WO2002009191A2

WO2002009191A2 - Non-volatile memory element

Info

Publication number: WO2002009191A2
Application number: PCT/US2001/022569
Authority: WO
Inventors: Jeffrey M. Finder; Kurt Eisenbeiser; Jerald A. Hallmark
Original assignee: Motorola, Inc.
Priority date: 2000-07-24
Filing date: 2001-07-18
Publication date: 2002-01-31
Also published as: TW503580B; AU2001273553A1; WO2002009191A3

Abstract

High quality epitaxial layers (26) of compound semiconductor materials can be grown overlying large silicon wafers (22) by first growing an accommodating buffer layer (24) on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Utilizing this technique permits (20) the fabrication of thin film non-volatile memory elements on a monocrystalline silicon substrate.

Description

NON-VOLATILE MEMORY ELEMENT ON A MONOCRYSTALLINE SEMICONDUCTOR SUBSTRATE

Field of the Invention This invention relates generally to semiconductor structures and devices and to a method for their fabrication, and more specifically to non-volatile, ferroelectric memory elements and integrated circuits fabricated on a monocrystalline semiconductor material.

Background of the Invention

Various metallic oxides exhibit desirable characteristics such as piezoelectric, ferroelectric, ferromagnetic, colossal magnetic resistance, and super conductivity properties . Such oxides may be included or used in connection with microelectronic devices that take advantage of these characteristics. For example, metallic oxides may be used to form ferroelectric memory devices and the like .

Because of the desirable characteristics of various metallic oxide materials, and because of their present generally high cost and low availability in bulk form, for many years attempts have been made to grow thin films of the desired metallic oxide materials on a foreign substrate. To achieve optimal characteristics of metallic oxide material, however, a monocrystalline film of high crystalline quality is desired. Attempts have been made, for example, to grow layers of a monocrystalline metallic oxide material on substrates such as silicon. These attempts have generally been unsuccessful because lattice mismatches between the host crystal and the grown crystal have caused the resulting thin film of metallic oxide material to be of low crystalline quality. Metallic oxides of higher quality have been grown over oxide substrates such as bulk strontium titanate. Metallic oxides grown over oxide substrates are often expensive because, in part, the oxide substrate is small and expensive .

If a large area thin film of high quality monocrystalline metallic oxide material was available at low cost, a variety of semiconductor devices could advantageously be fabricated using that film at a low cost compared to the cost of fabricating such devices on a bulk wafer of the metallic oxide material or in an epitaxial film of such material on a bulk wafer of oxide material . In addition, if a thin film of high quality monocrystalline metallic oxide material could be realized on a bulk wafer such as a silicon wafer, an integrated device structure could be achieved that took advantage of the best properties of both the silicon and the metallic oxide material.

Accordingly, a need exists for a microelectronic structure that provides a high quality monocrystalline metallic oxide film over another monocrystalline material and for a process for making such a structure. Non-volatile memory elements, for example, those employing field effects transistors (FET) and metal oxide semiconductor field effect transistors (MOSFET) are often fabricated using a monocrystalline thin film layer of a conducting oxide, with a ferroelectric thin film deposited over the conducting oxide. See, for example: S. Mathews, et al . , Ferroelectric field effect transistor based on epitaxial perovskite heterostructures , Science, Vol. 276 (11 April 1997); Ramesh, U.S. Patent No. 5, 270,298 entitled "Cubic Metal Oxide Thin Film Epitaxially Grown on Silicon;" Ramesh, et al . , U.S. Patent No. 5,248,564 entitled "C-Axis Perovskite Thin Films Grown on Silicon Dioxide;" and Inam, et al., U.S. Patent No. 5,155,658 entitled "Crystallographically Aligned Ferroelectric Films Usable in Memories and Method of Crystallographically

Aligning Perovskite Films." The contents of the foregoing are hereby incorporated by reference .

However, prior art techniques have not been able to conveniently fabricate thin film non-volatile memory elements on a monocrystalline silicon substrate, and thereby lack the capability of monolithic integration with logical elements formed in the silicon substrate.

Accordingly, a need exists for a semiconductor structure that provides a high quality ferroelectric film over another monocrystalline material and for a process for making such a structure .

Brief Description of the Drawings

The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and in which:

FIGS. 1 - 3 illustrate schematically, in cross section, device structures in accordance with various embodiments of the invention;

FIG. 4 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch between a host crystal and a grown crystalline overlayer;

FIGS. 5 and 6 illustrate schematically, in cross- section, non-volatile memory elements fabricated on a monocrystalline silicon substrate; FIG. 7 illustrates schematically, in cross-section, a non-volatile memory element fabricated on a silicon substrate illustrating monolithic integration between the memory element and a logic element formed in the silicon substrate;

FIG. 8 illustrates schematically, in cross-section, the structure of FIG. 6, further illustrating a logic element found in the substrate and an interconnect extending from the logic element; FIG. 9 illustrates schematically, in cross-section, a non-volatile memory element fabricated on a silicon substrate, showing the memory element integrated with transistors formed in the silicon substrate;

FIG. 10 illustrates schematically, in cross-section, the structure of FIG. 5 further including a template layer formed over the silicon substrate and a logic element formed in the silicon substrate;

FIG. 11 illustrates schematically, in cross-section, the structure of FIG. 10 showing electrical connection between the logic element in the silicon substrate and the memory element formed on the silicon substrate;

FIG. 12 illustrates schematically, in cross-section, the structure of FIG. 10 with various layers patterned to expose the logic element formed in the silicon substrate; FIG. 13 illustrates schematically, in cross-section, a memory element formed on a monocrystalline silicon substrate, illustrating logical devices built in the substrate and a metal layer deposited over the structure prior to patterning of the metal layer; FIG. 14 illustrates schematically, in cross-section, the structure of FIG. 13 illustrating the patterning of the metal to create electrical interconnect between the logic elements in the silicon and a memory element fabricated on the silicon substrate; FIGS. 15 illustrates schematically, in cross-section, memory elements built on a silicon wafer in accordance with alternate embodiments of the present invention; and

FIG. 16 illustrates schematically, in cross-section, a heterostructure transistor formed on silicon substrate.

Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.

Detailed Description of the Drawings

FIG. 1 illustrates schematically, in cross section, a portion of a microelectronic structure 20 in accordance with an embodiment of the invention. Microelectronic structure 20 includes a monocrystalline substrate 22, accommodating buffer layer 24 comprising a monocrystalline material, and a layer 26 of a monocrystalline conductive oxide material. In this context, the term "monocrystalline" shall have the meaning commonly used within the semiconductor industry. The term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry.

In accordance with one embodiment of the invention, structure 20 also includes an amorphous intermediate layer 28 positioned between substrate 22 and accommodating buffer layer 24. Structure 20 may also include a template layer 30 between the accommodating buffer layer and monocrystalline oxide layer 26. As will be explained more fully below, the template layer helps to initiate the growth of the conductive oxide layer on the accommodating buffer layer. The amorphous intermediate layer helps to relieve the strain in the accommodating buffer layer and, by doing so, aids in the growth of a high crystalline quality accommodating buffer layer. Substrate 22, in accordance with an embodiment of the invention, is a monocrystalline semiconductor wafer, preferably of large diameter. The wafer can be of a material from Group IV of the periodic table, and preferably a material from Group IVA. Examples of Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like. Substrate 22 can also be of a compound semiconductor material . The compound semiconductor material of substrate 22 can be selected, as needed for a particular semiconductor structure, from any of the Group IIIA and VA elements (III-V semiconductor compounds) , mixed III-V compounds, Group II (A or B) and VIA elements (II-VI semiconductor compounds), and mixed II-VI compounds. Examples include gallium arsenide (GaAs) , gallium indium arsenide (GalnAs) , gallium aluminum arsenide (GaAlAs) , indium phosphide (InP) , cadmium sulfide (CdS) , cadmium mercury telluride (CdHgTe) , zinc selenide (ZnSe) , zinc sulfur selenide (ZnSSe) , and the like. Preferably, substrate 22 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry. Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material epitaxially grown on the underlying substrate . In accordance with one embodiment of the invention, amorphous intermediate layer 28 is grown on substrate 22 at the interface between substrate 22 and the growing accommodating buffer layer by the oxidation of substrate 22 during the growth of layer 24. The amorphous intermediate layer serves to relieve strain that might otherwise occur in the monocrystalline accommodating buffer layer as a result of differences in the lattice constants of the substrate and the buffer layer. As used herein, lattice constant refers to the distance between atoms of a cell measured in the plane of the surface. If such strain is not relieved by the amorphous intermediate layer, the strain may cause defects in the crystalline structure of the accommodating buffer layer. Defects in the crystalline structure of the accommodating buffer layer, in turn, would make it difficult to achieve a high quality crystalline structure in monocrystalline conductive oxide layer 26. Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying substrate and with the overlying conductive oxide material. For example, the material could be an oxide or nitride having a lattice structure substantially matched to the substrate and/or to the subsequently applied conductive oxide material. Materials that are suitable for the accommodating buffer layer include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for the accommodating buffer layer. Most of these materials are insulators, although strontium ruthenate, for example, is a conductor. Generally, these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements and have a perovskte crystalline structure. In some specific applications, the metal oxides or nitride may include three or more different metallic elements.

Amorphous interface layer 28 is preferably an oxide formed by the oxidation of the surface of substrate 22, and more preferably is composed of a silicon oxide. The thickness of layer 28 is sufficient to relieve strain attributed to mismatches between the lattice constants of substrate 22 and accommodating buffer layer 24. Typically, layer 28 has a thickness in the range of approximately 0.5-5 nm.

The conductive oxide material of layer 26 can be selected, as desired for a particular structure or application. For example, layer 26 can include (La,Sr)Co0₃, SrRu0₃, SrCr0₃, and SrV0₃, having a thickness in the range of about 2 to 200 nm.

Suitable template materials chemically bond to the surface of the accommodating buffer layer 24 at selected sites and provide sites for the nucleation of the epitaxial growth of the subsequent conductive oxide layer 26. When used, template layer 30 has a thickness ranging f om about one to about ten monolayers .

FIG. 2 illustrates, in cross section, a portion of a microelectronic structure 40 in accordance with a further embodiment of the invention. Structure 40 is similar to the previously described structure 20, except that a ferroelectric layer 32 is formed over conductive oxide layer 26. Exemplary ferroelectric materials suitable for layer 32 include perovskite metallic oxides such as Pb(Ti,Zr)0₃, Bi₄ (Ti,Zr) ₃0₁₂, SrBi₂ (Ta,Nb) ₂0₉, YMn0₃, and BaTi0₃.

FIG. 3 schematically illustrates, in cross section, a portion of a microelectronic structure 34 in accordance with another exemplary embodiment of the invention. Structure 34 is similar to structure 40, except that structure 34 includes an amorphous layer 36, rather than accommodating buffer layer 24 and amorphous interface layer 28.

As explained in greater detail below, amorphous layer 36 may be formed by first forming an accommodating buffer layer and an amorphous interface layer in a similar manner to that described above . A thin cap layer may then be formed (preferably by epitaxial growth) overlying the monocrystalline accommodating buffer layer. The accommodating buffer layer is then exposed to an anneal process to convert the monocrystalline accommodating buffer layer to an amorphous layer. Amorphous layer 36 formed in this manner comprises materials from both the accommodating buffer and interface layers, which amorphous layers may or may not amalgamate. Thus, layer 36 may comprise one or two amorphous layers. Formation of amorphous layer 36 between substrate 22 and conductive oxide layer 26 relieves stresses between layers 22 and 26 and provides a true compliant substrate for subsequent processing.

The processes previously described above in connection with FIGS . 1 and 2 are adequate for growing monocrystalline metallic oxide layers over a monocrystalline substrate. However, the process described in connection with FIG. 3, which includes transforming a monocrystalline accommodating buffer layer to an amorphous oxide layer, may be better for growing monocrystalline conductive oxide and ferroelectric layers because it allows any strain in layer 26 to relax prior to forming layer 32.

In accordance with one embodiment of the present invention, layer 30 serves as an anneal cap during layer 36 formation and as a template for subsequent conductive oxide layer 26 formation.

The following non-limiting, illustrative examples illustrate various combinations of materials useful in structures 20, 40, and 34 in accordance with various alternative embodiments of the invention. These examples are merely illustrative, and it is not intended that the invention be limited to these illustrative examples.

Example 1

In accordance with one embodiment of the invention, monocrystalline substrate 22 is a silicon substrate oriented in the (100) direction. The silicon substrate can be, for example, a silicon substrate as is commonly used in making complementary metal oxide semiconductor (CMOS) integrated circuits having a diameter of about 200- 300 mm. In accordance with this embodiment of the invention, accommodating buffer layer 24 is a monocrystalline layer of Sr_zBa₁__zTi0₃ where z ranges from 0 to 1 and the amorphous intermediate layer is a layer of silicon oxide (SiO_x) formed at the interface between the silicon substrate and the accommodating buffer layer. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of the subsequently formed layer 26. The accommodating buffer layer can have a thickness of about 2 to about 100 nanometers (nm) and preferably has a thickness of about 10 nm. In general, it is desired to have an accommodating buffer layer thick enough to isolate the conductive layer from the substrate to obtain the desired properties. Layers thicker than 100 nm usually provide little additional benefit while increasing cost unnecessarily; however, thicker layers may be fabricated if needed. The amorphous intermediate layer of silicon oxide can have a thickness of about 0.5-5 nm, and preferably a thickness of about 1.5-2.5 nm.

In accordance with this embodiment of the invention, conductive material layer 26 is a layer of (La,Sr)Co0₃ having a thickness of about 2 to about 200 nm and preferably a thickness of about 10 to about 100 nm. The thickness generally depends on the application for which the layer is being prepared. Example 2

In accordance with another embodiment of the invention, a structure is provided that is suitable for the growth of an epitaxial film of ferroelectric material overlying a conductive material as illustrated in FIG. 2. The substrate is preferably a silicon wafer as described above. A suitable accommodating buffer layer material is Sr_xBa₁__xTi0₃, where x ranges from 0 to 1, having a thickness of about 2-100 nm and preferably a thickness of about 5-15 nm. The conducting oxide can be (La,Sr)Co0₃, having a thickness of about 2 to about 200 nm and preferably a thickness of about 10 to about 100 nm. Layer 98 of ferroelectric material includes Pb(Ti,Zr)0₃, having a thickness of about 2 to about 200 nm and preferably a thickness of about 10 to about 100 nm.

Referring again to FIGS. 1 - 3, substrate 22 is a monocrystalline substrate such as a monocrystalline silicon or gallium arsenide substrate. The crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation. In similar manner, accommodating buffer layer 24 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation. The lattice constants of the accommodating buffer layer and the monocrystalline substrate must be closely matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved. In this context the terms "substantially equal" and "substantially matched" mean that there is sufficient similarity between the lattice constants to permit the growth of a high quality crystalline layer on the underlying layer.

FIG. 4 graphically illustrates the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal. Curve 42 illustrates the boundary of high crystalline quality material. The area to the right of curve 42 represents layers that tend to be polycrystalline. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly. As a reference point, for example, if the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm cannot be achieved. In accordance with one embodiment of the invention, substrate 22 is a (100) or (111) oriented monocrystalline silicon wafer and accommodating buffer layer 24 is a layer of strontium barium titanate. Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate material by 45° with respect to the crystal orientation of the silicon substrate wafer. The inclusion in the structure of amorphous interface layer 28, a silicon oxide layer in this example, if it is of sufficient thickness, serves to reduce strain in the titanate monocrystalline layer that might result from any mismatch in the lattice constants of the host silicon wafer and the grown titanate layer. As a result, in accordance with an embodiment of the invention, a high quality, thick, monocrystalline titanate layer is achievable.

Still referring to FIGS. 1 - 3, layer 26 is a layer of epitaxially grown conductive oxide material and that crystalline material is also characterized by a crystal lattice constant and a crystal orientation. In accordance with one embodiment of the invention, the lattice constant of layer 26 differs from the lattice constant of substrate 22. To achieve high crystalline quality in this epitaxially grown monocrystalline layer, the accommodating buffer layer must be of high crystalline quality. In addition, in order to achieve high crystalline quality in layer 26, substantial matching between the crystal lattice constant of the host crystal, in this case, the monocrystalline accommodating buffer layer, and the grown crystal is desired. With properly selected materials, this substantial matching of lattice constants is achieved as a result of rotation of the crystal orientation of the grown crystal with respect to the orientation of the host crystal. In some instances, a crystalline buffer layer between the host oxide and the grown conductive oxide layer can be used to reduce strain in the grown monocrystalline conductive oxide layer that might result from small differences in lattice constants. Better crystalline quality in the grown monocrystalline conductive oxide layer can thereby be achieved.

The following example illustrates a process, in accordance with one embodiment of the invention, for fabricating a microelectronic structure such as the structures depicted in FIGS. 1 - 3. The process starts by providing a monocrystalline semiconductor substrate comprising silicon or germanium. In accordance with a preferred embodiment of the invention, the semiconductor substrate is a silicon wafer having a (100) orientation. The substrate is preferably oriented on axis or, at most, about 0.5° off axis . At least a portion of the semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures. The term "bare" in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material. As is well known, bare silicon is highly reactive and readily forms a native oxide. The term "bare" is intended to encompass such a native oxide. A thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process in accordance with the invention. In order to epitaxially grow a monocrystalline oxide layer overlying the monocrystalline substrate, the native oxide layer must first be removed to expose the crystalline structure of the underlying substrate. The following process is preferably carried out by molecular beam epitaxy (MBE) , although other epitaxial processes may also be used in accordance with the present invention. The native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus. In the case where strontium is used, the substrate is then heated to a temperature of about 750° C to cause the strontium to react with the native silicon oxide layer. The strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface. The resultant surface, which exhibits an ordered

2x1 structure, includes strontium, oxygen, and silicon. The ordered 2x1 structure forms a template for the ordered growth of an overlying layer of a monocrystalline oxide. The template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer .

In accordance with an alternate embodiment of the invention, the native silicon oxide can be converted and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkali earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 750°C. At this temperature, a solid state reaction takes place between the strontium oxide and the native silicon oxide, causing the reduction of the native silicon oxide and leaving an ordered 2x1 structure with strontium, oxygen, and silicon remaining on the substrate surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer.

Following the removal of the silicon oxide from the surface of the substrate, in accordance with one embodiment of the invention, the substrate is cooled to a temperature in the range of about 200-800°C and a layer of strontium titanate is grown on the template layer by molecular beam epitaxy. The MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources. The ratio of strontium and titanium is approximately 1:1. The partial pressure of oxygen is initially set at a minimum value to grow stochiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value. The overpressure of oxygen causes the growth of an amorphous silicon oxide layer at the interface between the underlying substrate and the growing strontium titanate layer. The growth of the silicon oxide layer results from the diffusion of oxygen through the growing strontium titanate layer to the interface where the oxygen reacts with silicon at the surface of the underlying substrate. The strontium titanate grows as an ordered monocrystal with the crystalline orientation rotated by 45° with respect to the ordered 2x1 crystalline structure of the underlying substrate. Strain that otherwise might exist in the strontium titanate layer because of the small mismatch in lattice constant between the silicon substrate and the growing crystal is relieved in the amorphous silicon oxide intermediate layer. After the strontium titanate layer has been grown to the desired thickness, the monocrystalline strontium titanate may be capped by a template layer that is conducive to the subsequent growth of an epitaxial layer of a desired conductive oxide material. For example, the MBE growth of the strontium titanate monocrystalline layer can be capped by terminating the growth with 1-2 monolayers of titanium, 1-2 monolayers of titanium-oxygen or with 1-2 monolayers of strontium-oxygen. Following the formation of the template (if one is formed) , the conductive oxide material is grown using MBE or other suitable techniques .

The structure illustrated in FIG. 2 can be formed by the process discussed above with the addition of a ferroelectric material layer deposition step. The ferroelectric material layer is formed overlying the conductive oxide by, for example, using RF sputter deposition.

Structure 34, illustrated in FIG. 3, may be formed by growing an accommodating buffer layer, forming an amorphous oxide layer over substrate 22, and growing a thin anneal cap over the accommodating buffer layer, as described above. The accommodating buffer layer and the amorphous oxide layer are then exposed to an anneal process sufficient to change the crystalline structure of the accommodating buffer layer from monocrystalline to amorphous, thereby forming an amorphous layer such that the combination of the amorphous oxide layer and the now amorphous accommodating buffer layer form a single amorphous oxide layer 36. Layer 26 is then subsequently grown over the anneal cap layer. Alternatively, the anneal process may be carried out subsequent to growth of layer 26.

In accordance with one aspect of this embodiment, layer 36 is formed by exposing substrate 22, the accommodating buffer layer, and the amorphous oxide layer to a rapid thermal anneal process with a peak temperature of about 700°C to about 1000°C and a process time of about 10 seconds to about 10 minutes. However, other suitable anneal processes may be employed to convert the accommodating buffer layer to an amorphous layer in accordance with the present invention. For example, laser annealing or "conventional" thermal annealing processes (in the proper environment) may be used to form layer 36. The process described above illustrates a process for forming a semiconductor structure including a silicon substrate, an overlying oxide layer, and a monocrystalline conductive oxide layer by the processed of molecular beam epitaxy and RF sputter deposition. The process can also be carried out by the process of chemical vapor deposition (CVD) , metal organic chemical vapor deposition (MOCVD) , migration enhanced epitaxy (MEE) , atomic layer epitaxy (ALE) , physical vapor deposition (PVD) , chemical solution deposition (CSD) , pulsed laser deposition (PLD) , or the like. Further, by a similar process, other monocrystalline accommodating buffer layers such as alkaline earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates, peroskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown. Further, by a similar process such as MBE, other conductive oxide layers can be deposited overlying the monocrystalline oxide accommodating buffer layer. For example, the conductive oxide may be grown via PLD, by ablating a target of the desired material with an eximer laser and heating the substrate to a temperature of about 300 °C to about 500 °C Each of the variations of conductive oxide, ferroelectric, and monocrystalline oxide accommodating buffer layers may use an appropriate template for initiating the growth of the respective layer. In such a case, suitable template materials may be grown according to the methods described above in connection with growing layer 26.

FIG. 5 illustrates a semiconductor structure 90, for example, a non-volatile memory element, including a monocrystalline semiconductor substrate 92, an amorphous oxide layer 93 and a monocrystalline insulative oxidide layer 94 overlying substrate 92, a conductive layer 96, and a ferroelectric layer 98 overlying conductive layer 96 . Structure 90 is similar to structure 34, except that a template layer is not illustrated in FIG. 5. Nevertheless, structure 90 may include template layers between any adjacent monocrystalline layers as described herein. In a preferred embodiment, substrate 92 is a silicon substrate, and layer 94 is an insulative oxide layer, for example, an oxide selected from the group consisting of alkali earth metal titanates, zirconates, hafnates, tantalates, ruthenates, niobates and vanadates, perovskites including tin based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide, as discussed above in connection with layer 24, illustrated in FIGS. 1-3 above. In a particularly preferred embodiment, layer 94 comprises (Ba,Sr)Ti0₃.

Layer 96 is preferably a oxide channel layer that behaves as either a metallic conductor or a semiconductor. In a preferred embodiment, channel layer 96 is a monocrystalline perovskite oxide material selected from the group consisting of (La,Sr)Co0₃, SrRu0₃, SrCr0₃, and SrV0₃. Layer 96 preferably exhibits a thickness in the range of about 2 to 200 nm.

Ferroelectric layer 98 preferably comprises a metallic oxide material { e . g. , oxide material discussed above in connection with layer 32) selected from the group consisting of Pb(Ti,Zr)0₃, Bi₄(Ti,Zr) ₃0₁₂, SrBi₂ (Ta,Nb) ₂0₉, YMn0₃, and BaTi0₃.

Those skilled in the art will appreciate that semiconductor structure 90 of FIG. 5 may be patterned, for example, photolithographically, to produce memory element structures in any desired configuration.

FIG. 6 illustrates schematically, in cross-section, the semiconductor structure 100, for example, a non- volatile memory element. Structure 100 preferably includes substrate 92, amorphous layer 93, insulator layer 94, preferably epitaxially grown overlying the substrate, and monocrystalline channel layer 96 epitaxially grown over layer 94. Structure 100 further includes ferroelectric layer 98 and a gate electrode layer 102 overlying the ferroelectric layer and the channel region formed by conductive layer 96. As illustrated in FIG. 6, gate electrode layer 102, ferroelectric layer 98, and channel layer 96 have been patterned ( e . g. , photolithographically) to expose a first electrical contact 97 and a second electrical contact 99 associated with conductor channel layer 96. Those skilled in the art will appreciate that the electrical contacts associated with the conductive region in a memory element may be disposed on the upper surface of the channel region, at the ends of the channel region, or in any convenient location which allows electrical contact with spaced apart electrical contacts 97 and 99. Gate electrode 102 can be formed of any suitable conductive material and preferably comprises a monocrystalline conductive oxide, for example, (La,Sr) Co0₃.

In a preferred embodiment, structure 100 of FIG. 6 may be manufactured as described herein by first providing semiconductor substrate 92, thereafter epitaxially growing layer 94 and forming layer 93 over substrate 92, and thereafter epitaxially growing conductive layer 96 over insulative layer 94. Ferroelectric layer 98 by then be epitaxially grown overlaying conductive layer 96, whereupon conductive layer 102 is formed over ferroelectric layer 98. Conductor layer 102 suitably comprises a metal layer, and may be epitaxially grown as a conductive oxide.

FIG. 7 illustrates schematically, in cross section, a semiconductor structure 104 generally analogous to structure 100 shown in FIG. 6, and further illustrating a logic element 104, for example a portion of an integrated circuit, formed in the in substrate 92, as well as an interconnect metalization structure 106 extending from a portion of logic element 104 to gate electrode 102. Those skilled in the art will appreciate that the various layers 92, 93, 94, 96, 98, and 102 may be patterned as needed to form any desired electrical interconnections between and among the memory elements fabricated from conductive layer 96 and ferroelectric layer 98, on the one hand, and logic elements formed within substrate 92 on the other hand.

FIG. 8 illustrates schematically, in cross section, a semiconductor structure 112 generally analogous to structure 100 shown in FIG. 6, further illustrating logic element 104 and a patterned interconnect metalization structure 114 extending between and making electrical connection between a portion of logic element 104 and channel oxide layer 96. In the illustrated embodiment, logic element 104 comprises a field effect transistor (FET) , for example, a metal oxide semiconductor field effect transistor (MOSFET) . Those skilled in the art will appreciate, however, that virtually any microelectronic structures fabricated at least in part within substrate 92 may be electrically integrated with the memory elements formed from layers 96, 98 and 102, to accommodate each specific application.

FIG. 10 illustrates schematically, in cross section, a semiconductor structure 146 including substrate layer 92, insulative oxide layer 94, channel layer 96, and ferroelectric layer 98. Semiconductor structure 146 also includes logic element 104 fabricated at least partially within substrate 92, amorphous layer 93, and a template layer 118 to facilitate lattice matching between insulative layer 94 and substrate 92, as discussed above in greater detail in connection with FIGS. 1-3. In the context of structure 146, logic element 104 may comprise an integrated logic circuit configured to communicate with other logic circuits (not shown) formed in substrate 92 and/or memory elements formed in conductive layer 96 and ferroelectric layer 98, as described below in greater detail.

In accordance with one aspect of the present invention, semiconductor structure 146 (as well as many of the other semiconductor structures described herein) may be conveniently fabricated in accordance with the following process parameters.

Integrated logic circuits, for example, logic element 104, may be partially or fully formed in substrate layer 92. Thereafter, template layer 118 may be grown overlaying substrate 92. In many cases, substrate layer 92 exhibits a silicon oxide layer on the surface thereof. Hence, template layer 118 may conveniently be formed by depositing the material ( e . g. , alkali earth metals, alkali metal oxides) onto silicon oxide layer formed on substrate 92 and thereafter heating the silicon substrate to react the alkali earth metal and/or the alkali earth metal oxide with the silicon oxide. Depositing the alkali earth metal and/or alkali earth metal oxide may be conveniently accomplished by the methods described in connection with FIGS 1-3. Thereafter, insulator layer 94 may be epitaxially grown on substrate 92, for example, by heating substrate 92 to a temperature between about 200 °C and 800 °C, and introducing reactants into the deposition chamber, for example, reactants comprising titanium, oxygen, and an element selected from strontium, barium, and strontium and barium. In this regard, it may be desirable to control the ratio of strontium to titanium or barium to titanium, and to control the partial pressure of oxygen as described in greater detail above in connection with FIGS. 1-3.

As also described above in connection with FIGS. 1-3 and with continued reference to FIG. 10, during the growth of insulative layer 94, amorphous oxide layer 93 is advantageously formed, for example, by increasing the partial pressure of oxygen above a level necessary for epitaxially growing insulator layer 94. As discussed above, epitaxially growing insulator layer 94 may preferably be performed by depositing a monocrystalline insulator selected from the group consisting of alkali earth metal titanites, zirconates, hafnates, tantalates, ruthenates, niobates and vanadates, tin based perovskites, lanthanum aluminate, lanthanum scandium oxide, gadolinium oxide, gallium nitride, and aluminum nitride. In a preferred embodiment of the present invention, the step of epitaxially growing a monocrystalline insulator comprises the step of depositing monocrystalline (Ba,Sr)Ti0₃. After insulator layer 94 has been fabricated, conductive monocrystalline layer 96 may be epitaxially grown over layer 94, for example, by growing a monocrystalline layer of material selected from the group consisting of (La,Sr)Co0₃, SrRu0₃, SrCr0₃, and SrV0₃. As stated above, each epitaxially growth step may be performed using an epitaxial process from the group consisting of MBE, MOCVD, MEE, CVD, PVD, PLD, CSD and ALE. Ferroelectric oxide layer 98 may then be conveniently epitaxially grown, for example, by the step of growing a monocrystalline layer of the material selected from the group consisting of Pb(Ti,Zr)0₃, Bi₄(Ti,Zr) ₃0₁₂,

SrBi₂ (Ta,Nb)₂0₉, YMn0₃, and BaTi0₃ using, for example, methods described in connection with forming ferroelectric layer 32.

In order to form non-volatile memory elements in structure 146, various photolithographic and other processing steps (for example, etching) may be performed as is known in the art.

More particularly, and referring now to FIG. 11, a semiconductor structure 148, generally analogous to structure 146 of FIG. 10, may be formed by patterning respective layers 118, 93, 94, 96, and 98 to permit the formation of an electrical interconnect 150 extending from a portion of logic element 104 to electrically conductive oxide layer 96 . FIG. 15 illustrates schematically, in cross-section, an alternate embodiment of the present invention, in which a semiconductor structure 174 comprises respective layers 92, 93, 94, 96, 98, and 102, wherein respective layers 93, 94, 96, 98, and 102 are selectively patterned to enable the forming of an interconnect 176 extending from logic element 104 to conductive oxide layer 96.

FIG. 12 illustrates schematically, in cross-section, a semiconductor structure 188 including substrate 92, template layer 98, amorphous layer 93, insulative oxide layer 94 , conductive channel layer 94 , ferroelectric layer 98, and logic element 104 disposed at least partially within substrate layer 92. In FIG. 12 it can be seen that various layers, including respective layers 93, 94, 96 and 98 have been patterned to expose a gate dielectric region 190 immediately proximate logic element 104. In a preferred embodiment, logic element 104 is a MOSFET, and gate dielectric region 190 is exposed to permit the patterning of a dielectric material in this region. Semiconductor structure 188 further illustrates the patterning of at least oxide layer 94 to form spaced apart first contact region 152 and second contact region 154 associated with logic element 104. As described in greater detail below in connection with FIGS. 13 and 14, first and second contact regions 152 and 154 may be placed into contact with an electrical interconnect thereby allowing logic element 104 to communicate with one or more additional logic elements .

FIG. 13 illustrates schematically, in cross section, a semiconductor structure 156 including substrate layer 92, template layer 118, amorphous layer 93, insulator layer 94, channel layer 96 and ferroelectric layer 98, shown patterned to enable the monolithic integration of the memory element fabricated from channel layer 96 and ferroelectric layer 98, on the one hand, and integrated circuit elements formed in substrate 92, as discussed in greater detail below.

With continuing reference to FIG. 13, a first logic element 120 is formed in substrate 92, including a source electrode 124 and a drain electrode 126; similarly, a second logic element 122 is formed within substrate 92, including a drain electrode 128 and a source electrode 130. Those skilled in the art will appreciate that the foregoing electrodes may suitably comprise portions of a MOSFET .

With momentary reference to FIG. 12, it can be seen that semiconductor structure 156 of FIG. 13 includes a first dielectric 158 formed at gate dielectric region 190. For completeness, a second dielectric structure 160 is formed in a corresponding gate dielectric region associated with logic element 122.

With continued reference to FIG. 13, in order to provide electrical communication between logic elements 120 (and logic element 122) and channel region 96, it may be advantageous to deposit a layer of metal 162 over the entire semiconductor structure 156. As seen in FIG. 14, metal layer 162 may then be patterned to form a first gate electrode 166 overlying gate dielectric 158 and a second gate electrode 160 overlying gate dielectric 160. In addition, patterning metal layer 162 may also yield an interconnecting trace 170 extending from drain electrode 126 to channel 96, as well as a second electrical interconnect extending from drain electrode 128 to the oppositely disposed contact side of channel 96.

As briefly mentioned above, the various layers and semiconductor structures discussed herein may be patterned in any desired configuration to produce heterostructures, integrated structures, or monolithic structures as desired.

FIG. 9 illustrates schematically, in cross-section, a semiconductor structure 116, including a monocrystalline substrate 92, respective logic elements 120 and 122 formed therein, respective gate dielectrics 134 and 136, respective gate electrodes 138 and 140, a first electrical interconnect 142 connecting drain 126 with channel 96 and a second electrical interconnect 144 connecting drain 128 with channel 96. Semiconductor structure 116 further includes a gate electrode 102. In accordance with an alternate embodiment of the present invention, an isolation region 132 may suitably be formed around the memory element comprising channel 96 and ferroelectric element 98. Those skilled in the art will appreciate that isolation region 132 may be manufactured using known fabrication techniques.

FIG. 16 illustrates schematically, in cross-section, a semiconductor structure 180, selectively patterned to yield a heterostructure transistor 196 which includes selectively patterned portions of respective layers 96 , 98 and 102. Those skilled in the art will appreciate that heterostructure transistor 196 preferably includes a first electrode 182, a second electrode 186, and a gate electrode 184, which are illustrated schematically. Those skilled in the art will appreciate the electrical connections extending from these electrodes may be configured to communicate with other memory devices and/or logic devices formed within substrate 92. Although not illustrated in Figures 5-18, any of the structures illustrated in these figures may include an amorphous layer between the substrate and the conductive layer rather than monocrystalline layer 94, wherein the amorphous layer comprise material from, for example layers 93 and 94. Such an amorphous layer is formed according to the methods described above in connection with FIG. 3. In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element (s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. As used herein, the terms "comprises,"

"comprising, " or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Claims

CLAIMS We Claim:

1. A non-volatile memory element comprising:

a monocrystalline semiconductor substrate;

a monocrystalline insulative oxide layer epitaxially grown overlying the substrate;

a monocrystalline channel layer epitaxially grown overlying the monocrystalline insulative oxide layer;

first and second spaced apart electrical contacts to the channel layer, the first and second spaced apart electrical contacts defining a channel region therebetween;

a monocrystalline ferroelectric layer epitaxially grown overlying the channel region; and

a gate electrode overlying the ferroelectric layer and the channel region.

2. The memory element of claim 1 further comprising at least a portion of an integrated circuit formed in the semiconductor substrate .

3. The memory element of claim 2 further comprising an interconnect metallization extending from the portion of the integrated circuit to the gate electrode .

4. The memory element of claim 1 wherein the semiconductor substrate comprises a silicon substrate.

5. The memory element of claim 4 further comprising an amorphous strain relief layer formed between the silicon substrate and the monocrystalline insulative oxide layer.

6. The memory element of claim 5 wherein the amorphous strain relief layer comprises a silicon oxide.

7. The memory element of claim 1 wherein the monocrystalline insulative oxide layer comprises an oxide selected from the group consisting of alkali earth metal titanates, zirconates, hafnates, tantalates, ruthenates, niobates and vanadates, perovskites including tin based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide.

8. The memory element of claim 7 wherein the monocrystalline insulative oxide comprises an alkali earth metal titanate.

9. The memory element of claim 1 wherein the monocrystalline insulative oxide comprises (Ba,Sr)Ti0₃.

10. The memory element of claim 9 further comprising an amorphous strain relief layer formed underlying the monocrystalline insulative oxide.

11. The memory element of claim 1 wherein the monocrystalline channel layer comprises a material selected from the group consisting of conductors and semiconductors .

12. The memory element of claim 11 wherein the monocrystalline channel layer comprises a monocrystalline perovskite oxide .

13. The memory element of claim 11 wherein the monocrystalline channel layer comprises a material selected from the group consisting of (La,Sr)Co0₃, SrRu0₃, SrCr0₃, and SrV0₃.

14. The memory element of claim 12 wherein the monocrystalline channel layer has a thickness of about 2 ■ 200nm.

15. The memory element of claim 1 wherein the monocrystalline ferroelectric layer comprises a material from the group consisting of Pb(Ti,Zr)0₃, Bi₄ (Ti, Zr) ₃0₁₂, SrBi₂ (Ta,Nb) ₂0₉, YMn0₃, and (Ba,Sr)Ti0₃.

16. The memory element of claim 1 wherein the gate electrode comprises a metal electrode.

17. The memory element of claim 1 wherein the gate electrode comprises a conductive oxide.

18. The memory element of claim 1 wherein the gate electrode comprises (La,Sr)Co0₃.

19. A non-volatile memory circuit comprising:

a monocrystalline silicon substrate;

a portion of an MOS circuit formed in the silicon substrate;

a monocrystalline insulative oxide comprising a material from the group consisting of alkali earth metal titanates, zirconates, hafnates, tantalates, ruthenates, niobates and vanadates, perovskites including tin based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide epitaxially grown overlying the silicon substrate;

an amorphous silicon oxide strain relief layer formed between the monocrystalline insulative oxide and the silicon substrate;

a monocrystalline channel oxide layer comprising a material selected from the group consisting of (La,Sr)Co0₃, SrRu0₃, SrCr0₃, and SrV0₃ grown epitaxially overlying the monocrystalline insulative oxide;

a monocrystalline ferroelectric gate dielectric comprising a material selected from the group consisting of Pb(Ti,Zr)0₃, Bi₄ (Ti, Zr) ₃0₁₂, SrBi₂ (Ta,Nb) ₂0₉, YMn0₃, and

(Ba, Sr) Ti0₃ grown epitaxially overlying the monocrystalline channel oxide;

a gate electrode overlying the monocrystalline ferroelectric gate dielectric,- and

patterned interconnect metallization extending between and making electrical connection between the portion of the MOS circuit and the monocrystalline channel oxide .

20. A memory element comprising:

a monocrystalline semiconductor substrate;

a first monocrystalline insulative oxide layer epitaxially grown overlying the substrate;

a second monocrystalline conductive oxide layer overlying the first monocrystalline insulative oxide layer; and

a third monocrystalline ferroelectric oxide layer epitaxially grown overlying the second monocrystalline conductive oxide layer.

21. An integrated memory element comprising:

a monocrystalline silicon substrate;

first and second MOS transistors each having source and drain regions formed in the semiconductor substrate;

a first monocrystalline layer of (Ba,Sr)Ti03 formed overlying the silicon substrate;

a monocrystalline channel oxide layer comprising a material selected from the group consisting of (La,Sr)Co0₃, SrRu0₃, SrCr0₃, and SrV0₃ grown epitaxially overlying the first monocrystalline layer;

a monocrystalline ferroelectric gate dielectric comprising a material selected from the group consisting of Pb(Ti,Zr)0₃, Bi₄ (Ti, Zr)₃0₁₂, SrBi₂ (Ta,Nb) ₂0₉, YMn0₃, and (Ba, Sr) Ti0₃ grown epitaxially overlying- the monocrystalline channel oxide;

a gate dielectric layer overlying the first and second MOS transistors;

gate electrodes overlying the gate dielectric layer and forming first and second gates of the first and second MOS transistors, respectively:

a memory gate electrode overlying the monocrystalline ferroelectric gate dielectric; and

patterned interconnect metallization extending from the drain region of the first MOS transistor to a first portion of the monocrystalline channel oxide layer and from the drain of the second MOS transistor to a second portion of the monocrystalline channel oxide.

22. A process for fabricating a ferroelectric memory element comprising the steps of:

providing a monocrystalline semiconductor substrate;

forming an integrated logic circuit at least partially in the semiconductor substrate;

forming a first template layer overlying the semiconductor substrate;

epitaxially growing a monocrystalline insulator layer overlying the first template layer;

forming an amorphous oxide layer underlying the monocrystalline insulator layer during the step of epitaxially growing the monocrystalline insulator layer;

epitaxially growing an electrically conductive monocrystalline oxide layer overlying the monocrystalline insulator layer;

epitaxially growing a monocrystalline ferroelectric oxide layer overlying the electrically conductive monocrystalline oxide layer;

photolithographically patterning the monocrystalline insulator layer, the electrically conductive monocrystalline oxide layer and the monocrystalline ferroelectric oxide layer to expose a portion of the integrated logic circuit; and

forming an electrical interconnect extending from the portion of the integrated logic circuit to the electrically conductive oxide layer.

23. The process of claim 22 wherein the step of providing a monocrystalline semiconductor substrate comprises the step of providing a substrate comprising silicon having a silicon oxide layer on a surface thereof and the step of forming a first template layer comprises the steps of :

depositing a material from the group consisting of alkali earth metals and alkali earth metal oxides onto the silicon oxide layer and

heating the substrate to react the material with the silicon oxide.

24. The process of claim 23 wherein the step of depositing a material from the group consisting of alkali earth metals and alkali earth metal oxides comprises depositing a material from the group consisting of barium, strontium, and mixtures of barium and strontium, and barium oxide, strontium oxide, and barium strontium oxide.

25. The process of claim 24 wherein the step of epitaxially growing a monocrystalline insulator layer comprises the steps of:

heating the monocrystalline semiconductor substrate to a temperature between about 200 °C and about 800 °C; and

introducing reactants comprising titanium, oxygen, and an element selected from strontium, barium, and strontium and barium.

26. The process of claim 25 wherein the step of introducing comprises controlling the ratio of strontium to titanium or barium to titanium and controlling the partial pressure of oxygen.

27. The process of claim 26 wherein the step of forming an amorphous oxide layer comprises increasing the partial pressure of oxygen above a level necessary for epitaxially growing the monocrystalline insulator layer.

28. The process of claim 22 wherein the step of epitaxially growing a monocrystalline insulator comprises the step of depositing a monocrystalline insulator selected from the group consisting of alkali earth metal titanates, zirconates, hafnates, tantalates, ruthenates, niobates and vanadates, tin based perovskites, lanthanum aluminate, lanthanum scandium oxide, gadolinium oxide, gallium nitride, and aluminum nitride.

29. The process of claim 22 wherein the step of epitaxially growing a monocrystalline insulator comprises the step of depositing monocrystalline (Ba,Sr)Ti0₃.

30. The process of claim 22 wherein the step of epitaxially growing an electrically conductive monocrystalline oxide layer comprises the step of growing a monocrystalline layer of material selected from the group consisting of (La,Sr)Co0₃, SrRu0₃, SrCr0₃, and SrV0₃.

31. The process of claim 22 wherein each step of epitaxially growing comprises selecting an epitaxial process from the group consisting of MBE, MOCVD, MEE, CVD, PVD, PLD, CSD and ALE.

32. The process of claim 22 wherein the step of epitaxially growing a monocrystalline ferroelectric oxide layer comprises the step of growing a monocrystalline layer of a material selected from the group consisting of Pb(Ti,Zr)0₃, Bi₄(Ti,Zr)₃0₁₂, SrBi₂ (Ta,Nb) ₂0₉, YMn0₃, and (Ba,Sr)Ti0₃.

33. The process of claim 22 wherein the step of photolithographically patterning comprises the steps of:

patterning the monocrystalline ferroelectric oxide layer to form a gate dielectric region; and

patterning the electrically conductive monocrystalline oxide layer to form spaced apart first and second contact regions on the electrically conductive monocrystalline oxide layer.

34. The process of claim 33 wherein the step of forming an electrical interconnect comprises the steps of

depositing a layer of metal; and

patterning the layer of metal to form a gate electrode overlying the gate dielectric, metallic contacts to the contact regions, and an interconnecting trace extending from the portion of the integrated circuit to the first and second metallic contacts .

35. The process of claim 34 wherein the step of forming an integrated logic circuit comprises the step of forming first and second MOS transistors, each having spaced apart source and drain regions formed in the substrate, and the step of patterning the layer of metal comprises forming an interconnecting trace coupling the first contact to the drain of the first MOS transistor and coupling the second contact to the drain of the second MOS transistor.

36. A process for fabricating a ferroelectric device comprising the steps of:

providing a monocrystalline semiconductor substrate;

epitaxially growing a first layer of monocrystalline insulative oxide overlying the substrate;

epitaxially growing a second layer of monocrystalline electrically conductive oxide overlying the first layer;

epitaxially growing a third layer of monocrystalline ferroelectric material overlying the second layer; and

forming a conductor layer overlying the third layer.

37. The process of claim 36 wherein the step of forming a conductor layer comprises the step of depositing a metal layer.

38. The process of claim 36 wherein the step of forming a conductor layer comprises the step of epitaxially growing a fourth layer of conductive oxide,

39. A process for fabricating a ferroelectric device comprising the steps of:

providing a monocrystalline silicon substrate;

depositing sequentially, by a process selected from the group consisting of MBE, MOCVD, MEE, CVD, PVD, PLD, CSD and ALE, the following monocrystalline epitaxial layers :

a layer of (Sr, Ba) Ti0₃;

a layer of electrically conductive oxide selected from the group consisting of (La,Sr)Co0₃, SrRu0₃, SrCr0₃, and SrV0₃, and

a layer of ferroelectric oxide selected from the group consisting of Pb(Ti,Zr)0₃, Bi₄ (Ti, Zr) ₃0₁₂, SrBi₂ (Ta,Nb)₂0₉, YMn0₃, and (Ba,Sr)Ti0₃; and

forming a layer of conductive material overlying the layer of ferroelectric oxide.

40. The process of claim 39 further comprising the step of forming a CMOS logic circuit at least partially in the silicon substrate.

41. The process of claim 40 further comprising the step of forming interconnect metallization extending from the CMOS logic circuit to the layer of electrically conductive oxide .

42. The process of claim 39 further comprising the step of forming a strain relief layer underlying the layer of (Sr,Ba)Ti0₃.

43. The process of claim 39 further comprising the step of patterning the layer of conductive oxide, the layer of ferroelectric oxide, and the layer of conductive material to form a heterostructure transistor.