EP1333611A3 - Circuit de génération d'horloge - Google Patents

Circuit de génération d'horloge Download PDF

Info

Publication number
EP1333611A3
EP1333611A3 EP03250372A EP03250372A EP1333611A3 EP 1333611 A3 EP1333611 A3 EP 1333611A3 EP 03250372 A EP03250372 A EP 03250372A EP 03250372 A EP03250372 A EP 03250372A EP 1333611 A3 EP1333611 A3 EP 1333611A3
Authority
EP
European Patent Office
Prior art keywords
signal generating
generating circuit
timing signal
circuit
input signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP03250372A
Other languages
German (de)
English (en)
Other versions
EP1333611B1 (fr
EP1333611A2 (fr
Inventor
Takaya Fujitsu Higashi-Nihon Dig.Tech.Ltd. Chiba
Hirotaka c/o Fujitsu Limited Tamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of EP1333611A2 publication Critical patent/EP1333611A2/fr
Publication of EP1333611A3 publication Critical patent/EP1333611A3/fr
Application granted granted Critical
Publication of EP1333611B1 publication Critical patent/EP1333611B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0025—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of clock signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dram (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Information Transfer Systems (AREA)
  • Manipulation Of Pulses (AREA)
  • Networks Using Active Elements (AREA)
EP03250372A 2002-02-01 2003-01-21 Circuit de génération d'horloge Expired - Lifetime EP1333611B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002025724A JP4107847B2 (ja) 2002-02-01 2002-02-01 タイミング信号発生回路および受信回路
JP2002025724 2002-02-01

Publications (3)

Publication Number Publication Date
EP1333611A2 EP1333611A2 (fr) 2003-08-06
EP1333611A3 true EP1333611A3 (fr) 2005-08-17
EP1333611B1 EP1333611B1 (fr) 2011-04-27

Family

ID=19192323

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03250372A Expired - Lifetime EP1333611B1 (fr) 2002-02-01 2003-01-21 Circuit de génération d'horloge

Country Status (4)

Country Link
US (1) US7173466B2 (fr)
EP (1) EP1333611B1 (fr)
JP (1) JP4107847B2 (fr)
DE (1) DE60336869D1 (fr)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4121863B2 (ja) 2003-01-29 2008-07-23 富士通株式会社 タイミング信号発生回路および受信回路
US7049882B2 (en) * 2004-02-03 2006-05-23 Broadcom Corporation Transmitter IF section and method enabling IF output signal amplitude that is less sensitive to process, voltage, and temperature
GB0413071D0 (en) 2004-06-12 2004-07-14 Texas Instruments Ltd Triangulating phase interpolator
WO2006030905A1 (fr) * 2004-09-17 2006-03-23 Nec Corporation Circuit de generation d’horloge et procede de generation d’horloge
US7301410B2 (en) * 2006-03-07 2007-11-27 International Business Machines Corporation Hybrid current-starved phase-interpolation circuit for voltage-controlled devices
US8958761B2 (en) * 2006-10-25 2015-02-17 Nxp, B.V. Determining on chip loading impedance of RF circuit
JP5303757B2 (ja) * 2007-06-18 2013-10-02 国立大学法人 長崎大学 タイミング発生回路
US20100123502A1 (en) * 2008-07-09 2010-05-20 Bhutta Imran A System for providing a substantially uniform potential profile
US8063683B2 (en) * 2009-06-08 2011-11-22 Integrated Device Technology, Inc. Low power clock and data recovery phase interpolator
JP5505208B2 (ja) * 2010-08-31 2014-05-28 富士通株式会社 受信回路
JP5569346B2 (ja) * 2010-11-08 2014-08-13 富士通株式会社 エンファシス信号生成回路及び信号合成回路
US8384459B2 (en) * 2011-05-10 2013-02-26 Elite Semiconductor Memory Technology Inc. Delay line circuit and phase interpolation module thereof
CN103516334B (zh) * 2012-06-15 2016-02-17 晶豪科技股份有限公司 延迟线电路及其相位内插模块
US9356588B2 (en) * 2014-06-09 2016-05-31 Qualcomm Incorporated Linearity of phase interpolators using capacitive elements
JP6354485B2 (ja) * 2014-09-18 2018-07-11 富士通株式会社 位相制御回路及び受信装置
US10128827B1 (en) * 2016-11-04 2018-11-13 Inphi Corporation High-speed phase interpolator
US10396772B2 (en) * 2016-12-12 2019-08-27 Psemi Corporation Methods and devices to improve switching time by bypassing gate resistor
JP7211010B2 (ja) * 2018-10-31 2023-01-24 セイコーエプソン株式会社 半導体集積回路、電子機器及び移動体

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0884732A2 (fr) * 1997-06-12 1998-12-16 Fujitsu Limited Circuit de temporisation, dispositif et système intégré à semiconducteurs auxquels le circuit de temporisation est connecté, et système de transmission de signaux
US6133773A (en) * 1997-10-10 2000-10-17 Rambus Inc Variable delay element
EP1104110A2 (fr) * 1999-11-26 2001-05-30 Fujitsu Limited Circuit de combinaison de phase et circuit générateur de signal d'horloge pour transmission de signal à grande vitesse
JP2001217682A (ja) * 1999-11-26 2001-08-10 Fujitsu Ltd 位相合成回路およびタイミング信号発生回路
EP1128559A1 (fr) * 2000-02-23 2001-08-29 Texas Instruments Incorporated Dispositif de génération d'un signal oscillant présentant une relation de phase souhaitée avec un signal d'entrée

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5757208A (en) * 1980-09-25 1982-04-06 Nissan Motor Co Ltd Course finder for vehicle
US4829257A (en) * 1987-02-20 1989-05-09 Cooper J Carl Method and apparatus for continuously shifting phase of an electronic signal
US6218887B1 (en) * 1996-09-13 2001-04-17 Lockheed Martin Corporation Method of and apparatus for multiplexing multiple input signals
KR100676354B1 (ko) * 2000-03-02 2007-01-31 산요덴키가부시키가이샤 가변 저항 회로, 연산 증폭 회로, 반도체 집적 회로,시상수 전환 회로 및 파형 성형 회로
US6509773B2 (en) * 2000-04-28 2003-01-21 Broadcom Corporation Phase interpolator device and method
JP3408788B2 (ja) * 2000-10-10 2003-05-19 川崎マイクロエレクトロニクス株式会社 Ｉ／ｖ変換回路およびｄａコンバータ
US6617936B2 (en) * 2001-02-20 2003-09-09 Velio Communications, Inc. Phase controlled oscillator
US6448811B1 (en) * 2001-04-02 2002-09-10 Intel Corporation Integrated circuit current reference

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0884732A2 (fr) * 1997-06-12 1998-12-16 Fujitsu Limited Circuit de temporisation, dispositif et système intégré à semiconducteurs auxquels le circuit de temporisation est connecté, et système de transmission de signaux
US6133773A (en) * 1997-10-10 2000-10-17 Rambus Inc Variable delay element
EP1104110A2 (fr) * 1999-11-26 2001-05-30 Fujitsu Limited Circuit de combinaison de phase et circuit générateur de signal d'horloge pour transmission de signal à grande vitesse
JP2001217682A (ja) * 1999-11-26 2001-08-10 Fujitsu Ltd 位相合成回路およびタイミング信号発生回路
EP1128559A1 (fr) * 2000-02-23 2001-08-29 Texas Instruments Incorporated Dispositif de génération d'un signal oscillant présentant une relation de phase souhaitée avec un signal d'entrée

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 25 12 April 2001 (2001-04-12) *

Also Published As

Publication number Publication date
EP1333611B1 (fr) 2011-04-27
JP4107847B2 (ja) 2008-06-25
JP2003229763A (ja) 2003-08-15
US20030146780A1 (en) 2003-08-07
DE60336869D1 (de) 2011-06-09
US7173466B2 (en) 2007-02-06
EP1333611A2 (fr) 2003-08-06

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