EP1323080A2 - Procede et agencement pour la comparaison entre deux systemes techniques par le biais de remplacements de systemes - Google Patents

Procede et agencement pour la comparaison entre deux systemes techniques par le biais de remplacements de systemes

Info

Publication number
EP1323080A2
EP1323080A2 EP01971643A EP01971643A EP1323080A2 EP 1323080 A2 EP1323080 A2 EP 1323080A2 EP 01971643 A EP01971643 A EP 01971643A EP 01971643 A EP01971643 A EP 01971643A EP 1323080 A2 EP1323080 A2 EP 1323080A2
Authority
EP
European Patent Office
Prior art keywords
systems
comparison
replacement
technical
technical systems
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01971643A
Other languages
German (de)
English (en)
Inventor
Stefan HÖRETH
Peter Warkentin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Onespin Solutions GmbH
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10105584A external-priority patent/DE10105584A1/de
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1323080A2 publication Critical patent/EP1323080A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking

Definitions

  • the invention relates to a method for comparing technical systems for the same technical functionality using system replacements.
  • a possible scenario in which the above problem can arise is an implementation verification in which a comparison of the synthesis results with the synthesis inputs is to be carried out to ensure that the synthesis process has not changed the functionality of the synthesis inputs.
  • a common method now consists in modifying the internal logic and in particular the coding of the internal states of the library cells based on heuristics in such a way that the internal behavior of the parts representing the library cell results from the synthesis inputs.
  • TM FormalPro
  • Mentor Graphics An example of a known solution is the FormalPro (TM) product, an implementation verification tool from Mentor Graphics. This uses heuristics to deal with various problem scenarios for library cells (see also Hughes, Roger B .: Whole-design formal verification of a 5-million gate design by equivalence checking is possible with a small memory footprint, DesignCon2000, February 2000).
  • this approach tries to find a kind of normal form for representing the library cells. This approach also supports the statement made above that library cells represent a particular problem.
  • the replacement condition is chosen such that it is not possible for every environment of the technical system to determine a difference between the technical system and the replacement system if only the interfaces of the technical system or its replacement system may be accessed for this check.
  • constraints are generated at the behavior of the 'environment in an automated manner so that the substitutability of the two systems under these restrictions may nevertheless be guaranteed.
  • a first advantageous embodiment of the method according to the present invention is characterized in this respect by the fact that the environment of the two technical systems to be compared is restricted by examining them for values potentially occurring at their outputs and reducing the environment by such input values that result in an output value that under no circumstances can be generated by the other system.
  • a further or alternative embodiment of the invention restricts the environment of the two technical systems to be compared by forming classes of inputs and restricting the environment in such a way that inputs from different classes do not change simultaneously.
  • This can be both an alternative to the possibility of a restriction described above, and also as a supplementary measure, if the first-mentioned restriction does not lead to success, ie the condition for replaceability cannot be proven.
  • replaceability can also be seen as a special case of replaceability under restrictions, if the restrictions are logically always true, i.e. are fulfilled by any environment.
  • the basic idea of the invention is accordingly that a comparison of two technical systems, which is not feasible according to the current general view, can be attributed to a considerably simpler, technically feasible comparison, in that subsystems of one or both systems are specifically replaced become.
  • the replacements are carried out in a controlled manner by checking an interchangeability condition with restrictions.
  • the replacement condition as well as the generation and checking of the necessary restrictions are carried out automatically. This enables a comparison of the two systems based on the replacement of the subsystems without a loss of precision in the comparison.
  • FIG. 1 shows a schematic diagram of an implementation verification based on replacements of library cells according to the invention.
  • a technical system FSM1 can be replaced with a technical system FSMO under the restriction C (FSMl ⁇ c FSMO) if there is a state SO of the system FSMO for each state S1 of the system FSM1 and for each sequence of input values, so that both the Restriction C is observed by the considered sequence of input values and at the same time the sequence of the output values for SO corresponds to the sequence for S1 for the considered input sequence.
  • FSMl ⁇ c FSMO restriction C
  • replaceability condition according to the given definition can be demonstrated mathematically in numerous ways.
  • Known automated processes include, for example, BDD, ROBDD, ATPG, SAT or simulation-based processes.
  • the restriction C is determined from the definition given in that the systems on Values potentially occurring at their outputs are examined. Those input values are then added to the restriction C which - regardless of internal states - result in an output value which under no circumstances can be generated by the other system.
  • library cells are an ideal application scenario for the invention presented here.
  • FIG. 1 shows an example of an implementation verification of a digital technical system, e.g. for the production of an ASIC, the interaction of the different tools.
  • the comparison task consists of checking the RTL synthesis input (here as FSMO) against the synthesis result 'netlist' (here as FSM1) for functional equality, 'netlist' and 'RTL' provide the user files UF (User Files), whereby 'netlist' is synthesized from 'RTL' with the help of the synthesis library '.db''syn'.
  • the library '.db' contains the synthesis models of the library cells and O co fv> N)

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Radar Systems Or Details Thereof (AREA)

Abstract

Selon la présente invention, une comparaison entre deux systèmes techniques, qui selon l'opinion générale ne peut être réalisée, peut être établie de façon extrêmement simple et techniquement faisable, des parties d'un ou de deux systèmes étant remplacées de manière ciblée. Ces remplacements sont effectués de façon contrôlée par la surveillance d'une condition de remplaçabilité sous certaines réserves. La surveillance de cette condition de remplaçabilité ainsi que l'établissement et la surveillance des réserves nécessaires s'effectuent automatiquement. Ainsi, une comparaison entre les deux systèmes est établie, sans perte de précision, sur la base des remplacements des parties de système.
EP01971643A 2000-09-05 2001-08-23 Procede et agencement pour la comparaison entre deux systemes techniques par le biais de remplacements de systemes Withdrawn EP1323080A2 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE10043759 2000-09-05
DE10043759 2000-09-05
DE10105584 2001-02-07
DE10105584A DE10105584A1 (de) 2000-09-05 2001-02-07 Verfahren und Anordnung zum Vergleich technischer Systeme unter Verwendung von Systemersetzungen
PCT/DE2001/003219 WO2002021344A2 (fr) 2000-09-05 2001-08-23 Procede et agencement pour la comparaison entre deux systemes techniques par le biais de remplacements de systemes

Publications (1)

Publication Number Publication Date
EP1323080A2 true EP1323080A2 (fr) 2003-07-02

Family

ID=26006935

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01971643A Withdrawn EP1323080A2 (fr) 2000-09-05 2001-08-23 Procede et agencement pour la comparaison entre deux systemes techniques par le biais de remplacements de systemes

Country Status (3)

Country Link
US (1) US7082586B2 (fr)
EP (1) EP1323080A2 (fr)
WO (1) WO2002021344A2 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7216294B2 (en) * 2001-09-04 2007-05-08 Microsoft Corporation Method and system for predicting optimal HTML structure without look-ahead
DE10239782A1 (de) * 2002-08-29 2004-03-18 Infineon Technologies Ag Verfahren und Vorrichtung zur Verifikation von digitalen Schaltungen
US7415693B1 (en) * 2004-05-21 2008-08-19 Altera Corporation Method and apparatus for reducing synthesis runtime
US9189581B2 (en) 2012-07-30 2015-11-17 Synopsys, Inc. Equivalence checking between two or more circuit designs that include division circuits

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0828215B1 (fr) 1996-09-05 2002-05-15 Siemens Aktiengesellschaft Procédé de vérification par un ordinateur d'un programme écrit dans un langage pour automate programmable
WO1999050766A1 (fr) 1998-03-30 1999-10-07 Siemens Aktiengesellschaft Procede de comparaison de circuits electriques
WO2000026825A1 (fr) 1998-11-03 2000-05-11 Siemens Aktiengesellschaft Procede et dispositif pour la comparaison de systemes techniques

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0221344A2 *

Also Published As

Publication number Publication date
US7082586B2 (en) 2006-07-25
US20040039541A1 (en) 2004-02-26
WO2002021344A3 (fr) 2003-03-06
WO2002021344A2 (fr) 2002-03-14

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